CY62147VL-70ZI [CYPRESS]
Standard SRAM, 256KX16, 150ns, CMOS, PDSO44, TSOP2-44;
| 型号： | CY62147VL-70ZI |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 256KX16, 150ns, CMOS, PDSO44, TSOP2-44 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总11页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
CY62147V MoBL™
256K x 16 Static RAM
disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Features
• Low voltage range:
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O through I/O ), is
1.8V–3.6V
—
• Ultra low active, standby power
0
7
written into the location specified on the address pins (A
0
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
through A ). If Byte High Enable (BHE) is LOW, then data
17
from I/O pins (I/O through I/O ) is written into the location
8
15
specified on the address pins (A through A ).
0
17
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
Functional Description
The CY62147V is a high-performance CMOS static RAM or-
ganized as 262,144 words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL™) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption by 99% when addresses are not toggling.
The device can also be put into standby mode when deselec-
tected (CE HIGH) or when CE is LOW and both BLE and BHE
pins will appear on I/O to I/O . If Byte High Enable (BHE) is
0
7
LOW, then data from memory will appear on I/O to I/O . See
8
15
the truth table at the back of this data sheet for a complete
description of read and write modes.
The 62147V MoBL SRAM has an extremely wide operating
voltage range. The datasheet has been specified to accurately
describe the device behavior at three common voltage ranges
(3.6 – 2.7, 2.7 – 2.3, 2.3 – 1.8)
are HIGH. The input/output pins (I/O through I/O ) are
placed in a high impedance state when: deselected (CE
HIGH), outputs are disabled (OE HIGH), BHE and BLE are
0
15
The CY62147V is available in 48-ball FBGA and standard
44-pin TSOP Type II (forward pinout) packaging.
Logic Block Diagram
Pin
Configurations
TSOP II (Forward)
Top View
44
1
A
4
A
5
43
42
41
40
39
38
A
A
2
3
4
5
6
3
6
DATA IN DRIVERS
A
A
2
7
OE
A
1
A9
BHE
BLE
I/O
I/O
I/O
A
0
A8
A7
A6
A5
A4
A3
CE
I/O
7
0
15
37
36
35
34
33
I/O
I/O
8
1
2
14
13
12
256K x 16
9
10
11
12
13
I/O
V
SS
RAM Array
1024 X 4096
I/O
I/O0 – I/O7
I/O8 – I/O15
3
CC
V
SS
V
V
CC
A2
A1
A0
I/O
32
I/O
I/O
4
5
6
7
11
10
I/O
I/O
I/O
31
30
29
28
14
15
16
I/O
I/O
9
8
WE 17
NC
18
27
26
25
A
A
8
16
A
19
A
9
COLUMN DECODER
15
A
20
21
22
A
14
10
A
A
12
24
23
11
13
A
A
17
BHE
WE
CE
62147V–2
OE
BLE
CE
Power Down
Circuit
62147V–1
BHE
BLE
MoBL and More Battery Life are trademarks of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
July 16, 1999
CY62147V MoBL™
PRELIMINARY
Pin Configuration (continued)
FBGA
Top View
4
3
1
2
5
6
A
A
2
A
NC
OE
BLE
0
A
B
C
1
A
A
I/O BHE
CE
I/O
I/O
0
4
3
8
A
A
I/O
I/O
I/O
2
5
6
10
9
1
A
V
V
I/O
I/O
3
A17
NC
CC
D
E
F
SS
7
11
A
V
CC
V
I/O
I/O
SS
16
12
4
A
A
I/O
I/O
I/O
I/O
6
14
15
13
5
14
A
A
G
H
I/O
I/O
7
NC
WE
13
12
15
A
A
9
A
A
8
NC
NC
10
11
62147V–3
[1]
DC Input Voltage .................................... −0.5V to V + 0.5V
Maximum Ratings
CC
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-Up Current.................................................... >200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
Range
Industrial
Ambient Temperature
V
CC
DC Voltage Applied to Outputs
[1]
–40°C to +85°C
1.8V to 3.6V
in High Z State ....................................–0.5V to V + 0.5V
CC
Product Portfolio
Power Dissipation (Industrial)
Product
V
Range
Speed
Operating (I
)
Standby (I
)
CC
CC
SB2
[2]
[2]
[2]
Min.
2.7V
2.3V
1.8V
Typ.
Max.
3.6V
2.7V
2.3V
Typ
7
Maximum
15 mA
10 mA
7 mA
Typ
2 µA
Maximum
20 µA
CY62147V
3.0V
2.5V
2.0V
70 ns
85 ns
CY62147V
CY62147V
Shaded area contains advance information.
Notes:
5
18 µA
150 ns
3
15 µA
1. VIL(min) = –2.0V for pulse durations less than 20 ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ, TA = 25°C.
2
CY62147V MoBL™
PRELIMINARY
Electrical Characteristics Over the Operating Range
CY62147V
[2]
Parameter
Description
Test Conditions
Min.
2.4
Typ.
Max.
Unit
V
V
Output HIGH Voltage
I
I
I
I
I
I
= –1.0 mA
= –0.1 mA
= –0.1 mA
= 2.1 mA
= 0.1 mA
= 0.1 mA
V
V
V
V
V
V
V
= 2.7V
= 2.3V
= 1.8V
= 2.7V
= 2.3V
= 1.8V
= 3.6V
OH
OH
OH
OH
OL
OL
OL
CC
CC
CC
CC
CC
CC
CC
2.0
V
1.5
V
V
Output LOW Voltage
Input HIGH Voltage
0.4
0.4
0.2
V
OL
V
V
V
V
2.2
2.0
1.4
V
V
IH
CC
+0.5V
V
V
= 2.7V
= 2.3V
V
V
V
CC
CC
CC
+0.5V
V
CC
+0.3V
0.8
0.6
0.4
+1
Input LOW Voltage
V
V
V
= 2.7V
= 2.3V
= 1.8V
–0.5
–0.5
–0.5
–1
V
V
IL
CC
CC
CC
V
I
I
Input Load Current
GND < V < V
CC
±1
+1
µA
µA
IX
I
Output Leakage Current
GND < V < V , Output
–1
+1
OZ
O
CC
Disabled
I
V
Operating Supply
I
= 0 mA,
V
V
V
= 3.6V
= 2.7V
= 2.3V
7
5
3
1
15
10
7
mA
mA
mA
mA
CC
CC
OUT
CC
CC
CC
Current
f = f
CMOS levels
= 1/t
,
RC
MAX
I
= 0 mA, f = 1 MHz, CMOS
2
OUT
Levels
I
I
Automatic CE
Power-Down Current—
CMOS Inputs
CE > V – 0.3V,
100
µA
SB1
CC
V
V
> V – 0.3V or
IN
IN
CC
< 0.3V, f = f
MAX
Automatic CE
Power-Down Current—
CMOS Inputs
CE > V – 0.3V
L
2
2
50
20
µA
µA
SB2
CC
V
> V – 0.3V
IN CC
V
3.6V
=
=
=
LL
CC
or V < 0.3V, f = 0
IN
V
2.7V
LL
LL
2
2
18
15
µA
µA
CC
V
CC
2.3V
Shaded area contains advance information.
Capacitance[3]
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
C
C
Input Capacitance
Output Capacitance
6
8
pF
pF
IN
A
V
= 3.0V
CC
OUT
Notes:
3. Tested initially and after any design or process changes that may affect these parameters.
3
CY62147V MoBL™
PRELIMINARY
AC Test Loads and Waveforms
R1
R1
VCC
Vcc
OUTPUT
ALL INPUT PULSES
OUTPUT
VCC Typ
GND
90%
90%
10%
10%
R2
5 pF
R2
30 pF
< 5 ns
INCLUDING
JIG AND
SCOPE
< 5 ns
INCLUDING
JIG AND
SCOPE
(a)
C62147V–5
(b)
C62147V–4
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
3.0V
1105
1550
645
2.5V
16670
15380
8000
2.0V
UNIT
Ohms
Ohms
Ohms
Volts
R1
R2
15294
11300
6500
R
V
TH
1.75V
1.2V
0.85V
TH
Shaded area contains advance information.
Data Retention Characteristics (Over the Operating Range)
[2]
Parameter
Description
Conditions
Min.
1.0
Typ.
Max.
3.6
Unit
V
V
V
for Data Retention
CC
DR
I
Data Retention Current
V
= 1.0V
CC
L/
LL
0.2
5.5
µA
µA
CCDR
CE > V – 0.3V,
CC
V
> V – 0.3V or
IN
CC
V
< 0.3V
IN
No input may exceed
+ 0.3V
V
CC
[3]
t
t
Chip Deselect to Data
Retention Time
0
ns
ns
CDR
Operation Recovery Time
t
RC
R
Data Retention Waveform
DATA RETENTION MODE
> 1.0 V
1.6V
1.6V
V
V
CC
DR
t
t
R
CDR
CE
C62147V–6
4
CY62147V MoBL™
PRELIMINARY
[4]
Switching Characteristics Over the Operating Range
(2.7V–3.6V
Operation)
(2.3V–2.7V
Operation)
(1.8V–2.3V
Operation)
Parameter
Description
Min.
Max.
Min.
Max.
Min.
150
10
Max.
Unit
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
70
10
85
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
70
85
150
AA
Data Hold from Address Change
CE LOW to Data Valid
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
70
35
85
50
150
100
OE LOW to Data Valid
[5, 6]
OE LOW to Low Z
5
10
0
5
10
0
5
10
0
[6]
OE HIGH to High Z
25
25
35
35
50
50
[5]
CE LOW to Low Z
[5, 6]
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
BHE / BLE LOW to Data Valid
BHE / BLE LOW to Low Z
BHE / BLE HIGH to High Z
70
70
85
85
150
150
PD
DBE
LZBE
HZBE
5
5
5
25
35
50
[7, 8]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
70
60
60
0
85
75
75
0
150
100
100
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
SCE
AW
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
HA
0
0
0
SA
50
60
30
0
65
75
50
0
100
100
80
PWE
BW
BHE / BLE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
SD
0
HD
[5, 6]
WE LOW to High Z
25
35
70
HZWE
LZWE
[5]
WE HIGH to Low Z
10
10
10
Shaded area contains advance information.
Notes:
4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC typ., and output loading of the
specified IOL/IOH and 30-pF load capacitance.
5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
6.
tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
8. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
5
CY62147V MoBL™
PRELIMINARY
Switching Waveforms
[9, 10]
Read Cycle No. 1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
C62147V–7
[10, 11]
Read Cycle No. 2
t
RC
CE
t
PD
t
t
HZCE
ACE
OE
t
HZOE
t
DOE
BHE/BLE
t
LZOE
t
HZBE
t
DBE
t
LZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PU
V
ICC
ISB
CC
SUPPLY
CURRENT
50%
50%
C62147V–8
Notes:
9. Device is continuously selected. OE, CE = VIL
10. WE is HIGH for read cycle.
.
11. Address valid prior to or coincident with CE transition LOW.
6
CY62147V MoBL™
PRELIMINARY
Switching Waveforms (continued)
[7, 12, 13]
Write Cycle No. 1 (WE Controlled)
t
WC
ADDRESS
CE
t
t
AW
HA
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
SD
t
HD
DATA VALID
IN
DATA I/O
NOTE14
t
HZOE
C62147V–9
[7, 12, 13]
Write Cycle No. 2 (CE Controlled)
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
t
BW
BHE/BLE
WE
t
PWE
t
t
HD
SD
DATA I/O
DATA VALID
IN
C62147V–10
Notes:
12. Data I/O is high impedance if OE = VIH
.
13. If CEgoes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
14. During this period, the I/Os are in output state and input signals should not be applied.
7
CY62147V MoBL™
PRELIMINARY
Switching Waveforms (continued)
[8, 13]
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
t
HA
AW
t
BW
BHE/BLE
t
SA
WE
t
t
HD
SD
DATA I/O
DATA VALID
NOTE 14
IN
t
t
LZWE
HZWE
C62147V–11
8
CY62147V MoBL™
PRELIMINARY
Typical DC and AC Characteristics
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
NORMALIZED
vs. AMBIENT TEMPERATURE
STANDBY CURRENT
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.0
0.75
0.5
1.4
1.2
3.0
2.5
2.0
1.5
1.0
V
=V typ.
CC
CC
T =25 C
°
A
V
=V typ.
1.0
0.8
0.6
IN
CC
I
I
SB
CC
V
=VCC typ.
IN
T =25 C
°
A
0.5
0.4
0.25
0
0.2
0.0
0.0
-0.5
1.7
2.2
2.7
3.2
3.7
55
−
25
105
1.7
2.2
2.7
3.2
3.7
AMBIENT TEMPERATURE ( C)
SUPPLY VOLTAGE (V)
°
SUPPLY VOLTAGE (V)
NORMALIZED STANDBY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED I vs.CYCLETIME
CC
1.50
1.00
0.50
0.10
1.4
1.2
V
CC
=3.6V
I
SB2
T =25 C
°
A
1.0
0.8
0.6
V
IN
=VCC typ.
T =25 C
°
A
0.4
0.2
0.0
5
1
15
10
1.0
3.7
2.8
SUPPLY VOLTAGE (V)
1.9
CYCLE FREQUENCY (MHz)
Truth Table
CE
H
L
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
Mode
Power
High Z
High Z
Deselect/Power-Down
Deselect/Power-Down
Read
Standby (I
Standby (I
)
SB
X
X
H
H
)
SB
L
H
L
L
L
Data Out(I/O – I/O
)
Active (I
Active (I
)
CC
O
15
L
H
L
H
L
Data Out(I/O – I/O );
Read
)
CC
O
7
I/O – I/O in High Z
8
15
L
H
L
L
H
Data Out(I/O – I/O );
Read
Active (I
)
CC
8
15
I/O – I/O in High Z
0
7
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z
Deselect/Output Disabled
Deselect/Output Disabled
Deselect/Output Disabled
Write
Active (I
Active (I
Active (I
Active (I
Active (I
)
CC
High Z
High Z
)
CC
)
CC
L
Data In(I/O – I/O
)
)
CC
O
15
L
H
Data In(I/O – I/O );
Write
)
CC
O
7
I/O – I/O in High Z
8
15
L
L
X
L
H
Data In(I/O – I/O );
Write
Active (I
)
CC
8
15
I/O – I/O in High Z
0
7
9
CY62147V MoBL™
PRELIMINARY
Ordering Information
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
Package Type
70
CY62147VL-70ZI
CY62147VL-70BAI
CY62147VLL-70ZI
CY62147VLL-70BAI
Z44
BA49
Z44
44-Pin TSOP II
48-Ball Fine Pitch BGA
Industrial
70
44-Pin TSOP II
BA49
48-Ball Fine Pitch BGA
Shaded area contains advance information.
Document #: 38–00757
Package Diagrams
48-Ball (7.00 mm x 8.5 mm x 1.5 mm) Thin BGA BA49
51-85106-A
10
CY62147V MoBL™
PRELIMINARY
Package Diagrams (continued)
44-Pin TSOP II Z44
51-85087-A
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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