概述
规格参数
数据手册
替代型号CY62148BLL-70SI 概述
512K x 8 Static RAM 512K ×8静态RAM RAM芯片 SRAM
CY62148BLL-70SI 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Obsolete |
| 零件包装代码： | SOIC | 包装说明： | 0.450 INCH, PLASTIC, SOIC-32 |
| 针数： | 32 | Reach Compliance Code： | not_compliant |
| ECCN代码： | 3A991.B.2.A | HTS代码： | 8542.32.00.41 |
| 风险等级： | 5.64 | 最长访问时间： | 70 ns |
| I/O 类型： | COMMON | JESD-30 代码： | R-PDSO-G32 |
| JESD-609代码： | e0 | 长度： | 20.447 mm |
| 内存密度： | 4194304 bit | 内存集成电路类型： | STANDARD SRAM |
| 内存宽度： | 8 | 湿度敏感等级： | 3 |
| 功能数量： | 1 | 端子数量： | 32 |
| 字数： | 524288 words | 字数代码： | 512000 |
| 工作模式： | ASYNCHRONOUS | 最高工作温度： | 85 °C |
| 最低工作温度： | -40 °C | 组织： | 512KX8 |
| 输出特性： | 3-STATE | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | SOP | 封装等效代码： | SOP32,.56 |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE |
| 并行/串行： | PARALLEL | 峰值回流温度（摄氏度）： | 225 |
| 电源： | 5 V | 认证状态： | Not Qualified |
| 座面最大高度： | 2.997 mm | 最大待机电流： | 0.00002 A |
| 最小待机电流： | 2 V | 子类别： | SRAMs |
| 最大压摆率： | 0.02 mA | 最大供电电压 (Vsup)： | 5.5 V |
| 最小供电电压 (Vsup)： | 4.5 V | 标称供电电压 (Vsup)： | 5 V |
| 表面贴装： | YES | 技术： | CMOS |
| 温度等级： | INDUSTRIAL | 端子面层： | Tin/Lead (Sn/Pb) |
| 端子形式： | GULL WING | 端子节距： | 1.27 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | 30 |
| 宽度： | 11.303 mm | Base Number Matches： | 1 |
CY62148BLL-70SI 数据手册
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PDF下载CY62148B MoBL™
512K x 8 Static RAM
an automatic power-down feature that reduces power con-
sumption by more than 99% when deselected.
Features
• 4.5V–5.5V operation
• Low active power
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location speci-
fied on the address pins (A0 through A18).
— Typical active current: 2.5 mA @ f = 1 MHz
— Typical active current: 12.5 mA @ f = fmax
• Low standby current
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• CMOS for optimum speed/power
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH for read. Under these conditions, the con-
tents of the memory location specified by the address pins will
appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
Functional Description
The CY62148B is a high-performance CMOS static RAM or-
ganized as 512K words by 8 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE), and three-state drivers. This device has
The CY62148B is available in a standard 32-pin 450-mil-wide
body width SOIC, 32-pin TSOP II, and 32-pin Reverse TSOP
II packages.
Logic Block Diagram
Pin
Configuration
Top View
SOIC
TSOP II
VCC
A15
A18
A17
A16
32
31
30
1
2
3
4
5
6
7
A14
A12
A7
A6
29
28
27
26
WE
A13
A8
A5
A9
I/O
25
24
23
22
21
A4
A3
A2
0
8
9
10
11
12
13
A11
INPUT BUFFER
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
I/O
I/O
1
2
A
0
A1
A
1
A0
I/O0
A
4
20
19
A
5
6
I/O1
I/O2
GND
14
15
16
A
I/O
I/O
I/O
18
17
3
4
5
512 x 256 x 8
ARRAY
A
7
A
12
A
14
Top View
Reverse
TSOP II
A
16
A
17
I/O3
GND
I/O2
I/O1
17
18
19
20
21
22
16
15
14
13
12
11
10
9
8
7
6
5
I/O
6
7
I/O4
I/O5
POWER
DOWN
COLUMN
DECODER
CE
I/O0
I/O6
I/O7
CE
I/O
WE
A0
A1
A2
A3
A4
A5
A6
A7
A12
OE
23 A10
24
OE
A11
A9
A8
A13
25
26
27
28
29
30
4
3
2
1
WE
A18
A15
Vcc
A14
A16
A17
31
32
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05039 Rev. *B
October 8, 2001
CY62148B MoBL™
Product Portfolio
Power Dissipation
Operating, Icc
f = fmax
Standby (ISB2)
VCC Range
Typ.
Product
Min.
Max.
Speed
Temp.
Com’l
Ind’l
Typ.[3]
Max.
Typ.[3]
Max.
CY62148BLL
4.5 V
5.0V
5.5V
70 ns
12.5 mA
20 mA
4 µA
20 µA
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Static Discharge Voltage...............................................2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage on VCC to Relative GND ....... –0.5V to +7.0V
Ambient
Temperature[2]
0°C to +70°C
VCC
DC Voltage Applied to Outputs
Range
Commercial
Industrial
in High Z State[1].....................................–0.5V to VCC +0.5V
4.5V–5.5V
DC Input Voltage[1] .................................–0.5V to VCC +0.5V
–40°C to +85°C
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the “Instant On” case temperature
3. Typical values are measured at VCC = 5V, TA = 25°C, and are included for reference only and are not tested or guaranteed.
Document #: 38-05039 Rev. *B
Page 2 of 11
CY62148B MoBL™
Electrical Characteristics Over the Operating Range
CY62148B-70
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Test Conditions
VCC = Min., IOH = – 1 mA
VCC = Min., IOL = 2.1 mA
Min.
Typ.[3]
Max.
Unit
V
2.4
0.4
VCC+0.3
0.8
V
VIH
2.2
–0.3
–1
V
VIL
V
IIX
GND ≤ VI ≤ VCC
+1
µA
µA
IOZ
Output Leakage
Current
GND ≤ VI ≤ VCC, Output Disabled
–1
+1
ICC
VCC Operating
Supply Current
f = fMAX = 1/tRC
f = 1 MHz
Com/Ind’l
IOUT =0 mA
VCC = Max.,
12.5
2.5
20
mA
mA
ISB1
Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC
CE ≥ VIH
,
Com/
Ind’l
1.5
mA
V
V
IN ≥ VIH or
IN ≤ VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC
,
Com/
4
20
µA
CE ≥ VCC – 0.3V, Ind’l
IN ≥ VCC – 0.3V,
or VIN ≤ 0.3V, f =0
V
Capacitance[4]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
pF
CIN
Input Capacitance
Output Capacitance
6
8
COUT
pF
AC Test Loads and Waveforms
R1 1800Ω
R1 1800 Ω
5V
ALL INPUT PULSES
5V
3.0V
GND
OUTPUT
OUTPUT
R2
990Ω
90%
10%
90%
10%
R2
990Ω
100 pF
5 pF
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
≤ 3 ns
≤ 3 ns
(b)
(a)
Equivalent to:
THEVENIN EQUIVALENT
639Ω
1.77V
OUTPUT
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05039 Rev. *B
Page 3 of 11
CY62148B MoBL™
Switching Characteristics[5] Over the Operating Range
62148BLL-70
Parameter
Description
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
70
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[6]
OE HIGH to High Z[6, 7]
CE LOW to Low Z[6]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
70
tOHA
tACE
70
35
tDOE
tLZOE
5
10
0
tHZOE
25
25
70
tLZCE
tHZCE
tPU
tPD
WRITE CYCLE[8]
tWC
tSCE
tAW
tHA
Write Cycle Time
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tSA
0
tPWE
tSD
55
30
0
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[6]
tHD
tLZWE
5
tHZWE
WE LOW to High Z[6, 7]
25
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
OL/IOH and 100-pF load capacitance.
I
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, and WELOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Document #: 38-05039 Rev. *B
Page 4 of 11
CY62148B MoBL™
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
Description
VCC for Data Retention
Data Retention Current
Conditions
Min.
Typ.[3]
Max.
Unit
V
2.0
Com’l LL
Ind’l LL
No input may exceed
VCC + 0.3V
VCC = VDR = 3.0V
CE > VCC – 0.3V
VIN > VCC – 0.3V or
VIN < 0.3V
20
20
µA
µA
ns
[4]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
[9]
tR
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
3.0V
3.0V
V
DR
> 2V
V
CC
t
t
R
CDR
CE
Switching Waveforms
Read Cycle No.1[10, 11]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[11, 12]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
V
CC
50%
50%
SUPPLY
I
CURRENT
SB
Notes:
9. Full Device operatin requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at Vcc(min) > 100 µs.
10. Device is continuously selected. OE, CE = VIL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05039 Rev. *B
Page 5 of 11
CY62148B MoBL™
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[13]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14]
t
WC
ADDRESS
CE
t
SCE
tHZCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 15
t
HZOE
Notes:
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
14. Data I/O is high-impedance if OE = VIH
.
15. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05039 Rev. *B
Page 6 of 11
CY62148B MoBL™
Switching Waveforms (continued)
Write Cycle No.3 (WE Controlled, OE LOW)[13, 14]
t
WC
ADDRESS
t
SCE
CE
tHZCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 15
DATAI/O
DATA VALID
t
t
LZWE
HZWE
Truth Table
CE
H
L
OE
WE
I/O0 – I/O7
High Z
Mode
Power
X
L
X
H
L
Power-Down
Read
Standby (ISB
)
Data Out
Data In
High Z
Active (ICC
Active (ICC
Active (ICC)
)
L
X
H
Write
)
L
H
Selected, Outputs Disabled
Ordering Information
Speed
(ns)
Package
Operating
Range
Ordering Code
CY62148BLL-70SC
CY62148BLL-70ZC
CY62148BLL-70ZRC
CY62148BLL-70SI
CY62148BLL-70ZI
CY62148BLL-70ZRI
Name
Package Type
32-Lead (450-Mil) Molded SOIC
32-Lead TSOP II
70
S34
Commercial
ZS32
ZU32
S34
32-Lead RTSOP II
32-Lead (450-Mil) Molded SOIC
32-Lead TSOP II
Industrial
ZS32
ZU32
32-Lead RTSOP II
Document #: 38-05039 Rev. *B
Page 7 of 11
CY62148B MoBL™
Package Diagrams
32-Lead (450 MIL) Molded SOIC S34
51-85081-A
Document #: 38-05039 Rev. *B
Page 8 of 11
CY62148B MoBL™
Package Diagrams (continued)
32-Lead
TSOP II ZS32
51-85095
Document #: 38-05039 Rev. *B
Page 9 of 11
CY62148B MoBL™
Package Diagrams (continued)
32-Lead Reverse Thin Small Outline Package Type II ZU32
51-85138-**
Document #: 38-05039 Rev. *B
Page 10 of 11
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62148B MoBL™
Document Title: CY62148B 512K x 8 Static RAM
Document Number: 38-05039
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
106833
106970
109766
Description of Change
05/01/01
07/16/01
10/09/01
SZV
GAV
MGN
Change from Spec number 38-01104 to 38-05039
Modified annotations on Pin Configurations; tSD = 30 ns
Remove 55-ns devices
*A
*B
Document #: 38-05039 Rev. *B
Page 11 of 11
CY62148BLL-70SI 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| CY62148BNLL-70SXI | CYPRESS | 4-Mbit (512K x 8) Static RAM | 类似代替 |
|
| CY62148BLL-70SC | CYPRESS | 512K x 8 Static RAM | 功能相似 |
|
| CY62148ELL-45SXI | CYPRESS | Standard SRAM, 512KX8, 45ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, SOIC-32 | 功能相似 |
|
CY62148BLL-70SI 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| CY62148BLL-70SIT | CYPRESS | Standard SRAM, 512KX8, 70ns, CMOS, PDSO32, 0.450 INCH, PLASTIC, SOIC-32 | 获取价格 |
|
| CY62148BLL-70SXI | CYPRESS | 4-Mbit (512K x 8) Static RAM | 获取价格 |
|
| CY62148BLL-70ZC | CYPRESS | 512K x 8 Static RAM | 获取价格 |
|
| CY62148BLL-70ZCT | CYPRESS | Standard SRAM, 512KX8, 70ns, CMOS, PDSO32, TSOP2-32 | 获取价格 |
|
| CY62148BLL-70ZI | CYPRESS | 512K x 8 Static RAM | 获取价格 |
|
| CY62148BLL-70ZI | ROCHESTER | Standard SRAM, 512KX8, 70ns, CMOS, PDSO32, TSOP2-32 | 获取价格 |
|
| CY62148BLL-70ZIT | CYPRESS | 暂无描述 | 获取价格 |
|
| CY62148BLL-70ZRC | CYPRESS | 512K x 8 Static RAM | 获取价格 |
|
| CY62148BLL-70ZRCT | CYPRESS | Standard SRAM, 512KX8, 70ns, CMOS, PDSO32, REVERSE, TSOP2-32 | 获取价格 |
|
| CY62148BLL-70ZRI | CYPRESS | 512K x 8 Static RAM | 获取价格 |
|
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