CY62512VLL-70ZI [CYPRESS]
Standard SRAM, 64KX8, 70ns, CMOS, PDSO32;
| 型号： | CY62512VLL-70ZI |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 64KX8, 70ns, CMOS, PDSO32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总7页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
fax id: 1098
PRELIMINARY
CY62512V
64K x 8 Static RAM
er-down feature that reduces power consumption by more
than 99% when deselected.
Features
• 2.7V–3.6V operation
Writing to the device is accomplished by taking chip enable
• CMOS for optimum speed/power
• Low active power (70 ns, LL version)
— 144 mW (max.)
one (CE ) and write enable (WE) inputs LOW and chip enable
1
two (CE ) input HIGH. Data on the eight I/O pins (I/O through
2
0
I/O ) is then written into the location specified on the address
7
pins (A through A ).
0
15
• Low standby power (70 ns, LL version)
Reading from the device is accomplished by taking chip en-
able one (CE ) and output enable (OE) LOW while forcing
— 54 W (max.)
µ
1
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
write enable (WE) and chip enable two (CE ) HIGH. Under
2
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
• Easy memory expansion with CE , CE , and OE options
1
2
The eight input/output pins (I/O through I/O ) are placed in a
0
7
Functional Description
high-impedance state when the device is deselected (CE
1
HIGH or CE LOW), the outputs are disabled (OE HIGH), or
2
The CY62512V is a high-performance CMOS static RAM or-
ganized as 65,536 words by 8 bits. Easy memory expansion
during a write operation (CE LOW, CE HIGH, and WE LOW).
1
2
The CY62512V is available in standard 32-pin TSOP type I
package.
is provided by an active LOW chip enable (CE ), an active
1
HIGH chip enable (CE ), an active LOW output enable (OE),
2
and three-state drivers. This device has an automatic pow-
Logic Block Diagram
Pin
Configurations
A
A
A
A
1
2
32
31
11
OE
A
9
8
10
3
4
5
6
7
8
30
29
28
CE
1
I/O
I/O
I/O
13
7
6
5
WE
CE
A
27
26
25
24
23
22
21
20
19
18
2
TSOP I
Top View
(not to scale)
15
I/O
I/O
4
3
V
CC
NC
NC
9
GND
I/O
10
11
12
13
14
15
16
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
A
A
A
7
14
I/O
12
0
INPUT BUFFER
A
6
I/O
I/O
1
2
A
A
5
4
A
0
17
A
1
A
2
A
3
4
A
I/O
I/O
I/O
3
4
5
256 x 256 x 8
ARRAY
A
6
5
A
A
7
8
A
I/O
6
7
POWER
DOWN
COLUMN
DECODER
CE
1
CE
2
I/O
WE
62512V-1
OE
Selection Guide
CY62512V–55
55
CY62512V–70
70
Maximum Access Time (ns)
Maximum Operating Current
Maximum CMOS Standby Current
40 mA
100 µA
15 µA
40 mA
100 µA
15 µA
L
Com’l
Ind’l
LL
LL
30 µA
30 µA
Shaded areas contain advance information.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
April 6, 1998
CY62512V
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Ambient
[2]
Supply Voltage on V to Relative GND........ –0.5V to +4.6V
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40C to +85C
V
CC
CC
DC Voltage Applied to Outputs
2.7V–3.6V
[1]
in High Z State .....................................–0.5V to V +0.5V
CC
[1]
DC Input Voltage ..................................–0.5V to V +0.5V
CC
Electrical Characteristics Over the Operating Range
62512V
[3]
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
= Min., I = –1.0 mA
Min.
Typ.
Max.
Unit
V
V
V
V
V
2.4
V
V
V
OH
OL
IH
CC
CC
OH
= Min., I = 2.1mA
0.4
OL
2.0
V
+
CC
0.3
[1]
V
Input LOW Voltage
–0.3
–1
0.8
+1
+1
V
IL
I
I
Input Load Current
GND ≤ V ≤ V
CC
±0.1
±0.1
µA
µA
IX
I
Output Leakage
Current
GND ≤ V ≤ V , Output Disabled
–1
OZ
I
CC
I
I
V
Operating
V
= Max.
,
= 0 mA,
20
20
40
40
mA
mA
CC
CC
CC
Supply Current
I
OUT
f = f
= 1/t
MAX
RC
Automatic CE
Power-Down Current
—TTL Inputs
Max. V , CE ≥ V
or CE < V ,
V
V
15
15
300
300
µA
µA
SB1
SB2
CC
1
IH
2 IL
≥ V or
IH
IN
IN
≤ V , f = f
IL
MAX
I
Automatic CE
Power-Down Current
—CMOS Inputs
Max. V
CE ≥ V – 0.3V,
or CE ≤ 0.3V,
V
,
L
0.4
0.4
0.4
100
15
µA
µA
µA
CC
1 CC
Com’l
Ind
LL
LL
2
≥ V – 0.3V,
30
IN
CC
or V ≤ 0.3V, f=0
IN
Capacitance[4]
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
pF
C
C
Input Capacitance
Output Capacitance
6
8
IN
A
V
= 3.0V
CC
pF
OUT
Notes:
1.
V
IL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the “instant on” case temperature.
3. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions
(TA = 25°C, VCC=3.0V). Parameters are guaranteed by design and characterization, and not 100% tested.
4. Tested initially and after any design or process changes that may affect these parameters.
2
CY62512V
PRELIMINARY
Switching Characteristics[5] Over the Operating Range
62512V–55
Min. Max.
62512V–70
Min. Max.
Parameter
Description
Unit
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
55
10
70
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
55
70
AA
Data Hold from Address Change
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
CE LOW to Data Valid, CE HIGH to Data Valid
55
25
70
35
1
2
OE LOW to Data Valid
[7]
OE LOW to Low Z
10
10
0
10
10
0
[6, 7]
OE HIGH to High Z
20
20
55
25
25
70
[7]
CE LOW to Low Z, CE HIGH to Low Z
1
2
[6, 7]
CE HIGH to High Z, CE LOW to High Z
1
2
CE LOW to Power-Up, CE HIGH to Power-Up
1
2
CE HIGH to Power-Down, CE LOW to Power-Down
PD
1
2
[8]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
CE LOW to Write End, CE HIGH to Write End
55
45
45
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
SCE
AW
1
2
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
HA
0
0
SA
40
25
0
55
30
0
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
HD
[7]
WE HIGH to Low Z
5
5
LZWE
HZWE
[6,7]
WE LOW to High Z
20
25
Shaded areas contain advance information.
Note:
5. Test conditions assume signal transition time of 5ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100pF load capacitance.
6.
tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write,
and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates
the write.
3
CY62512V
PRELIMINARY
Data Retention Characteristics (Over the Operating Range for “L” and “LL” version only)
[3]
Parameter
DR
Description
Conditions
Min.
Typ.
Max.
Unit
V
V
for Data Retention
2.0
V
CC
I
Data Retention Current
L
No input may exceed V + 0.3V
0.4
0.4
0.4
80
12
25
µA
µA
µA
ns
CCDR
CC
V
= V = 3.0V,
CC
DR
Com’l LL
CE > V − 0.3V,
CC
Ind’l
LL
V
> V − 0.3V or
IN
CC
V
< 0.3V
[4]
IN
t
t
Chip Deselect to Data
Retention Time
0
CDR
Operation Recovery
Time
t
ns
R
RC
Data Retention Waveform
DATA RETENTION MODE
3.0V
3.0V
V
DR
> 2V
V
CC
t
t
R
CDR
CE
62512–5
Switching Waveforms
[9,10]
Read Cycle No.1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
62512V-6
[10,11]
Read Cycle No. 2 (OE Controlled)
ADDRESS
t
RC
CE
1
CE
2
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
ISB
t
PU
V
CC
50%
50%
SUPPLY
CURRENT
62512V-7
Notes:
9. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH
.
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
4
CY62512V
PRELIMINARY
Switching Waveforms (continued)
[12,13]
Write Cycle No. 1 (CE or CE Controlled)
1
2
t
WC
ADDRESS
t
SCE
CE
1
t
SA
CE
2
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
62512V-8
[12,13]
WC
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
t
ADDRESS
t
SCE
CE
1
CE
2
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 14
t
HZOE
62512V-9
Note:
12. Data I/O is high impedance if OE = VIH
.
13. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
14. During this period the I/Os are in the output state and input signals should not be applied.
5
CY62512V
PRELIMINARY
Switching Waveforms (continued)
[12,13]
Write Cycle No.3 (WE Controlled, OE LOW)
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 14
DATAI/O
DATA VALID
t
t
LZWE
HZWE
62512V-10
Truth Table
CE
H
X
CE
X
OE
X
WE
I/O – I/O
7
Mode
Power
1
2
0
X
X
H
L
High Z
High Z
Power-Down
Power-Down
Read
Standby (I
Standby (I
)
SB
L
X
)
SB
L
H
L
Data Out
Data In
High Z
Active (I
Active (I
Active (I
)
CC
L
H
X
Write
)
CC
L
H
H
H
Selected, Outputs Disabled
)
CC
Ordering Information
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
Package Type
70
CY62512VLL-70ZC
Z32
32-Lead Thin Small Outline Package
Commercial
Document #: 38–00640
6
CY62512V
PRELIMINARY
Package Diagram
32-Lead Thin Small Outline Package Z32
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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