CY74FCT16245ETPAC [CYPRESS]
Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.240 INCH, 0.0196 INCH PITCH, TSSOP-48;
| 型号： | CY74FCT16245ETPAC |
| 厂家： | 
CYPRESS |
| 描述： | Bus Transceiver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.240 INCH, 0.0196 INCH PITCH, TSSOP-48 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
445T/2
fax id: 7041
CY74FCT16245T/2245T
CY74FCT16445T/2H245T
16-Bit Transceiver
CY74FCT162H245T Features:
Features
Bus hold on data inputs
Eliminates the need for external pull-up or pull-down
resistors
•
•
Low power, pin-compatible replacement for ABT
•
functions
FCT-E speed at 3.2 ns
Power-off disable outputs permits live insertion
Edge-rate control circuitry for significantly improved
noise characteristics
Typical output skew < 250 ps
ESD > 2000V
TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
Industrial temperature range of –40°C to +85°C
•
•
•
Functional Description
These 16-bit transceivers are designed for use in bidirectional
synchronous communication between two buses, where high
speed and low power are required. With the exception of the
CY74FCT16245T, these devices can be operated either as two
independent octals or a single 16-bit transceiver. Direction of
data flow is controlled by (DIR), the Output Enable (OE) trans-
fers data when LOW and isolates the buses when HIGH. The
output buffers are designed with power off disable capability to
allow for live insertion of boards.
•
•
•
•
•
V
= 5V 10%
±
CC
CY74FCT16245T Features:
The CY74FCT16245T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
64 mA sink current, 32 mA source current
•
•
Typical V
A
(ground bounce)<1.0V at V = 5V,
CC
OLP
The CY74FCT162245T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for minimal
T = 25°C
CY74FCT162245T Features:
undershoot
and
reduced
ground
bounce.
The
Balanced output drivers: 24 mA
Reduced system switching noise
•
•
•
CY74FCT162245T is ideal for driving transmission lines.
The CY74FCT16445T is designed for 16-bit operation, reduc-
ing control lines from two OE and two DIR pins to one OE and
one DIR pin to reduce loading.
Typical V
A
(ground bounce) <0.6V at V = 5V,
CC
OLP
T = 25°C
CY74FCT16445T Features:
The CY74FCT162H245T is a 24-mA balanced output part that
has bus hold on the data inputs. The device retains the input’s
last state whenever the input goes to high impedance. This
eliminates the need for pull-up/down resistors and prevents
floating inputs.
64 mA sink current, 32 mA source current
Reduces system loading
•
•
Logic Block Diagrams CY74FCT16245T,CY74FCT162245T,
CY74FCT162H245T
Pin Configuration
SSOP/TSSOP
Top View
DIR
DIR
2
1
OE
OE
1
2
3
4
48
47
46
DIR
B
OE
1
2
1
1
1
A
1
1
1
1
A
A
1
1
1
2
B
2
A
2
1
GND
B
GND
A
45
44
43
42
41
B
B
B
1
1
1
2
2
2
1
3
5
6
7
8
9
1
3
A
A
2
1
1
2
2
2
B
4
A
4
1
1
B
2
V
CC
V
CC
1
16245T
162245T
B
A
5
1
1
5
1
1
A
3
A
3
162H2455T
B
6
A
6
40
39
38
37
36
35
34
B
B
3
1
1
1
3
4
5
2
2
2
GND
GND
10
11
B
A
7
1
1
7
1
1
A
A
4
1
4
2
2
B
8
A
8
12
13
B
B
B
4
B
A
1
2
2
1
2
2
14
15
16
17
18
B
2
A
2
A
A
5
1
5
GND
GND
B
5
33
32
31
30
29
28
27
26
25
B
A
3
2
2
3
2
2
A
A
6
B
4
A
4
1
6
2
2
V
CC
V
CC
B
1
B
1
B
1
B
6
6
7
8
2
2
2
B
5
A
5
19
20
21
22
23
24
2
2
2
2
A
A
7
B
6
A
6
1
7
GND
B
GND
A
B
7
2
2
7
2
7
A
A
8
B
8
A
1
8
2
2
2
8
DIR
2
OE
B
8
FCT16245–3
FCT16245–1
FCT16245–2
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
July 1994 – Revised October 30, 1997
CY74FCT16245T/2245T
CY74FCT16445T/2H245
Logic Block DiagramCY74FCT16445T
Pin Configuration
SSOP/TSSOP
Top View
DIR
1
2
3
4
48
47
46
45
44
43
DIR
OE
OE
B
1
A
1
B
2
A
2
A
1
GND
GND
B
B
B
3
A
3
1
2
5
B
4
A
4
6
A
2
V
CC
V
CC
42
41
7
16445T
B
B
A
5
5
6
8
A
6
9
40
39
38
A
3
GND
GND
10
B
B
3
4
B
B
B
A
7
7
8
9
11
12
13
A
8
37
36
35
34
33
A
4
A
9
14
15
16
17
18
B
A
10
10
GND
GND
B
B
A
A
11
12
11
TO OTHER 12 CHANNELS
FCT16245–4
32
31
30
29
28
27
26
25
12
V
CC
V
CC
B
A
13
19
20
21
22
23
24
13
14
B
A
14
GND
GND
B
A
15
15
B
A
16
16
NC
NC
FCT16245–5
Maximum Ratings[3, 4]
Pin Description
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Name
Description
OE
DIR
A
Three-State Output Enable Inputs (Active LOW)
Direction Control
Storage Temperature ........................ Com’l -55°C to +125°C
Ambient Temperature with
Power Applied.................................... Com’l -55°C to +125°C
[1]
Inputs or Three-State Outputs
[1]
DC Input Voltage ............................................–0.5V to +7.0V
DC Output Voltage..........................................–0.5V to +7.0V
B
Inputs or Three-State Outputs
Function Table[2]
DC Output Current
(Maximum Sink Current/Pin) ........................ –60 to +120 mA
Inputs
Power Dissipation.......................................................... 1.0W
OE
L
DIR
L
Outputs
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Bus B Data to Bus A
Bus A Data to Bus B
High Z State
L
H
Operating Range
H
X
Ambient
Range
Industrial
Temperature
V
CC
–40°C to +85°C
5V ± 10%
Notes:
1. On CY74FCT162H245T these pins have bus hold.
2. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = High Impedance.
3. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range.
4. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
2
CY74FCT16245T/2245T
CY74FCT16445T/2H245
Electrical Characteristics Over the Operating Range
[5]
Parameter
Description
Input HIGH Voltage
Test Conditions
Min.
Typ.
Max.
Unit
V
V
V
V
V
2.0
IH
IL
H
Input LOW Voltage
0.8
V
[6]
Input Hysteresis
100
mV
V
Input Clamp Diode Voltage
Input HIGH Current
V
V
=Min., I =–18 mA
–0.7
–1.2
±1
IK
CC
CC
IN
I
Standard
Bus Hold
Standard
=Max., V =V
CC
µA
IH
I
±100
±1
I
Input LOW Current
V
V
=Max., V =GND
µA
µA
µA
IL
CC
CC
I
Bus Hold
±100
[7]
I
I
Bus Hold Sustain Current on Bus Hold Input
=Min.
V =2.0V
–50
+50
BBH
BBL
I
V =0.8V
I
[7]
I
I
Bus Hold Overdrive Current on Bus Hold Input
V
V
V
=Max., V =1.5V
TBD
±1
mA
µA
µA
BHHO
BHLO
CC
CC
CC
I
I
High Impedance Output Current
(Three-State Output pins)
=Max., V
=Max., V
=2.7V
=0.5V
=GND
OZH
OUT
OUT
I
High Impedance Output Current
(Three-State Output pins)
±1
OZL
[8]
I
I
I
Short Circuit Current
V
V
V
=Max., V
=Max., V
–80
–50
–140
–200
–180
±1
mA
mA
µA
OS
CC
CC
CC
OUT
[8]
Output Drive Current
=2.5V
O
OUT
[9]
Power-Off Disable
=0V, V
≤4.5V
OFF
OUT
Output Drive Characteristics for CY74FCT16245T, CY74FCT16445T
[5]
Parameter
Description
Test Conditions
=Min., I =–3 mA
Min.
2.5
Typ.
Max.
Unit
V
V
Output HIGH Voltage
V
V
V
V
3.5
3.5
3.0
0.2
OH
CC
CC
CC
CC
OH
=Min., I =–15 mA
2.4
V
OH
=Min., I =–32 mA
2.0
V
OH
V
Output LOW Voltage
=Min., I =64 mA
0.55
V
OL
OL
Output Drive Characteristics for CY74FCT162245T, CY74FCT162H245T
[5]
Parameter
Description
Test Conditions
=5V, V =V or V , V
Min.
60
Typ.
Max.
150
Unit
mA
mA
V
[8]
I
Output LOW Current
V
V
V
V
=1.5V
=1.5V
115
–115
3.3
ODL
ODH
CC
CC
CC
CC
IN
IH
IL OUT
[8]
I
Output HIGH Current
Output HIGH Voltage
Output LOW Voltage
=5V, V =V or V , V
IL OUT
–60
2.4
–150
IN
IH
V
V
=Min., I =–24 mA
OH
OH
OL
=Min., I =24 mA
0.3
0.55
V
OL
Notes:
5. Typical values are at VCC=5.0V, TA=+25°C ambient.
6. This parameter is guaranteed but not tested.
7. Pins with bus hold are described in Pin Description.
8. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
9. Tested at +25°C.
3
CY74FCT16245T/2245T
CY74FCT16445T/2H245
Capacitance[6] (T = +25°C, f = 1.0 MHz)
A
[5]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Test Conditions
Typ.
4.5
Max.
6.0
Unit
pF
C
C
V
V
= 0V
IN
IN
= 0V
5.5
8.0
pF
OUT
OUT
Power Supply Characteristics
[5]
Parameter
Description
Quiescent Power Supply Current V =Max.
Typ.
Max.
Unit
I
V <0.2V,
5
500
µA
CC
CC
IN
V >V -0.2V
IN
CC
[10]
∆I
Quiescent Power Supply Current V =Max.
(TTL inputs HIGH)
V =3.4V
0.5
60
1.5
mA
CC
CC
IN
I
Dynamic Power Supply
Current
V
=Max., One Input Toggling, V =V or
50% Duty Cycle, Outputs Open, V =GND
100
µA/MHz
CCD
CC
IN
CC
[11]
IN
OE=DIR=GND
[12]
I
Total Power Supply Current
V
=Max., f =10 MHz,
V =V or
0.6
0.9
2.4
6.4
1.5
2.3
mA
mA
mA
mA
C
CC
1
IN
CC
50% Duty Cycle, Outputs Open, V =GND
One Bit Toggling,
OE=DIR=GND
IN
V =3.4V or
IN
V =GND
IN
[13]
V
=Max., f =2.5 MHz, 50%
V =V or
4.5
CC
1
IN
CC
Duty Cycle, Outputs Open,
Sixteen Bits Toggling,
OE=DIR=GND
V =GND
IN
[13]
V =3.4V or
16.5
IN
V =GND
IN
Notes:
10. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
12. IC
IC
= IQUIESCENT + IINPUTS + IDYNAMIC
= ICC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)
DH = Duty Cycle for TTL inputs HIGH
NT = Number of TTL inputs at DH
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
f0
f1
= Clock frequency for registered devices, otherwise zero
= Input signal frequency
N1 = Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
13. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
4
CY74FCT16245T/2245T
CY74FCT16445T/2H245
]
[14]
Switching Characteristics Over the Operating Range
74FCT16245T
74FCT162245T
74FCT16445T
74FCT162H245T
74FCT16245AT
74FCT162245AT
74FCT16445AT
74FCT162H245AT
Fig.
[15]
Parameter
Description
Min.
Max.
Min.
Max.
Unit
No.
t
t
Propagation Delay Data to Output
A to B, B to A
1.5
7.0
1.5
4.5
ns
1, 3
PLH
PHL
t
t
Output Enable Time
OE to A or B
1.5
1.5
1.5
1.5
9.5
7.5
9.5
7.5
0.5
1.5
1.5
1.5
1.5
6.2
5.0
6.2
5.0
0.5
ns
ns
ns
ns
ns
1, 7, 8
1, 7, 8
1, 7, 8
1, 7, 8
—
PZH
PZL
t
t
Output Disable Time
OE to A or B
PHZ
PLZ
t
t
Output Enable Time
DIR to A or B
PZH
PZL
t
t
Output Disable Time
DIR to A or B
PHZ
PLZ
[16]
t
Output Skew
SK(O)
74FCT16245CT
74FCT162245CT
74FCT16445CT
74FCT162H245CT
74FCT16245ET
74FCT162245ET
74FCT162H245ET
Fig.
[15]
Parameter
Description
Min.
Max.
Min.
Max.
Unit
No.
t
t
Propagation Delay Data to Output
A to B, B to A
1.5
4.1
1.5
3.2
ns
1, 3
1, 7, 8
1, 7, 8
1, 7, 8
1, 7, 8
—
PLH
PHL
t
t
Output Enable Time
OE to A or B
1.5
1.5
1.5
1.5
5.8
4.8
5.8
4.8
0.5
1.5
1.5
1.5
1.5
4.4
4.0
4.8
4.0
0.5
ns
ns
ns
ns
ns
PZH
PZL
t
t
Output Disable Time
OE to A or B
PHZ
PLZ
t
t
Output Enable Time
DIR to A or B
PZH
PZL
t
t
Output Disable Time
DIR to A or B
PHZ
PLZ
[16]
t
Output Skew
SK(O)
Note:
14. Minimum limits are guaranteed but not tested on Propagation Delays.
15. See “Parameter Measurement Information” in the General Information section.
16. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
5
CY74FCT16245T/2245T
CY74FCT16445T/2H245
Ordering Information CY74FCT16245
Speed
Package
Name
Operating
(ns)
Ordering Code
CY74FCT16245ETPAC
CY74FCT16245ETPVC
CY74FCT16245CTPAC
CY74FCT16245CTPVC
CY74FCT16245ATPAC
CY74FCT16245ATPVC
CY74FCT16245TPAC
CY74FCT16245TPVC
Package Type
Range
3.2
Z48
O48
Z48
O48
Z48
O48
Z48
O48
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
Industrial
4.1
4.5
7.0
Industrial
Industrial
Industrial
Ordering Information CY74FCT162245
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY74FCT162245ETPAC
CY74FCT162245ETPVC
CY74FCT162245CTPAC
CY74FCT162245CTPVC
CY74FCT162245ATPAC
CY74FCT162245ATPVC
CY74FCT162245TPAC
CY74FCT162245TPVC
Package Type
3.2
Z48
O48
Z48
O48
Z48
O48
Z48
O48
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
Industrial
Industrial
Industrial
Industrial
4.1
4.5
7.0
Ordering Information CY74FCT16445
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY74FCT16445CTPAC
CY74FCT16445CTPVC
CY74FCT16445ATPAC
CY74FCT16445ATPVC
CY74FCT16445TPAC
CY74FCT16445TPVC
Package Type
4.1
Z48
O48
Z48
O48
Z48
O48
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
Industrial
Industrial
Industrial
4.5
7.0
Ordering Information CY74FCT162H245
Speed
(ns)
Package
Operating
Range
Ordering Code
CY74FCT162H245ETPAC
CY74FCT162H245ETPVC
CY74FCT162H245CTPAC
CY74FCT162H245CTPVC
CY74FCT162H245ATPAC
CY74FCT162H245ATPVC
CY74FCT162H245TPAC
CY74FCT162H245TPVC
Name
Package Type
3.2
4.1
4.5
7.0
Z48
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
Industrial
Industrial
Industrial
Industrial
O48
Z48
O48
Z48
O48
Z48
O48
Document #: 38-00389-C
6
CY74FCT16245T/2245T
CY74FCT16445T/2H245
Package Diagrams
48-Lead Shrunk Small Outline Package O48
48-Lead Thin Shrunk Small Outline Package Z48
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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