CY74FCT163373CPAC [CYPRESS]
Bus Driver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.240 INCH, 0.0196 INCH PITCH, TSSOP-48;
| 型号： | CY74FCT163373CPAC |
| 厂家： | 
CYPRESS |
| 描述： | Bus Driver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.240 INCH, 0.0196 INCH PITCH, TSSOP-48 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
fax id: 7050
CY74FCT163373
CY74FCT163H373
CY74FCT163LD373
CY74FCT163LDH373
16-Bit Latch
CY74FCT163LD2373
Features
• Lite Drive™ option for low noise applications
• 6 mA balanced drive outputs
• FCT-A speed at 5.2 ns
• Low power, pin-compatible replacement for LCX, LPT,
LVC, LVCH & LVT families
• 5V tolerant inputs and outputs*
• 6 mA & 24 mA balanced drive outputs
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for reduced noise
• FCT-C speed at 4.2 ns
• V = 3.0V to 3.6V
CC
• ESD (HBM) > 1100V
Functional Description
These devices are 16-bit, D-type latches, designed for use in
bus applications requiring high speed and low power. They can
either be used as two independent 8-bit latches, or as a single
16-bit latch by connecting the Output Enable (OE) and Latch
(LE) inputs. The outputs are 24-mA balanced output drivers
with current limiting resistors to reduce the need for external
terminating resistors and provide for minimal undershoot and
reduced ground bounce. Flow-through pinout and small shrink
packaging aid in simplifying board layout.
• Latch-up performance exceeds JEDEC standard no. 17
• Typical output skew < 250 ps
• Industrial temperature range of –40°C to +85°C
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
• Typical
(ground bounce) performance exceeds Mil
V
olp
Std 883D
• V = 2.7V to 3.6V
CC
• ESD (HBM) > 2000V
CY74FCT163H373
The CY74FCT163H373 and CY74FCT163LDH373 have “bus
hold” on the data inputs, which retain the input’s last state
whenever the source driving the input goes to high impedance.
This eliminates the need for pullup/down resistors and pre-
vents floating inputs.
• Bus hold on data inputs
• Eliminates the need for external pull-up or pull-down
resistors
• *Devices with bus hold are not recommended for trans-
lating rail-to-rail CMOS signals to 3.3V logic levels
The CY74FCT163373 and the CY74FCT163LD373 are
designed with inputs and outputs capable of being driven by
5.0 V buses, allowing them to be used in mixed voltage
systems as translators. The outputs are also designed with a
power off disable feature enabling them to be used in
applications requiring live insertion.
Pin Configuration
Logic Block Diagrams CY74FCT163373, CY74FCT163H373,
CY74FCT163LD373, CY74FCT163LDH373
SSOP/TSSOP
Top View
OE
1
1
48
47
46
45
44
43
42
41
OE
O
LE
1
1
1
D
1
2
1
1
2
LE
O
D
2
1
3
1
1
GND
O
4
GND
D
D
C
D
1
1
5
1
1
3
4
1
1
3
4
O
1
1
O
D
6
V
CC
V
CC
7
O
D
1
1
5
6
1
1
5
6
8
O
D
9
40
39
38
GND
GND
10
11
TO 7 OTHERCHANNELS
O
D
1
1
7
8
1
1
7
8
O
D
12
13
37
36
35
34
33
O
O
D
D
2
2
1
2
2
1
OE
LE
2
14
15
16
17
18
2
2
GND
O
GND
D
2
2
2
3
4
2
2
3
4
32
31
30
29
28
27
26
25
O
D
D
C
D
2
1
V
CC
V
CC
O
1
2
O
5
D
5
19
20
21
22
23
24
2
2
2
2
O
6
D
6
GND
O
GND
D
2
2
7
8
2
7
8
O
D
2
2
TO 7 OTHERCHANNELS
OE
LE
2
Lite Drive is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
March 19, 1997 - Revised April 20, 1998
CY74FCT163373
CY74FCT163H373
CY74FCT163LD373
CY74FCT163LDH373
Maximum Ratings[3, 4]
Pin Description
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Name
Description
[1]
D
Data Inputs
Storage Temperature...................................... −55°C to +125°C
LE
OE
O
Latch Enable Inputs (Active HIGH)
Output Enable Inputs (Active LOW)
Three-State Outputs
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage Range......................................0.5V to +4.6V
DC Input Voltage.................................................−0.5V to +7.0V
DC Output Voltage..............................................−0.5V to +7.0V
Function Table[2]
DC Output Current
Inputs
Outputs
(Maximum Sink Current/Pin)........................... −60 to +120 mA
D
H
L
LE
H
H
L
OE
L
O
H
L
Power Dissipation.......................................................... 1.0W
Operating Range
L
X
X
L
Q
Ambient
0
Range
Industrial
Temperature
V
CC
X
H
Z
−40°C to +85°C
2.7V to3.6V
Electrical Characteristics for Non Bus Hold Devices Over the Operating Range V =2.7V to 3.6V
CC
[5]
Parameter
Description
Input HIGH Voltage
Test Conditions
All Inputs
Min.
Typ.
Max.
5.5
Unit
V
V
2.0
IH
IL
H
V
V
V
Input LOW Voltage
0.8
V
[6]
Input Hysteresis
100
mV
V
Input Clamp Diode Voltage
Input HIGH Current
V
V
=Min., I =–18 mA
–0.7
–1.2
IK
CC
CC
IN
I
I
I
=Max., V =5.5
±1
µA
IH
I
Input LOW Current
V
V
=Max., V =GND
±1
±1
µA
µA
IL
CC
CC
I
High Impedance Output Current
(Three-State Output pins)
=Max., V
=Max., V
=Max., V
=5.5V
=GND
=GND
OZH
OUT
OUT
OUT
I
High Impedance Output Current
(Three-State Output pins)
V
±1
µA
OZL
CC
[7]
I
I
I
Short Circuit Current
V
V
V
–60
–135
–240
±100
10
mA
µA
µA
OS
CC
CC
Power-Off Disable
=0V, V
≤4.5V
OFF
CC
OUT
Quiescent Power Supply Current
≤0.2V,
V
V
=Max.
=Max.
0.1
2.0
IN
CC
V >V –0.2V
IN
CC
[8]
∆I
Quiescent Power Supply Current
(TTL inputs HIGH)
V =V –0.6V
30
µA
CC
IN
CC
CC
Note:
1. On the CY74FCT163H373 & CY74FCT163LDH373 these pins have “bus hold.
2. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = High Impedance. Q0=Previous state of flip-flop.
3. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature
range.
4. With the exception of inputs with bus hold, unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
5. Typical values are at VCC=3.3V, TA = +25°C ambient.
6. This parameter is guaranteed but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
8. Per TTL driven input; all other inputs at VCC or GND.
2
CY74FCT163373
CY74FCT163H373
CY74FCT163LD373
CY74FCT163LDH373
Electrical Characteristics For Bus Hold Devices Over the Operating Range V =2.7V to 3.6V
CC
[5]
Parameter
Description
Input HIGH Voltage
Test Conditions
All Inputs
Min.
Typ.
Max.
Unit
V
V
2.0
V
CC
IH
IL
H
V
V
V
Input LOW Voltage
0.8
V
[6]
Input Hysteresis
100
mV
V
Input Clamp Diode Voltage
Input HIGH Current
V
V
=Min., I =–18 mA
–0.7
– 1.2
IK
CC
CC
IN
I
=Max., V =V
±100
µA
IH
I
CC
I
Input LOW Current
±100
µA
µA
µA
µA
IL
[9]
I
I
Bus Hold Sustain Current on Bus Hold Input
V
V
=Min.
V =2.0V
–50
+50
BBH
BBL
CC
CC
I
V =0.8V
I
[9]
I
I
Bus Hold Overdrive Current on Bus Hold Input
=Max., V =1.5V
I
±500
BHHO
BHLO
I
High Impedance Output Current
(Three-State Output pins)
V
V
=Max., V
=Max., V
=Max., V
=V
CC
±1
±1
µA
µA
OZH
CC
CC
OUT
OUT
OUT
I
High Impedance Output Current
(Three-State Output pins)
=GND
=GND
OZL
[7]
I
I
I
Short Circuit Current
V
V
V
–60
–135
–240
±100
+40
mA
µA
µA
OS
CC
CC
Power-Off Disable
=0V, V
≤4.5V
OFF
CC
OUT
Quiescent Power Supply Current
≤0.2V,
IN
IN
V
V
=Max.
=Max.
CC
V >V –0.2V
CC
[8]
∆
Quiescent Power supply Current
(TTL inputs HIGH)
V =V –0.6V
+350
µA
ICC
IN
CC
CC
Electrical Characteristics For Balanced Drive Devices Over the Operating Range V =2.7V to 3.6V
CC
[5]
Parameter
Description
Test Conditions
=3.3V, V =V
Min.
Typ.
Max.
Unit
[7]
I
I
Output LOW Dynamic Current
Output HIGH Dynamic Current
Output HIGH Voltage
V
45
180
mA
ODL
CC
IN
IH
or V , V
=1.5V
IL OUT
[7]
V
=3.3V, V =V
IH
–45
–
–180
mA
ODH
CC
IN
or V , V
=1.5V
IL OUT
V
V
V
V
V
V
=Min., I = –0.1 mA
V –0.2
CC
V
V
V
V
OH
CC
CC
CC
CC
CC
OH
[10]
=Min., I = –8 mA
2.4
2.0
3.0
3.0
OH
=3.0V, I = –24 mA
OH
V
Output LOW Voltage
=Min., I = 0.1mA
0.2
OL
OL
=Min., I = 24 mA
0.3
0.55
OL
Electrical Characteristics For Lite Drive Devices Over the Operating Range V =3.0V to 3.6V
CC
[5]
Parameter
Description
Test Conditions
=3.3V, V =V
Min.
Typ.
Max.
Unit
[7]
I
I
Output LOW Dynamic Current
V
15.0
45
mA
ODL
CC
IN
IH
or V , V
=1.5V
IL OUT
[7]
Output HIGH Dynamic Current
V
=3.3V, V =V
IH
–15.0
2.4
–45
mA
ODH
CC
IN
=1.5V
or V , V
IL OUT
V
V
Output HIGH Voltage
Output LOW Voltage
V
V
=3.0 V, I = –6 mA
3.0
V
V
OH
CC
CC
OH
=3.0 V, I = 6 mA
0.55
OL
OL
Notes:
9. Pins with bus hold are described in Pin Description.
10. VOH=VCC–0.6 V at rated current.
3
CY74FCT163373
CY74FCT163H373
CY74FCT163LD373
CY74FCT163LDH373
Capacitance[6](T = +25°C, f = 1.0 MHz)
A
[5]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Test Conditions
Typ.
4.5
Max.
6.0
Unit
pF
C
C
V
V
= 0V
IN
IN
= 0V
5.5
8.0
pF
OUT
OUT
Power Supply Characteristics
[5]
Parameter
Description
Typ.
50
Max.
Unit
I
Dynamic Power Supply
V
=Max., One Input Toggling, V =V or
75
µA/MHz
CCD
CC
IN
CC
[11]
Current
50% Duty Cycle,
V =GND
IN
Outputs Open, OE=GND
I
Total Power Supply
Current
V
=Max., f =10 MHz, 50%
V =V or
0.5
0.5
2.0
2.0
0.8
0.8
mA
mA
mA
mA
C
CC
1
IN
CC
[12]
Duty Cycle, Outputs Open, One V =GND
Bit Toggling, OE=GND
IN
V =V –0.6V or
IN
CC
V =GND
IN
[13]
V
=Max., f =2.5 MHz, 50%
V =V or
3.0
CC
1
IN
CC
Duty Cycle, Outputs Open, Six- V =GND
teen Bits Toggling, OE=GND
IN
[13]
V =V –0.6V or
3.3
IN
CC
V =GND
IN
[14,15]
Over the Operating Range V =3.0V to 3.6V
Switching Characteristics
CC
CY74FCT163373A
CY74FCT163H373A
CY74FCT163373C
CY74FCT163H373C
[16]
Parameter
Description
Min.
Max.
Min.
Max.
Unit
Fig. No.
t
t
Propagation Delay D to Q
Output
1.5
4.8
1.5
4.1
ns
ns
ns
ns
1, 3
PLH
PHL
t
t
Propagation Delay LE to Q
Output
2.0
1.5
1.5
8.0
6.2
5.6
2.0
1.5
1.5
5.5
5.8
5.2
1, 5
PLH
PHL
t
t
Output Enable Time
1, 7, 8
1, 7, 8
PZH
PZL
t
t
Output Disable Time
PHZ
PLZ
t
t
t
Input Setup time
Input Hold time
2.0
1.5
-
-
2.0
1.5
-
-
ns
ns
ns
1, 4
1, 4
—
SU
H
[17]
Output Skew
0.5
0.5
SK(O)
Notes:
11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
12. IC
IC
=
=
=
=
=
=
=
=
=
=
IQUIESCENT + IINPUTS + IDYNAMIC
ICC+∆ICCDHNT+ICCD(f0/2 + f1N1)
Quiescent Current with CMOS input levels
Power Supply Current for a TTL HIGH input (VIN=3.4V)
Duty Cycle for TTL inputs HIGH
ICC
∆ICC
DH
NT
ICCD
f0
Number of TTL inputs at DH
Dynamic Current caused by an input transition pair (HLH or LHL)
Clock frequency for registered devices, otherwise zero
Input signal frequency
f1
N1
Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
13. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
14. Minimum limits are guaranteed but not tested on Propagation Delays.
15. For VCC =2.7, propagation delay, output enable and output disable times should be degraded by 20%.
16. See “Parameter Measurement Information” in the General Information section.
17. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4
CY74FCT163373
CY74FCT163H373
CY74FCT163LD373
CY74FCT163LDH373
[14,15]
Over the Operating Range V =3.0V to 3.6V
Switching Characteristics
CC
[18]
[18]
CY74FCT163LD373
CY74FCT163LDH373
CY74FCT163LD373A
CY74FCT163LDH373A
[16]
Parameter
Description
Min.
Max.
Min.
Max.
Unit
Fig. No.
t
t
Propagation Delay Clock to
Q Output
8
1.5
4.8
ns
1, 3
PLH
PHL
t
t
Propagation Delay LE to Q
Output
13
12
8.0
6.2
5.6
ns
ns
ns
1. 3
PLH
PHL
t
t
Output Enable Time
1.5
1.5
1, 7, 8
1, 7, 8
PZH
PZL
t
t
Output Disable Time
7.5
PHZ
PLZ
t
t
t
Input Setup time
Input Hold time
2.0
1.5
-
-
2.0
1.5
ns
ns
ns
1, 4
1, 4
—
SU
H
[17]
Output Skew
0.5
0.5
SK(O)
Note:
18. For Lite Drive devices the load capacitance is 30 pF. For all others it is 50 pF.
Ordering Information CY74FCT163373
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
CY74FCT163373CPAC
CY74FCT163373CPVC
CY74FCT163373APAC
CY74FCT163373APVC
Package Type
4.2
Z48
O48
Z48
O48
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
Industrial
5.2
Industrial
Ordering Information CY74FCT163H373
Speed
(ns)
Package
Operating
Range
Ordering Code
CY74FCT163H373CPAC
CY74FCT163H373CPVC
CY74FCT163H373APAC
CY74FCT163H373APVC
Name
Package Type
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
4.2
Z48
Industrial
O48
Z48
5.2
Industrial
O48
Ordering Information CY74FCT163LD373
Speed
(ns)
Package
Operating
Range
Ordering Code
CY74FCT163LD373APAC
CY74FCT163LD373APVC
CY74FCT163LD373PAC
CY74FCT163LD373PVC
Name
Package Type
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
5.2
Z48
Industrial
O48
Z48
8.0
Industrial
O48
5
CY74FCT163373
CY74FCT163H373
CY74FCT163LD373
CY74FCT163LDH373
Ordering Information CY74FCT163LDH373
Speed
(ns)
Package
Operating
Range
Ordering Code
CY74FCT163LDH373APAC
CY74FCT163LDH373APVC
CY74FCT163LDH373PAC
CY74FCT163LDH373PVC
Name
Package Type
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
48-Lead (240-Mil) TSSOP
48-Lead (300-Mil) SSOP
5.2
Z48
Industrial
O48
Z48
8.0
Industrial
O48
Document #: 38-00580-A
Package Diagrams
48-Lead Shrunk Small Outline Package O48
6
CY74FCT163373
CY74FCT163H373
CY74FCT163LD373
CY74FCT163LDH373
Package Diagrams (continued)
48-Lead Thin Shrunk Small Outline Package Z48
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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