CY7B991-7JXIT [CYPRESS]
PLL Based Clock Driver, 7B Series, 8 True Output(s), 0 Inverted Output(s), PQCC32, 0.453 X 0.553 INCH, LEAD FREE, PLASTIC, LCC-32;
| 型号： | CY7B991-7JXIT |
| 厂家： | 
CYPRESS |
| 描述： | PLL Based Clock Driver, 7B Series, 8 True Output(s), 0 Inverted Output(s), PQCC32, 0.453 X 0.553 INCH, LEAD FREE, PLASTIC, LCC-32 |
| 文件： | 总21页 (文件大小：1822K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7B991
CY7B992
Programmable Skew Clock Buffer
Programmable Skew Clock Buffer
Features
Functional Description
■ All output pair skew <100 ps typical (250 ps maximum)
■ 3.75 MHz to 80 MHz output operation
The CY7B991 and CY7B992 Programmable Skew Clock Buffers
(PSCB) offer user selectable control over system clock functions.
These multiple output clock drivers provide the system integrator
with functions necessary to optimize the timing of high
performance computer systems. Each of the eight individual
drivers, arranged in four pairs of user controllable outputs, can
drive terminated transmission lines with impedances as low as
50. They can deliver minimal and specified output skews and
full swing logic levels (CY7B991 TTL or CY7B992 CMOS).
■ User selectable output functions
❐ Selectable skew to 18 ns
❐ Inverted and non-inverted
❐ Operation at 1⁄2 and 1⁄4 input frequency
❐ Operation at 2 × and 4 × input frequency (input as low as
3.75 MHz)
Each output is hardwired to one of the nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are determined
by the operating frequency with outputs that skew up to ±6 time
units from their nominal “zero” skew position. The completely
integrated PLL allows cancellation of external load and
transmission line delay effects. When this “zero delay” capability
of the PSCB is combined with the selectable output skew
functions, you can create output-to-output delays of up to ±12
time units.
■ Zero input to output delay
■ 50% duty cycle outputs
■ Outputs drive 50 terminated lines
■ Low operating current
■ 32-pin PLCC package
■ Jitter < 200 ps peak-to-peak (< 25 ps RMS)
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
enable distribution of a low frequency clock that are multiplied by
two or four at the clock destination. This facility minimizes clock
distribution difficulty, allowing maximum system clock speed and
flexibility.
For a complete list of related documentation, click here.
Logic Block Diagram
TEST
PHASE
FB
VCO AND
TIME UNIT
GENERATOR
FREQ
DET
FILTER
REF
FS
4Q0
4Q1
4F0
4F1
SELECT
INPUTS
(THREE
LEVEL)
SKEW
3Q0
3F0
3F1
3Q1
SELECT
2Q0
2F0
2F1
MATRIX
2Q1
1Q0
1Q1
1F0
1F1
Cypress Semiconductor Corporation
Document Number: 38-07138 Rev. *N
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 4, 2016
CY7B991
CY7B992
Contents
Pinouts ..............................................................................3
Pin Definitions ..................................................................3
Block Diagram Description ..............................................4
Phase Frequency Detector and Filter ..........................4
VCO and Time Unit Generator ....................................4
Skew Select Matrix ......................................................4
Test Mode ..........................................................................5
Maximum Ratings .............................................................6
Operating Range ...............................................................6
Electrical Characteristics .................................................7
Capacitance ......................................................................8
Thermal Resistance ..........................................................8
AC Test Loads and Waveforms .......................................8
Switching Characteristics ................................................9
Switching Characteristics ..............................................10
Switching Characteristics ..............................................11
AC Timing Diagrams ......................................................12
Operational Mode Descriptions ....................................13
Ordering Information ......................................................17
Ordering Code Definitions .........................................17
Package Diagram ............................................................18
Acronyms ........................................................................19
Document Conventions .................................................19
Units of Measure .......................................................19
Document History Page .................................................20
Sales, Solutions, and Legal Information ......................21
Worldwide Sales and Design Support .......................21
Products ....................................................................21
PSoC®Solutions .......................................................21
Cypress Developer Community .................................21
Technical Support .....................................................21
Document Number: 38-07138 Rev. *N
Page 2 of 21
CY7B991
CY7B992
Pinouts
Figure 1. 32-pin PLCC pinout
4
3
2
1
32 31 30
29
2F0
GND
1F1
1F0
5
6
3F1
4F0
28
27
4F1
7
8
9
V
26
25
24
23
CCQ
CY7B991
CY7B992
V
CCN
V
CCN
4Q1
10
1Q0
1Q1
GND
GND
4Q0
GND
GND
11
12
22
21
13
14 15 16 17 18 19 20
Pin Definitions
Signal Name
I/O
Description
REF
I
Reference frequency input. This input supplies the frequency and timing against which all functional
variations are measured.
FB
I
PLL feedback input (typically connected to one of the eight outputs).
Three level frequency range select. See Table 1.
Three level function select inputs for output pair 1 (1Q0, 1Q1). See Table 2.
Three level function select inputs for output pair 2 (2Q0, 2Q1). See Table 2.
Three level function select inputs for output pair 3 (3Q0, 3Q1). See Table 2.
Three level function select inputs for output pair 4 (4Q0, 4Q1). See Table 2.
Three level select. See Test Mode on page 5 under the Block Diagram Description on page 4.
Output pair 1. See Table 2.
FS
I
1F0, 1F1
2F0, 2F1
3F0, 3F1
4F0, 4F1
TEST
I
I
I
I
I
1Q0, 1Q1
2Q0, 2Q1
3Q0, 3Q1
4Q0, 4Q1
VCCN
O
O
Output pair 2. See Table 2.
O
Output pair 3. See Table 2.
O
Output pair 4. See Table 2.
PWR
PWR
PWR
Power supply for output drivers.
VCCQ
Power supply for internal circuitry.
GND
Ground.
Document Number: 38-07138 Rev. *N
Page 3 of 21
CY7B991
CY7B992
Skew Select Matrix
Block Diagram Description
The skew select matrix contains four independent sections. Each
section has two low skew, high fanout drivers (× Q0, × Q1), and
two corresponding three level function select (× F0, × F1) inputs.
Table 2 shows the nine possible output functions for each section
as determined by the function select inputs. All times are
measured with respect to the REF input assuming that the output
connected to the FB input has 0tU selected.
Phase Frequency Detector and Filter
The Phase Frequency Detector and Filter blocks accept inputs
from the reference frequency (REF) input and the feedback (FB)
input and generate correction information to control the
frequency of the Voltage Controlled Oscillator (VCO). These
blocks, along with the VCO, form a Phase Locked Loop (PLL)
that tracks the incoming REF signal.
Table 2. Programmable Skew Configurations [1]
VCO and Time Unit Generator
Function Selects
Output Functions
The VCO accepts analog control inputs from the PLL filter block.
It generates a frequency used by the time unit generator to
create discrete time units that are selected in the skew select
matrix. The operational range of the VCO is determined by the
FS control pin. The time unit (tU) is determined by the operating
frequency of the device and the level of the FS pin as shown in
Table 1.
1F1, 2F1, 1F0, 2F0, 1Q0, 1Q1,
3Q0, 3Q1 4Q0, 4Q1
3F1, 4F1
LOW
LOW
LOW
MID
3F0, 4F0 2Q0, 2Q1
LOW
MID
–4tU
–3tU
–2tU
–1tU
0tU
Divide by 2 Divide by 2
–6tU
–4tU
–2tU
0tU
–6tU
–4tU
–2tU
0tU
HIGH
LOW
MID
Table 1. Frequency Range Select and tU Calculation [1]
MID
fNOM (MHz)
MID
HIGH
LOW
MID
+1tU
+2tU
+3tU
+4tU
+2tU
+4tU
+6tU
+2tU
+4tU
+6tU
1
Approximate
-----------------------
=
tU
FS [2, 3]
fNOM N Frequency (MHz) at
HIGH
HIGH
HIGH
Min
Max
which tU = 1.0 ns
where N =
LOW
MID
15
25
40
30
50
80
44
26
16
22.7
38.5
62.5
HIGH
Divide by 4 Inverted
HIGH
Notes
1. For all tristate inputs, HIGH indicates a connection to V , LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry
CC
holds an unconnected input to V /2.
CC
2. The level is set on FS is determined by the “normal” operating frequency (fNOM) of the VCO and Time Unit Generator (see Logic Block Diagram). Nominal frequency
(fNOM) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB
inputs are fNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs are fNOM/2 or fNOM/4 when the part is configured for a
frequency multiplication by using a divided output as the FB input.
3. When the FS pin is selected HIGH, the REF input must not transition upon power up until V has reached 4.3 V.
CC
Document Number: 38-07138 Rev. *N
Page 4 of 21
CY7B991
CY7B992
Figure 2 shows the typical outputs with FB connected to a zero skew output. [4]
Figure 2. Typical Outputs with FB Connected to a Zero-Skew Output
FBInput
REFInput
1Fx
2Fx
3Fx
4Fx
(N/A)
LM
– 6t
– 4t
– 3t
U
U
U
LL
LH
LM
(N/A)
LH
ML
ML
– 2t
– 1t
U
U
(N/A)
MM
MH
HL
MM
(N/A)
MH
0t
U
U
U
U
+1t
+2t
+3t
HM
(N/A)
HH
HL
HM
+4t
+6t
U
U
(N/A)
(N/A)
(N/A)
LL/HH
HH
DIVIDED
INVERT
If the TEST input is forced to its MID or HIGH state, the device
operates with its internal phase locked loop disconnected, and
input levels supplied to REF directly controls all outputs. Relative
output to output functions are the same as in normal mode.
Test Mode
The TEST input is a three level input. In normal system
operation, this pin is connected to ground, enabling the
CY7B991 or CY7B992 to operate as explained in Skew Select
Matrix on page 4. For testing purposes, any of the three level
inputs can have a removable jumper to ground, or be tied LOW
through a 100 resistor. This enables an external tester to
change the state of these pins.
In contrast with normal operation (TEST tied LOW), all outputs
function based only on the connection of their own function
selects inputs (× F0 and × F1) and the waveform characteristics
of the REF input.
Note
4. FB connected to an output selected for “zero” skew (i.e., × F1 = × F0 = MID).
Document Number: 38-07138 Rev. *N
Page 5 of 21
CY7B991
CY7B992
Maximum Ratings
Operating Range
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Ambient Temperature
Storage Temperature ............................... –65 °C to +150 °C
Range
Commercial
Industrial
VCC
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
0 °C to +70 °C
5 V 10%
5 V 10%
–40 °C to +85 °C
Supply Voltage to Ground Potential .............–0.5 V to +7.0 V
DC Input Voltage .........................................–0.5 V to +7.0 V
Output Current into Outputs (LOW) ............................ 64 mA
Static Discharge Voltage
(MIL-STD-883, Method 3015) .................................> 2001 V
Latch Up Current ...................................................> 200 mA
Document Number: 38-07138 Rev. *N
Page 6 of 21
CY7B991
CY7B992
Electrical Characteristics
Over the Operating Range
CY7B991
CY7B992
Parameter
Description
Test Conditions
Unit
Min
Max
–
Min
Max
–
VOH
Output HIGH Voltage
VCC = Min IOH = –16 mA
2.4
–
–
V
V
CC = Min, IOH =–40 mA
–
VCC
–
–
0.75
VOL
Output LOW Voltage
VCC = Min, IOL = 46 mA
VCC = Min, IOL = 46 mA
–
–
0.45
–
–
–
–
V
0.45
VCC
VIH
VIL
Input HIGH Voltage (REF and FB
inputs only)
2.0
VCC
VCC – 1.35
V
V
Input LOW Voltage (REF and FB
inputs only)
–0.5
0.8
–0.5
1.35
VCC
VIHH
VIMM
VILL
IIH
Three Level Input HIGH Voltage Min VCC Max
VCC – 0.85
VCC
VCC – 0.85
V
(Test, FS, × Fn) [5]
Three Level Input MID Voltage
(Test, FS, × Fn) [5]
Min VCC Max
VCC/2 – VCC/2 + VCC/2 – VCC/2 +
500 mV
V
500 mV
500 mV 500 mV
Three Level Input LOW Voltage Min VCC Maximum
0.0
0.85
0.0
–
0.85
10
V
(Test, FS, × Fn) [5]
Input HIGH Leakage Current
(REF and FB inputs only)
VCC = Max, VIN = Max.
VCC = Max, VIN = 0.4 V
VIN = VCC
–
–500
–
10
–
A
A
A
A
A
mA
mA
IIL
Input LOW Leakage Current
(REF and FB inputs only)
–500
–
–
IIHH
IIMM
IILL
Input HIGH Current
(Test, FS, × Fn)
200
50
200
50
Input MID Current
(Test, FS, × Fn)
VIN = VCC/2
–50
–
–50
–
Input LOW Current
(Test, FS, × Fn)
Output Short Circuit Current [6]
VIN = GND
–200
–250
–200
N/A
IOS
VCC = Max, VOUT = GND (25 °C
only)
–
–
ICCQ
Operating Current Used by
Internal Circuitry
VCCN = VCCQ = Max, Commercial
–
–
85
90
–
–
85
90
All Input Selects
Open
Industrial
ICCN
PD
Output Buffer Current per Output VCCN = VCCQ = Max, IOUT = 0 mA
–
–
14
78
–
–
19
mA
Pair [7]
Input Selects Open, fMAX
Power Dissipation per Output
Pair [5]
VCCN = VCCQ = Max,
IOUT = 0 mA,
104 [8] mW
Input Selects Open, fMAX
Notes
5. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to the load
circuit:
CY7B991:PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] × 1.1
CY7B992:PD = [(19.25+ 0.94F) + [((700 + 6F)/Z) + (.017FC)]N] × 1.1
See note 7 for variable definition.
6. CY7B991 must be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B992 outputs must not
be shorted to GND. Doing so may cause permanent damage.
7. Total output current per output pair is approximated by the following expression that includes device current plus load current:
CY7B991:
CY7B992:
Where
I
I
= [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] × 1.1
= [(3.5 + 0.17F) + [((1160 – 2.8F)/Z) + (.0025FC)]N] × 1.1
CCN
CCN
F = frequency in MHz; C = capacitive load in pF; Z = line impedance in ohms; N = number of loaded outputs; 0, 1, or 2; FC = F × C.
8. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-07138 Rev. *N
Page 7 of 21
CY7B991
CY7B992
Capacitance
Parameter [9, 10]
Description
Test Conditions
Max
Unit
CIN
Input Capacitance
TA = 25 °C, f = 1 MHz, VCC = 5.0 V
10
pF
Thermal Resistance
32-pin PLCC
Package
Parameter [10]
Description
Test Conditions
Unit
JA
JC
Thermal resistance
(junction to ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
according to EIA/JESD51.
44
°C/W
Thermal resistance
(junction to case)
26
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
5V
3.0V
2.0V
=1.5V
0.8V
2.0V
th
0.8V
R1=130
R2=91
R1
R2
V
th
V =1.5V
C = 50 pF (C =30 pF for –2 and –5 devices)
L
L
0.0V
C
L
(Includes fixture and probe capacitance)
1ns
1ns
TTL ACTest Load (CY7B991)
TTL Input Test Waveform (CY7B991)
V
CC
V
CC
R1=100
R2=100
C = 50 pF (C
80%
80%
= V /2
20%
R1
R2
=30 pF for –2 and –5 devices)
L
L
V
th
= V /2
V
CC
th
CC
(Includes fixture and probe capacitance)
20%
0.0V
C
L
3ns
3ns
CMOS AC Test Load (CY7B992)
CMOS Input Test Waveform (CY7B992)
Notes
9. CMOS output buffer current and power dissipation specified at 50 MHz reference frequency.
10. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-07138 Rev. *N
Page 8 of 21
CY7B991
CY7B992
Switching Characteristics
Over the Operating Range
CY7B991-2 [13]
CY7B992-2 [13]
Parameter [11, 12]
Description
Unit
Min
Typ
–
Max
Min
15
Typ
–
Max
30
fNOM
Operating Clock Frequency FS = LOW [11, 14]
FS = MID [11, 14]
in MHz
15
25
30
50
80
–
MHz
–
25
–
50
80 [16]
FS = HIGH [11, 14, 15]
40
–
40
–
tRPWH
tRPWL
tU
REF Pulse Width HIGH
5.0
5.0
–
5.0
5.0
–
–
ns
ns
REF Pulse Width LOW
–
–
–
–
Programmable Skew Unit
See Table 1 on page 4
tSKEWPR
tSKEW0
tSKEW1
Zero Output Matched-Pair Skew (XQ0, XQ1) [17, 18]
Zero Output Skew (All Outputs) [17, 19, 20]
–
–
–
0.05
0.1
0.20
0.25
0.5
–
–
–
0.05
0.1
0.20
0.25
0.5
ns
ns
ns
Output Skew (Rise-Rise, Fall-Fall, Same Class
Outputs) [17, 20]
0.25
0.25
tSKEW2
tSKEW3
tSKEW4
Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided) [17, 20]
–
–
–
0.3
0.25
0.5
0.5
0.5
–
–
–
–
0.3
0.25
0.5
0.5
0.5
0.7
ns
ns
ns
Output Skew (Rise-Rise, Fall-Fall, Different Class
Outputs) [17, 20]
Output Skew (Rise-Fall, Nominal-Divided,
0.9
Divided-Inverted) [17, 20]
tDEV
Device-to-Device Skew [13, 21]
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation [22]
Output HIGH Time Deviation from 50% [23, 24]
Output LOW Time Deviation from 50% [23, 24]
Output Rise Time [23, 25]
Output Fall Time [23, 25]
PLL Lock Time [26]
Cycle-to-Cycle Output Jitter RMS [13]
Peak-to-Peak [13]
–
–0.25
–0.65
–
–
0.0
0.0
–
0.75
–
0.0
0.0
–
0.75
+0.25
+0.5
3.0
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
tPD
+0.25 –0.25
tODCV
tPWH
tPWL
tORISE
tOFALL
tLOCK
tJR
+0.65
2.0
–0.5
–
–
–
1.5
–
–
3.0
0.15
0.15
–
1.0
1.0
–
1.2
0.5
0.5
–
2.0
2.0
–
2.5
1.2
2.5
0.5
0.5
–
–
25
–
–
25
–
–
200
–
–
200
Notes
11. The level is set on FS is determined by the “normal” operating frequency (fNOM) of the VCO and Time Unit Generator (see Logic Block Diagram). Nominal frequency
(
) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB
fNOM
inputs are f
when the output connected to FB is undivided. The frequency of the REF and FB inputs are fNOM/2 or fNOM/4 when the part is configured for a
NOM
frequency multiplication by using a divided output as the FB input.
12. Test measurement levels for the CY7B991 are TTL levels (1.5 V to 1.5 V). Test measurement levels for the CY7B992 are CMOS levels (V /2 to V /2). Test
CC
CC
conditions assume signal transition times of 2 ns or less and output loading as shown in the Figure 3 on page 8 unless otherwise specified.
13. Guaranteed by statistical correlation. Tested initially and after any design or process changes that affect these parameters.
14. For all tristate inputs, HIGH indicates a connection to V , LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry
CC
holds an unconnected input to V /2.
CC
15. When the FS pin is selected HIGH, the REF input must not transition upon power up until V has reached 4.3 V.
CC
16. Except as noted, all CY7B992-2 and -5 timing parameters are specified to 80 MHz with a 30 pF load.
17. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same t delay is selected when all are loaded with
U
50 pF and terminated with 50 to 2.06 V (CY7B991) or V /2 (CY7B992).
CC
18. t
19. t
is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0t .
SKEWPR
U
is defined as the skew between outputs when they are selected for 0t . Other outputs are divided or inverted but not shifted.
SKEW0
U
20. C = 0 pF. For C = 30 pF, t
= 0.35 ns.
L
L
SKEW0
21. t
22. t
is the output-to-output skew between any two devices operating under the same conditions (V ambient temperature, air flow, and so on.)
DEV
ODCV
CC
is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in t
and t
specifications.
SKEW4
SKEW2
23. Specified with outputs loaded with 30 pF for the CY7B99X-2 and -5 devices and 50 pF for the CY7B99X-7 devices. Devices are terminated through 50 to 2.06 V
(CY7B991) or V /2 (CY7B992).
CC
24. tPWH is measured at 2.0 V for the CY7B991 and 0.8 V for the CY7B992. tPWL is measured at 0.8V for the CY7B991 and 0.2 V for the CY7B992.
CC
CC
25. t
26. t
and t
measured between 0.8V and 2.0V for the CY7B991 or 0.8 V and 0.2 V for the CY7B992.
ORISE
OFALL CC CC
is the time that is required before synchronization is achieved. This specification is valid only after V is stable and within normal operating limits. This parameter
is measured from the application of a new signal or frequency at REF or FB until t is within specified limits.
LOCK
CC
PD
Document Number: 38-07138 Rev. *N
Page 9 of 21
CY7B991
CY7B992
Switching Characteristics
Over the Operating Range
CY7B991-5
CY7B992-5
Parameter [27, 28]
Description
FS = LOW [27, 29]
Unit
Min
15
Typ
–
Max
30
50
80
–
Min
15
Typ
–
Max
30
fNOM
Operating Clock
Frequency in MHz
MHz
FS = MID [27, 29]
FS = HIGH [27, 29, 30]
25
–
25
–
50
40
–
40
–
80 [31]
tRPWH
tRPWL
tU
REF Pulse Width HIGH
REF Pulse Width LOW
Programmable Skew Unit
5.0
5.0
–
5.0
5.0
–
–
ns
ns
–
–
–
–
See Table 1 on page 4
tSKEWPR
tSKEW0
tSKEW1
Zero Output Matched-Pair Skew (XQ0, XQ1) [32, 33]
Zero Output Skew (All Outputs) [32, 34]
–
–
–
0.1
0.25
0.6
0.25
0.5
–
–
–
0.1
0.25
0.6
0.25
0.5
ns
ns
ns
Output Skew (Rise-Rise, Fall-Fall, Same Class
Outputs) [32, 35]
0.7
0.7
tSKEW2
tSKEW3
tSKEW4
Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided) [32, 35]
–
–
–
0.5
0.5
0.5
1.0
0.7
1.0
–
–
–
0.6
0.5
0.6
1.5
0.7
1.7
ns
ns
ns
Output Skew (Rise-Rise, Fall-Fall, Different Class
Outputs)[32, 35]
Output Skew (Rise-Fall, Nominal-Divided,
Divided-Inverted) [32, 35]
tDEV
Device-to-Device Skew [36, 37]
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation [22]
Output HIGH Time Deviation from 50% [39, 40]
Output LOW Time Deviation from 50% [39, 40]
Output Rise Time [39, 41]
Output Fall Time [39, 41]
PLL Lock Time [42]
Cycle-to-Cycle Output Jitter RMS [36]
Peak-to-Peak [36]
–
–0.5
–1.0
–
–
0.0
0.0
–
1.25
+0.5
+1.0
2.5
3
–
–0.5
–1.2
–
–
0.0
0.0
–
1.25
+0.5
+1.2
4.0
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
tPD
tODCV
tPWH
tPWL
tORISE
tOFALL
tLOCK
tJR
–
–
–
–
4.0
0.15
0.15
–
1.0
1.0
–
1.5
1.5
0.5
25
0.5
0.5
–
2.0
2.0
–
3.5
3.5
0.5
–
–
–
–
25
–
–
200
–
–
200
Notes
27. The level is set on FS is determined by the “normal” operating frequency (fNOM) of the VCO and Time Unit Generator (see Logic Block Diagram). Nominal frequency
(
) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB
fNOM
inputs are f
when the output connected to FB is undivided. The frequency of the REF and FB inputs are fNOM/2 or fNOM/4 when the part is configured for a
NOM
frequency multiplication by using a divided output as the FB input.
28. Test measurement levels for the CY7B991 are TTL levels (1.5 V to 1.5 V). Test measurement levels for the CY7B992 are CMOS levels (V /2 to V /2). Test
CC
CC
conditions assume signal transition times of 2 ns or less and output loading as shown in the Figure 3 on page 8 unless otherwise specified.
29. For all tristate inputs, HIGH indicates a connection to V , LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry
CC
holds an unconnected input to V /2.
CC
30. When the FS pin is selected HIGH, the REF input must not transition upon power up until V has reached 4.3 V.
CC
31. Except as noted, all CY7B992-2 and -5 timing parameters are specified to 80 MHz with a 30 pF load.
32. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same t delay is selected when all are loaded with
U
50 pF and terminated with 50 to 2.06 V (CY7B991) or V /2 (CY7B992).
CC
33. t
34. t
is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0t .
SKEWPR
U
is defined as the skew between outputs when they are selected for 0t . Other outputs are divided or inverted but not shifted.
SKEW0
U
35. C = 0 pF. For C = 30 pF, t = 0.35 ns.
L
L
SKEW0
36. Guaranteed by statistical correlation. Tested initially and after any design or process changes that affect these parameters.
37. t
38. t
is the output-to-output skew between any two devices operating under the same conditions (V ambient temperature, air flow, and so on.)
DEV
CC
is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in t
and t
specifications.
SKEW4
ODCV
SKEW2
39. Specified with outputs loaded with 30 pF for the CY7B99X-2 and -5 devices and 50 pF for the CY7B99X-7 devices. Devices are terminated through 50 to 2.06 V
(CY7B991) or V /2 (CY7B992).
CC
40. tPWH is measured at 2.0 V for the CY7B991 and 0.8 V for the CY7B992. tPWL is measured at 0.8V for the CY7B991 and 0.2 V for the CY7B992.
CC
CC
41. t
42. t
and t
measured between 0.8V and 2.0V for the CY7B991 or 0.8 V and 0.2 V for the CY7B992.
ORISE
OFALL CC CC
is the time that is required before synchronization is achieved. This specification is valid only after V is stable and within normal operating limits. This parameter
is measured from the application of a new signal or frequency at REF or FB until t is within specified limits.
PD
LOCK
CC
Document Number: 38-07138 Rev. *N
Page 10 of 21
CY7B991
CY7B992
Switching Characteristics
Over the Operating Range
CY7B991-7
CY7B992-7
Parameter [43, 44]
Description
Unit
Min
15
Typ
–
Max
30
50
80
–
Min
15
Typ
–
Max
30
fNOM
Operating Clock Frequency FS = LOW [43, 45]
FS = MID [43, 45]
in MHz
MHz
25
–
25
–
50
FS = HIGH [43, 45]
40
–
40
–
80 [46]
tRPWH
tRPWL
tU
REF Pulse Width HIGH
5.0
5.0
–
5.0
5.0
–
–
ns
ns
REF Pulse Width LOW
–
–
–
–
Programmable Skew Unit
See Table 1 on page 4
tSKEWPR
tSKEW0
tSKEW1
Zero Output Matched-Pair Skew (XQ0, XQ1) [47, 48]
Zero Output Skew (All Outputs) [47, 49]
–
–
–
0.1
0.3
0.6
0.25
0.75
1.0
–
–
–
0.1
0.3
0.6
0.25
0.75
1.0
ns
ns
ns
Output Skew (Rise-Rise, Fall-Fall, Same Class
Outputs) [47, 50]
tSKEW2
tSKEW3
tSKEW4
Output Skew (Rise-Fall, Nominal-Inverted,
Divided-Divided) [47, 50]
–
–
–
1.0
0.7
1.2
1.5
1.2
1.7
–
–
–
1.0
0.7
1.2
1.5
1.2
1.7
ns
ns
ns
Output Skew (Rise-Rise, Fall-Fall, Different Class
Outputs) [47, 50]
Output Skew (Rise-Fall, Nominal-Divided,
Divided-Inverted) [17, 20]
tDEV
Device-to-Device Skew[51, 52]
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation[53]
Output HIGH Time Deviation from 50%[54, 55]
Output LOW Time Deviation from 50%[54, 55]
Output Rise Time [54, 56]
Output Fall Time [54, 56]
PLL Lock Time [57]
Cycle-to-Cycle Output Jitter RMS[51]
Peak-to-Peak [51]
–
–0.7
–1.2
–
–
0.0
0.0
–
1.65
+0.7
+1.2
3
–
–0.7
–1.5
–
–
0.0
0.0
–
1.65
+0.7
+1.5
5.5
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
tPD
tODCV
tPWH
tPWL
tORISE
tOFALL
tLOCK
tJR
–
–
3.5
2.5
2.5
0.5
25
–
–
5.5
0.15
0.15
–
1.5
1.5
–
0.5
0.5
–
3.0
3.0
–
5.0
5.0
0.5
–
–
–
–
25
–
–
200
–
–
200
Notes
43. The level is set on FS is determined by the “normal” operating frequency (fNOM) of the VCO and Time Unit Generator (see Logic Block Diagram). Nominal frequency
(
) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB
fNOM
inputs are f
when the output connected to FB is undivided. The frequency of the REF and FB inputs are fNOM/2 or fNOM/4 when the part is configured for a
NOM
frequency multiplication by using a divided output as the FB input.
44. Test measurement levels for the CY7B991 are TTL levels (1.5 V to 1.5 V). Test measurement levels for the CY7B992 are CMOS levels (V /2 to V /2). Test
CC
CC
conditions assume signal transition times of 2 ns or less and output loading as shown in the Figure 3 on page 8 unless otherwise specified.
45. For all tristate inputs, HIGH indicates a connection to V , LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry
CC
holds an unconnected input to V /2.
CC
46. Except as noted, all CY7B992-2 and -5 timing parameters are specified to 80 MHz with a 30 pF load.
47. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same t delay is selected when all are loaded with
U
50 pF and terminated with 50 to 2.06 V (CY7B991) or V /2 (CY7B992).
CC
48. t
49. t
is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0t .
SKEWPR
U
is defined as the skew between outputs when they are selected for 0t . Other outputs are divided or inverted but not shifted.
SKEW0
U
50. C = 0 pF. For C = 30 pF, t = 0.35 ns.
L
L
SKEW0
51. Guaranteed by statistical correlation. Tested initially and after any design or process changes that affect these parameters.
52. t
53. t
is the output-to-output skew between any two devices operating under the same conditions (V ambient temperature, air flow, and so on.)
DEV
CC
is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in t
and t
specifications.
SKEW4
ODCV
SKEW2
54. Specified with outputs loaded with 30 pF for the CY7B99X-2 and -5 devices and 50 pF for the CY7B99X-7 devices. Devices are terminated through 50 to 2.06 V
(CY7B991) or V /2 (CY7B992).
CC
55. tPWH is measured at 2.0 V for the CY7B991 and 0.8 V for the CY7B992. tPWL is measured at 0.8V for the CY7B991 and 0.2 V for the CY7B992.
CC
CC
56. t
57. t
and t
measured between 0.8V and 2.0V for the CY7B991 or 0.8 V and 0.2 V for the CY7B992.
ORISE
OFALL CC CC
is the time that is required before synchronization is achieved. This specification is valid only after V is stable and within normal operating limits. This parameter
is measured from the application of a new signal or frequency at REF or FB until t is within specified limits.
PD
LOCK
CC
Document Number: 38-07138 Rev. *N
Page 11 of 21
CY7B991
CY7B992
AC Timing Diagrams
t
t
RPWL
REF
t
RPWH
REF
t
t
ODCV
PD
t
ODCV
FB
Q
t
JR
t
t
t
t
SKEWPR,
SKEW0,1
SKEWPR,
SKEW0,1
OTHERQ
t
SKEW2
t
SKEW2
INVERTED Q
t
SKEW3,4
t
t
SKEW3,4
t
SKEW3,4
REF DIVIDED BY 2
REF DIVIDED BY 4
t
SKEW1,3, 4
SKEW2,4
Document Number: 38-07138 Rev. *N
Page 12 of 21
CY7B991
CY7B992
Operational Mode Descriptions
Figure 4. Zero Skew and Zero Delay Clock Driver
REF
LOAD
Z
Z
0
L1
L2
FB
SYSTEM
CLOCK
REF
FS
LOAD
LOAD
4Q0
4Q1
4F0
4F1
0
3Q0
3Q1
3F0
3F1
L3
L4
2F0
2F1
2Q0
2Q1
Z
0
1F0
1F1
1Q0
1Q1
LOAD
TEST
Z
0
LENGTH L1 = L2 = L3 = L4
Figure 4 shows the PSCB configured as a zero skew clock
buffer. In this mode the 7B991/992 is used as the basis for a
low-skew clock distribution tree. When all of the function select
inputs (× F0, × F1) are left open, the outputs are aligned and each
drives a terminated transmission line to an independent load.
The FB input is tied to any output in this configuration and the
operating frequency range is selected with the FS pin. The
low-skew specification, coupled with the ability to drive
terminated transmission lines (with impedances as low as
50 ohms), enables efficient printed circuit board design.
Figure 5. Programmable Skew Clock Driver
REF
LOAD
Z
0
L1
L2
FB
REF
FS
SYSTEM
CLOCK
LOAD
LOAD
4Q0
4Q1
4F0
4F1
Z
0
3Q0
3Q1
3F0
3F1
L3
L4
2F0
2F1
2Q0
2Q1
Z
0
1F0
1F1
1Q0
1Q1
LOAD
TEST
Z
0
LENGTH L1 = L2
L3 < L2 by 6 inches
L4 > L2 by 6 inches
Figure 5 shows a configuration to equalize skew between metal
traces of different lengths. In addition to low skew between
outputs, the PSCB is programmed to stagger the timing of its
outputs. Each of the four groups of output pairs are programmed
to different output timing. Skew timing is adjusted over a wide
range in small increments with the appropriate strapping of the
Document Number: 38-07138 Rev. *N
Page 13 of 21
CY7B991
CY7B992
function select pins. In this configuration the 4Q0 output is fed
back to FB and configured for zero skew. The other three pairs
of outputs are programmed to yield different skews relative to the
feedback. By advancing the clock signal on the longer traces or
retarding the clock signal on shorter traces, all loads can receive
the clock pulse at the same time.
Figure 7. Frequency Multiplier with Skew Connections
REF
In this illustration the FB input is connected to an output with 0 ns
skew (× F1, × F0 = MID) selected. The internal PLL synchronizes
the FB and REF inputs and aligns their rising edges to ensure
that all outputs have precise phase alignment.
FB
20 MHz
REF
FS
40 MHz
4Q0
4Q1
4F0
4F1
20 MHz
80 MHz
Clock skews are advanced by ±6 time units (tU) when using an
output selected for zero skew as the feedback. A wider range of
delays is possible if the output connected to FB is also skewed.
Since “Zero Skew”, +tU, and –tU are defined relative to output
groups, and since the PLL aligns the rising edges of REF and
FB, you can create wider output skews by proper selection of the
× Fn inputs. For example, a +10 tU between REF and 3Qx is
achieved by connecting 1Q0 to FB and setting 1F0 = 1F1 = GND,
3F0 = MID, and 3F1 = High. (Since FB aligns at –4tU and 3Qx
skews to +6tU, a total of +10tU skew is realized.) Many other
configurations are realized by skewing both the outputs used as
the FB input and skewing the other outputs.
3Q0
3Q1
3F0
3F1
2F0
2F1
2Q0
2Q1
1Q0
1Q1
1F0
1F1
TEST
Figure 7 shows the PSCB configured as a clock multiplier. The
3Q0 output is programmed to divide by four and is sent to FB.
This causes the PLL to increase its frequency until the 3Q0 and
3Q1 outputs are locked at 20 MHz while the 1Qx and 2Qx
outputs run at 80 MHz. The 4Q0 and 4Q1 outputs are
programmed to divide by two, that results in a 40 MHz waveform
at these outputs. Note that the 20 and 40 MHz clocks fall
simultaneously and are out of phase on their rising edge. This
enables the designer to use the rising edges of the 1⁄2 frequency
and 1⁄4 frequency outputs without concern for rising edge skew.
The 2Q0, 2Q1, 1Q0, and 1Q1 outputs run at 80 MHz and are
skewed by programming their select inputs accordingly. Note
that the FS pin is wired for 80 MHz operation because that is the
frequency of the fastest output.
Figure 6. Inverted Output Connections
REF
FB
REF
FS
4Q0
4Q1
4F0
4F1
3Q0
3Q1
Figure 8. Frequency Divider Connections
3F0
3F1
REF
2Q0
2Q1
2F0
2F1
1Q0
1Q1
1F0
1F1
FB
REF
20 MHz
FS
TEST
10 MHz
4Q0
4F0
4Q1
4F1
5 MHz
Figure 6 shows an example of the invert function of the PSCB.
In this example the 4Q0 output used as the FB input is
programmed for invert (4F0 = 4F1 = HIGH) while the other three
pairs of outputs are programmed for zero skew. When 4F0 and
4F1 are tied high, 4Q0 and 4Q1 become inverted zero phase
outputs. The PLL aligns the rising edge of the FB input with the
rising edge of the REF. This causes the 1Q, 2Q, and 3Q outputs
to become the “inverted” outputs with respect to the REF input.
It is possible to have 2 inverted and 6 non-inverted outputs or 6
inverted and 2 non-inverted outputs by selecting the output
connected to FB. The correct configuration is determined by the
need for more (or fewer) inverted outputs. 1Q, 2Q, and 3Q
outputs can also be skewed to compensate for varying trace
delays independent of inversion on 4Q.
3Q0
3Q1
3F0
3F1
20 MHz
2Q0
2Q1
2F0
2F1
1F0
1F1
1Q0
1Q1
TEST
Figure 8 demonstrates the PSCB in a clock divider application.
2Q0 is fed back to the FB input and programmed for zero skew.
3Qx is programmed to divide by four. 4Qx is programmed to
divide by two. Note that the falling edges of the 4Qx and 3Qx
outputs are aligned. This enables the use of rising edges of the
1
1
⁄
frequency and
⁄
frequency without concern for skew
2
4
mismatch. The 1Qx outputs are programmed to zero skew and
Document Number: 38-07138 Rev. *N
Page 14 of 21
CY7B991
CY7B992
are aligned with the 2Qx outputs. In this example, the FS input
is grounded to configure the device in the 15 MHz to 30 MHz
range since the highest frequency output is running at 20 MHz.
Figure 9 shows some of the functions that are selectable on the
3Qx and 4Qx outputs. These include inverted outputs and
outputs that offer divide-by-2 and divide-by-4 timing. An inverted
output enables the system designer to clock different
subsystems on opposite edges, without suffering from the pulse
asymmetry typical of non-ideal loading. This function enables
each of the two subsystems to clock 180 degrees out of phase
and align within the skew specifications.
feature, an external divider is added, and the propagation delay
of the divider adds to the skew between the different clock
signals.
These divided outputs, coupled with the Phase Locked Loop,
enables the PSCB to multiply the clock rate at the REF input by
either two or four. This mode enables the designer to distribute
a low frequency clock between various portions of the system,
and then locally multiply the clock rate to a more suitable
frequency, still maintaining the low skew characteristics of the
clock driver. The PSCB performs all of the functions described in
this section at the same time. It multiplies by two and four or
divides by two (and four) at the same time. In other words, it is
shifting its outputs over a wide range or maintaining zero skew
between selected outputs.
The divided outputs offer a zero delay divider for portions of the
system that need the clock divided by either two or four, and still
remain within a narrow skew of the “1X” clock. Without this
Figure 9. Multi-Function Clock Driver
REF
LOAD
Z
0
80 MHz
INVERTED
FB
REF
FS
20 MHz
DISTRIBUTION
CLOCK
LOAD
LOAD
4Q0
4Q1
4F0
4F1
20 MHz
Z
0
3Q0
3Q1
2Q0
2Q1
3F0
3F1
2F0
2F1
80 MHz
ZERO SKEW
Z
0
1Q0
1Q1
1F0
LOAD
80 MHz
SKEWED –3.125 ns (–4tU)
1F1
TEST
Z
0
Document Number: 38-07138 Rev. *N
Page 15 of 21
CY7B991
CY7B992
Figure 10. Board-to-Board Clock Distribution
LOAD
LOAD
REF
Z
0
L1
FB
SYSTEM
CLOCK
REF
FS
L2
Z
0
4Q0
4Q1
4F0
4F1
3Q0
3Q1
3F0
3F1
LOAD
L3
2F0
2F1
2Q0
2Q1
Z
0
1F0
1F1
1Q0
1Q1
L4
FB
REF
TEST
FS
LOAD
4Q0
4Q1
4F0
4F1
3F0
3F1
2F0
2F1
Z
0
3Q0
3Q1
2Q0
2Q1
LOAD
1F0
1Q0
1Q1
1F1
TEST
Figure 10 shows the CY7B991 and 992 connected in series to
construct a zero skew clock distribution tree between boards.
Delays of the downstream clock buffers are programmed to
compensate for the wire length (that is, select negative skew
equal to the wire delay) necessary to connect them to the master
clock source, approximating a zero delay clock tree. Cascaded
clock buffers accumulates low frequency jitter because of the
non-ideal filtering characteristics of the PLL filter. Do not connect
more than two clock buffers in series.
Document Number: 38-07138 Rev. *N
Page 16 of 21
CY7B991
CY7B992
Ordering Information
Accuracy
Operating
Ordering Code
Package Type
(ps)
Range
Industrial
Industrial
Industrial
Industrial
500
CY7B991-5JI
CY7B991-5JIT
CY7B991-7JI
CY7B992-7JI
32-pin PLCC
32-pin PLCC - Tape and Reel
32-pin PLCC
750
750
32-pin PLCC
Pb-free
250
CY7B991-2JXC
CY7B991-2JXCT
CY7B991-5JXC
CY7B991-5JXCT
CY7B991-5JXI
CY7B991-5JXIT
CY7B991-7JXC
CY7B991-7JXCT
CY7B991-7JXI
32-pin PLCC
Commercial
Commercial
Commercial
Commercial
Industrial
32-pin PLCC - Tape and Reel
32-pin PLCC
500
32-pin PLCC - Tape and Reel
32-pin PLCC
32-pin PLCC - Tape and Reel
32-pin PLCC
Industrial
750
500
Commercial
Commercial
Industrial
32-pin PLCC - Tape and Reel
32-pin PLCC
CY7B992-5JXI (Not
32-pin PLCC
Industrial
Recommended for New Designs)
CY7B992-5JXIT
32-pin PLCC - Tape and Reel
Industrial
Ordering Code Definitions
X
J
CY 7B99X
–
X
X
X
X = blank or T
blank = Tube; T = Tape and Reel
Temperature: X = C or I
C = Commercial; I = Industrial
X = Pb-free, blank = not Pb-free
Package Type: J = 32-pin PLCC package
Speed grade: X = 2 ps or 5 ps or 7 ps, based on propagation delay
Base part number: 7B99X = 7B991 or 7B992
7B991 = Clock buffer with TTL outputs
7B992 = Clock buffer with CMOS outputs
Company ID: CY = Cypress
Document Number: 38-07138 Rev. *N
Page 17 of 21
CY7B991
CY7B992
Package Diagram
Figure 11. 32-pin PLCC (0.453 × 0.553 inches) J32 Package Outline, 51-85002
51-85002 *E
Document Number: 38-07138 Rev. *N
Page 18 of 21
CY7B991
CY7B992
Acronyms
Document Conventions
Units of Measure
Acronym
Description
CMOS
FB
Complementary Metal-Oxide Semiconductor
Feedback
Symbol
°C
Unit of Measure
degree Celsius
megahertz
microampere
milliampere
millisecond
milliwatt
PLCC
PLL
Plastic Leaded Chip Carrier
Phase-Locked Loop
MHz
µA
mA
ms
mW
ns
PSCB
TTL
Programmable Skew Clock Buffers
Transistor-Transistor Logic
Voltage Controlled Oscillator
VCO
nanosecond
ohm
%
percent
pF
ps
picofarad
picosecond
volt
V
Document Number: 38-07138 Rev. *N
Page 19 of 21
CY7B991
CY7B992
Document History Page
Document Title: CY7B991/CY7B992, Programmable Skew Clock Buffer
Document Number: 38-07138
Orig. of
Change
Submission
Date
Rev.
ECN
Description of Change
**
110247
SZV
12/19/01
Changed Specification number: 38-00513 to 38-07138.
*A
1199925
KVM /
AESA
See ECN Updated Features (Remove Compatible with a Pentium™-based processor).
Updated Ordering Information (Added Pb-free part numbers, Update package
names in Ordering Information table).
*B
*C
*D
1286064
2750166
2761988
AESA
TSAI
CXQ
See ECN Changed status from Preliminary to Final.
08/10/09
09/10/09
Post to external web.
Updated Ordering Information (Fixed Ordering Information table replacement
error of “lead” with “Pb”).
*E
2894960
KVM
03/18/10
Updated Ordering Information (Removed following obsolete parts from the
ordering information table: CY7B991-7LMB, CY7B992-7LMB, CY7B992-5JI,
CY7B992-5JIT).
Updated Package Diagram.
Updated sales links
Added Table of Contents.
*F
2905889
2950368
KVM
KVM
04/06/2010 Updated Ordering Information (Removed inactive part numbers
CY7B991-2JC, CY7B991-2JCT, CY7B991-5JC, CY7B991-5JCT,
CY7B991-7JC, CY7B991-7JCT, CY7B992-2JC and CY7B992-2JCT).
*G
06/11/2010 Updated Operating Range (Removed Military temperature range).
Removed Military Specifications.
Updated Ordering Information (Added part numbers CY7B992-7JXC and
CY7B992-7JXCT).
*H
3045340
BASH
10/07/2010 Updated Ordering Information (Removed inactive part numbers CY7B992-5JC
and CY7B992-5JCT).
Added Ordering Code Definitions.
*I
3201434
3560698
BASH
PURU
03/21/2011 Added Acronyms and Units of Measure.
*J
03/24/2012 Updated Ordering Information (Added part number CY7B991-7JXI).
Updated Package Diagram.
*K
*L
4334627
4403827
CINM
AJU
04/06/2014 Updated to new template.
Completing Sunset Review.
06/10/2014 Updated Ordering Information:
No change in part numbers.
Added “Not Recommended for New Designs” against the MPN
“CY7B992-5JXI”.
*M
*N
4570101
5259008
AJU
PSR
11/14/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Ordering Information:
Removed the prune part numbers CY7B992-7JC, CY7B992-7JCT,
CY7B992-7JXC, and CY7B992-7JXCT.
05/04/2016 Updated Features:
Replaced “32-pin PLCC/LCC package” with “32-pin PLCC package”.
Updated Electrical Characteristics:
Updated Note 7 (Replaced “FC = F < C” with “FC = F × C”).
Added Thermal Resistance.
Updated Package Diagram:
spec 51-85002 – Changed revision from *D to *E.
Updated to new template.
Document Number: 38-07138 Rev. *N
Page 20 of 21
CY7B991
CY7B992
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
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closest to you, visit us at Cypress Locations.
®
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Forums | Projects | Video | Blogs | Training | Components
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© Cypress Semiconductor Corporation, 2001-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-07138 Rev. *N
Revised May 4, 2016
Page 21 of 21
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