CY7B9910-7SCT [CYPRESS]
PLL Based Clock Driver, 7B Series, 8 True Output(s), 0 Inverted Output(s), BICMOS, PDSO24, 0.300 INCH, MO-119, SOIC-24;
| 型号： | CY7B9910-7SCT |
| 厂家： | 
CYPRESS |
| 描述： | PLL Based Clock Driver, 7B Series, 8 True Output(s), 0 Inverted Output(s), BICMOS, PDSO24, 0.300 INCH, MO-119, SOIC-24 信息通信管理 光电二极管 |
| 文件： | 总11页 (文件大小：356K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7B9910
CY7B9920
Low Skew Clock Buffer
Features
Block Diagram Description
■ All Outputs Skew <100 ps typical (250 max.)
■ 15 to 80 MHz Output Operation
■ Zero Input to Output Delay
Phase Frequency Detector and Filter
The Phase Frequency Detector and Filter blocks accept inputs
from the reference frequency (REF) input and the feedback (FB)
input and generate correction information to control the
frequency of the Voltage Controlled Oscillator (VCO). These
blocks, along with the VCO, form a Phase Locked Loop (PLL)
that tracks the incoming REF signal.
■ 50% Duty Cycle Outputs
■ Outputs drive 50Ω terminated lines
■ Low Operating Current
VCO
■ 24-pin SOIC Package
The VCO accepts analog control inputs from the PLL filter block
and generates a frequency. The operational range of the VCO is
determined by the FS control pin.
■ Jitter: <200 ps Peak to Peak, <25 ps RMS
Functional Description
The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer
low skew system clock distribution. These multiple output clock
drivers optimize the timing of high performance computer
systems. Each of the eight individual drivers can drive terminated
transmission lines with impedances as low as 50Ω. They deliver
minimal and specified output skews and full swing logic levels
(CY7B9910 TTL or CY7B9920 CMOS).
The completely integrated PLL enables “zero delay” capability.
External divide capability, combined with the internal PLL, allows
distribution of a low frequency clock that is multiplied by virtually
any factor at the clock destination. This facility minimizes clock
distribution difficulty while allowing maximum system clock
speed and flexibility.
Logic Block Diagram
TEST
VOLTAGE
PHASE
FB
FREQ
DET
FILTER
CONTROLLED
OSCILLATOR
REF
FS
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Cypress Semiconductor Corporation
Document Number: 38-07135 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 10, 2009
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CY7B9910
CY7B9920
Pinouts
Figure 1. Pin Configuration – 24-Pin (300-Mil) Molded SOIC S13
SOIC
Top View
REF
1
24
23
22
21
GND
TEST
NC
V
CCQ
2
FS
NC
3
4
GND
V
CCQ
20
19
18
17
16
15
5
V
CCN
6
V
CCN
7B9910
7B9920
Q7
Q6
GND
Q5
Q4
Q0
7
Q1
GND
Q2
8
9
10
11
12
14
13
Q3
V
CCN
V
CCN
FB
Table 1. Pin Definition
Signal Name
IO
Description
REF
I
Reference frequency input. This input supplies the frequency and timing against which all functional
variations are measured.
FB
I
I
PLL feedback input (typically connected to one of the eight outputs).
Three level frequency range select.
Three level select. See TEST MODE.
Clock outputs.
FS[1,2,3]
TEST
Q[0..7]
VCCN
VCCQ
GND
I
O
PWR
PWR
PWR
Power supply for output drivers.
Power supply for internal circuitry.
Ground.
Test Mode
The TEST input is a three level input. In normal system operation, this pin is connected to ground, allowing the CY7B9910 and
CY7B9920 to operate as described in Block Diagram Description. For testing purposes, any of the three level inputs can have a
removable jumper to ground or be tied LOW through a 100Ω resistor. This enables an external tester to change the state of these pins.
If the TEST input is forced to its MID or HIGH state, the device operates with its internal phase locked loop disconnected and input
levels supplied to REF directly control all outputs. Relative output-to-output functions are the same as in normal mode.
Notes
1. For all three state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination
circuitry holds an unconnected input to VCC/2.
2. The level to be set on FS is determined by the “normal” operating frequency (fNOM) of the VCO (see Logic Block Diagram). The frequency appearing at the REF
and FB inputs are fNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs are fNOM/X when the device is configured for a
frequency multiplication by using external division in the feedback path of value X.
3. When the FS pin is selected HIGH, the REF input must not transition upon power up until VCC reached 4.3V.
Document Number: 38-07135 Rev. *D
Page 2 of 11
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CY7B9910
CY7B9920
Maximum Ratings
Operating Range
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Ambient
Temperature
Range
VCC
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied ............................................–55°C to +125°C
Commercial
0°C to +70°C
–40°C to +85°C
5V ± 10%
5V ± 10%
Industrial
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
Output Current into Outputs (LOW)............................. 64 mA
Static Discharge Voltage............................................>2001V
(MIL-STD-883, Method 3015)
Latch Up Current .....................................................>200 mA
Document Number: 38-07135 Rev. *D
Page 3 of 11
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CY7B9910
CY7B9920
Electrical Characteristics
Over the Operating Range
CY7B9910
CY7B9920
Parameter
Description
Test Conditions
VCC = Min, IOH = –16 mA
VCC = Min, IOH =–40 mA
VCC = Min, IOL = 46 mA
VCC = Min, IOL = 46 mA
Min
Max
Min
Max
Unit
VOH
Output HIGH Voltage
2.4
V
VCC–0.75
VOL
Output LOW Voltage
0.45
V
0.45
VCC
VIH
VIL
Input HIGH Voltage
(REF and FB inputs only)
2.0
–0.5
VCC
0.8
VCC
–
V
V
1.35
Input LOW Voltage
(REF and FB inputs only)
–0.5
1.35
VCC
VIHH
VIMM
VILL
IIH
Three Level Input HIGH
Voltage (Test, FS)[4]
Min ≤ VCC ≤ Max
Min ≤ VCC ≤ Max
Min ≤ VCC ≤ Max
VCC – 1V
VCC
VCC – 1V
V
Three Level Input MID
Voltage (Test, FS)[4]
VCC/2 – VCC/2 +
500 mV
VCC/2 –
500 mV
VCC/2 +
500 mV
V
500 mV
Three Level Input LOW
Voltage (Test, FS)[4]
0.0
1.0
0.0
–500
–50
1.0
V
Input HIGH Leakage Current VCC = Max, VIN = Max
(REF and FB inputs only)
10
10
μA
μA
μA
μA
μA
mA
mA
IIL
Input LOW Leakage Current VCC = Max, VIN = 0.4V
(REF and FB inputs only)
–500
–50
IIHH
IIMM
IILL
Input HIGH Current
(Test, FS)
VIN = VCC
VIN = VCC/2
VIN = GND
200
50
200
50
Input MID Current
(Test, FS)
Input LOW Current
(Test, FS)
–200
–250
–200
N/A
IOS
Output Short Circuit
Current[5]
VCC = Max, VOUT
= GND (25°C only)
VCCN = VCCQ = Max All Com’l
ICCQ
Operating Current Used by
Internal Circuitry
85
90
85
90
Input
Selects Open
Mil/Ind
ICCN
Output Buffer Current per
Output Pair[6]
VCCN = VCCQ = Max
14
19
mA
IOUT = 0 mA
Input Selects Open, fMAX
PD
Power Dissipation per
Output Pair[7]
VCCN = VCCQ = Max
78
104[5]
mW
IOUT = 0 mA
Input Selects Open, fMAX
Notes
4. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time
before all datasheet limits are achieved.
5. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B9920 outputs are not short circuit
protected.
6. Total output current per output pair is approximated by the following expression that includes device current plus load current:
CY7B9910:
ICCN = [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1
CY7B9920:
ICCN = [(3.5+.17F) + [((1160 – 2.8F)/Z) + (.0025FC)]N] x 1.1
Where
F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
FC = F < C.
7. Total power dissipation per output pair is approximated by the following expression that includes device power dissipation plus power dissipation due to the load circuit:
CY7B9910:
PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] x 1.1
CY7B9920:
PD = [(19.25+ 0.94F) + [((700 + 6F)/Z) + (.017FC)]N] x 1.1.See note 3 for variable definition.
Document Number: 38-07135 Rev. *D
Page 4 of 11
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CY7B9910
CY7B9920
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
CIN
Description
Test Conditions
Max
Unit
Input Capacitance
TA = 25°C, f = 1 MHz, VCC = 5.0V
10
pF
Figure 2. AC Test Loads and Waveforms
5V
3.0V
2.0V
=1.5V
0.8V
2.0V
=1.5V
0.8V
R1=130
R2=91
R1
R2
V
th
V
th
C = 50 pF (C = 30pF for –5 and – 2 devices)
L
L
0.0V
C
L
(Includes fixture and probe capacitance)
≤1ns
≤1ns
7B9910–3
7B9910–4
TTL AC Test Load (CY7B9910)
TTL Input Test Waveform (Cy7B9910)
V
CC
V
CC
R1=100
R2=100
80%
80%
R1
R2
C = 50 pF (C =30 pF for –5 and – 2devices)
V
th
= V /2
V
th
= V /2
L
L
CC
CC
(Includes fixture and probe capacitance)
20%
0.0V
20%
C
L
≤ 3ns
≤ 3ns
7B9910–5
7B9910–6
CMOS Input Test Waveform (CY7B9920)
CMOS AC Test Load (CY7B9920)
Switching Characteristics
Over the Operating Range [11]
CY7B9910–2[8]
CY7B9920–2[8]
Parameter
fNOM
Description
Min
Typ
Max
Min
Typ
Max
Unit
Operating Clock
FS = LOW[1, 2]
FS = MID[1, 2]
15
25
30
50
80
15
25
30
MHz
Frequency in MHz
50
80[12]
FS = HIGH[1, 2, 3]
40
40
tRPWH
tRPWL
tSKEW
tDEV
REF Pulse Width HIGH
REF Pulse Width LOW
5.0
5.0
5.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
Zero Output Skew (All Outputs)[13, 14]
Device-to-Device Skew[14, 15]
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation[16]
Output Rise Time[17, 18]
0.1
0.25
0.75
+0.25
+0.65
1.2
0.1
0.25
0.75
+0.25
+0.65
2.5
tPD
–0.25
–0.65
0.15
0.0
0.0
1.0
1.0
–0.25
–0.65
0.5
0.0
0.0
2.0
2.0
tODCV
tORISE
tOFALL
tLOCK
tJR
Output Fall Time[17, 18]
PLL Lock Time[19]
0.15
1.2
0.5
2.5
0.5
0.5
Cycle-to-Cycle Output Jitter Peak to Peak
RMS
200
25
200
25
Document Number: 38-07135 Rev. *D
Page 5 of 11
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CY7B9910
CY7B9920
Switching Characteristics
Over the Operating Range[11] (continued)
CY7B9910–5
Typ
CY7B9920–5
Typ
Parameter
fNOM
Description
Min
15
Max
30
Min
15
Max
Unit
Operating Clock
FS = LOW[1, 2]
FS = MID[1, 2]
30
MHz
Frequency in MHz
25
50
25
50
FS = HIGH[1, 2, 3]
40
80
40
80[12]
tRPWH
tRPWL
tSKEW
tDEV
REF Pulse Width HIGH
REF Pulse Width LOW
5.0
5.0
5.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
Zero Output Skew (All Outputs)[13, 14]
Device-to-Device Skew[8, 15]
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation[16]
Output Rise Time[17, 18
Output Fall Time[17, 18]
PLL Lock Time[19]
Cycle-to-Cycle Output Jitter Peak to Peak[8]
RMS[8]
0.25
0.5
1.0
0.25
0.5
1.0
tPD
–0.5
–1.0
0.15
0.15
0.0
0.0
1.0
1.0
+0.5
+1.0
1.5
–0.5
–1.0
0.5
0.0
0.0
2.0
2.0
+0.5
+1.0
3.0
tODCV
tORISE
tOFALL
tLOCK
tJR
1.5
0.5
3.0
0.5
0.5
200
25
200
25
Notes
8. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
9. CMOS output buffer current and power dissipation specified at 50 MHz reference frequency.
10. Applies to REF and FB inputs only.
11. Test measurement levels for the CY7B9910 are TTL levels (1.5V to 1.5V). Test measurement levels for the CY7B9920 are CMOS levels (VCC/2 to VCC/2). Test
conditions assume signal transition times of 2 ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
12. Except as noted, all CY7B9920–2 and –5 timing parameters are specified to 80 MHz with a 30 pF load.
13. tSKEW is defined as the time between the earliest and the latest output transition among all outputs when all are loaded with 50 pF and terminated with 50Ω to
2.06V (CY7B9910) or VCC/2 (CY7B9920).
14. tSKEW is defined as the skew between outputs.
15. tDEV is the output-to-output skew between any two outputs on separate devices operating under the same conditions (VCC, ambient temperature, air flow, and
so on).
16. tODCV is the deviation of the output from a 50% duty cycle.
17. Specified with outputs loaded with 30 pF for the CY7B99X0–2 and –5 devices and 50 pF for the CY7B99X0–7 devices. Devices are terminated through 50Ω to
2.06V (CY7B9910) or VCC/2 (CY7B9920).
18. tORISE and tOFALL measured between 0.8V and 2.0V for the CY7B9910 or 0.8VCC and 0.2VCC for the CY7B9920.
19. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This
parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
Document Number: 38-07135 Rev. *D
Page 6 of 11
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CY7B9910
CY7B9920
Switching Characteristics
Over the Operating Range[11] (continued)
CY7B9910–7
Typ
CY7B9920–7
Typ
Parameter
Description
Min
Max
Min
Max
Unit
fNOM
Operating Clock
Frequency in MHz
FS = LOW[1, 2]
15
30
15
30
MHz
FS = MID[1, 2]
FS = HIGH1, 2, 3]
25
40
50
80
25
40
50
80[12]
tRPWH
tRPWL
tSKEW
tDEV
REF Pulse Width HIGH
REF Pulse Width LOW
5.0
5.0
5.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
Zero Output Skew (All Outputs)[13, 14]
Device-to-Device Skew[8, 15]
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation[16]
Output Rise Time[17, 18]
Output Fall Time17, 18]
PLL Lock Time[19]
Cycle-to-Cycle Output Peak to Peak[8]
Jitter
0.3
0.75
1.5
0.3
0.75
1.5
tPD
–0.7
–1.2
0.15
0.15
0.0
0.0
1.5
1.5
+0.7
+1.2
2.5
–0.7
–1.2
0.5
0.0
0.0
3.0
3.0
+0.7
+1.2
5.0
tODCV
tORISE
tOFALL
tLOCK
tJR
2.5
0.5
5.0
0.5
0.5
200
25
200
25
tJR
RMS[8]
Document Number: 38-07135 Rev. *D
Page 7 of 11
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CY7B9910
CY7B9920
AC Timing Diagrams
Figure 3. AC Timing Diagrams
t
t
RPWL
REF
t
RPWH
REF
t
PD
t
ODCV
t
ODCV
FB
Q
t
JR
t
SKEW
t
SKEW
OTHERQ
Figure 4. Zero Skew and Zero Delay Clock Driver
REF
LOAD
Z
Z
0
FB
SYSTEM
CLOCK
REF
FS
LOAD
LOAD
Q0
Q1
0
Q2
Q3
Q4
Q5
Z
0
Q6
Q7
LOAD
TEST
Z
0
Document Number: 38-07135 Rev. *D
Page 8 of 11
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CY7B9910
CY7B9920
Operational Mode Descriptions
Figure 4 shows the device configured as a zero skew clock
buffer. In this mode the 7B9910/9920 is used as the basis for a
low skew clock distribution tree. The outputs are aligned and may
each drive a terminated transmission line to an independent
load. The FB input is tied to any output and the operating
frequency range is selected with the FS pin. The low skew speci-
fication, coupled with the ability to drive terminated transmission
lines (with impedances as low as 50 ohms), enables efficient
printed circuit board design.
Figure 3 shows the CY7B9910/9920 connected in series to
construct a zero skew clock distribution tree between boards.
Cascaded clock buffers accumulates low frequency jitter
because of the non-ideal filtering characteristics of the PLL filter.
Do not connect more than two clock buffers in series.
Figure 5. Board-to-Board Clock Distribution
LOAD
LOAD
REF
Z
0
FB
SYSTEM
CLOCK
REF
FS
Z
0
Q0
Q1
Q2
Q3
LOAD
Q4
Q5
Z
0
Q6
Q7
FB
REF
FS
TEST
LOAD
Q0
Q1
Z
0
Q2
Q3
Q4
Q5
LOAD
Q6
Q7
TEST
Document Number: 38-07135 Rev. *D
Page 9 of 11
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CY7B9910
CY7B9920
Ordering Information
Accuracy
Operating
Range
Ordering Code
Package Type
24-Pin Small Outline IC
(ps)
250
CY7B9910–2SC[20]
CY7B9910–2SCT[20]
CY7B9920–2SC[20]
CY7B9910–5SC[20]
CY7B9910–5SCT[20]
CY7B9910–5SI
Commercial
24-Pin Small Outline IC - Tape and Reel
24-Pin Small Outline IC
Commercial
Commercial
Commercial
Commercial
Industrial
500
24-Pin Small Outline IC
24-Pin Small Outline IC - Tape and Reel
24-Pin Small Outline IC
CY7B9910–5SIT
24-Pin Small Outline IC - Tape and Reel
24-Pin Small Outline IC
Industrial
CY7B9920–5SC[20]
CY7B9920–5SCT[20]
CY7B9920–5SI[20]
CY7B9910–7SC[20]
CY7B9910–7SI[20]
CY7B9920–7SC[20]
CY7B9920–7SI[20]
Commercial
Commercial
Industrial
24-Pin Small Outline IC - Tape and Reel
24-Pin Small Outline IC
750
24-Pin Small Outline IC
Commercial
Industrial
24-Pin Small Outline IC
24-Pin Small Outline IC
Commercial
Industrial
24-Pin Small Outline IC
Pb-Free
250
CY7B9910–2SXC
CY7B9910–2SXCT
CY7B9910–5SXC
CY7B9910–5SXCT
CY7B9910–5SXI
CY7B9910–5SXIT
CY7B9910–7SXC
CY7B9910–7SXCT
24-Pin Small Outline IC
Commercial
Commercial
Commercial
Commercial
Industrial
24-Pin Small Outline IC - Tape and Reel
24-Pin Small Outline IC
500
24-Pin Small Outline IC - Tape and Reel
24-Pin Small Outline IC
24-Pin Small Outline IC - Tape and Reel
24-Pin Small Outline IC
Industrial
750
Commercial
Commercial
24-Pin Small Outline IC - Tape and Reel
Package Diagram
Figure 6. 24-Pin (300-Mil) Molded SOIC S13
51-85025-*C
Note
20. Not recommended for new design.
Document Number: 38-07135 Rev. *D
Page 10 of 11
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CY7B9910
CY7B9920
Document History Page
Document Title: CY7B9910/CY7B9920 Low Skew Clock Buffer
Document Number: 38-07135
Orig. of Submission
Revision
ECN
Description of Change
Change
Date
**
110244
SZV
10/28/01
Change from Specification number: 38-00437 to 38-07135
*A
1199925 DPF/AESA
See ECN Added Pb-free parts in Ordering Information
Added Note 20: Not recommended for the new design
*B
*C
*D
1353343
2750166
2761988
AESA
TSAI
CXQ
See ECN Change status to final
08/10/09
09/10/09
Post to external web
Fixed typo from 100W resistor to 100Ω resistor.
Added “Not recommended for new designs” note to Pb devices.
Fixed incorrect instances of auto-replacement of “lead” to “Pb”.
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07135 Rev. *D
Revised September 10, 2009
Page 11 of 11
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
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trademarks referenced herein are property of the respective corporations. Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
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Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. All products and company names
mentioned in this document may be the trademarks of their respective holders.
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