概述
规格参数
数据手册
替代型号CY7B991V-2JXCT 概述
Low Voltage Programmable Skew Clock Buffer 低电压可编程偏移时钟缓冲器 时钟缓冲器、驱动器、锁相环 时钟驱动器
CY7B991V-2JXCT 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Obsolete | 零件包装代码： | QFJ |
| 包装说明： | LCC-32 | 针数： | 32 |
| Reach Compliance Code： | compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.31.00.01 | 风险等级： | 5.28 |
| 系列： | 7B | 输入调节： | STANDARD |
| JESD-30 代码： | R-PQCC-J32 | JESD-609代码： | e3 |
| 长度： | 13.97 mm | 逻辑集成电路类型： | PLL BASED CLOCK DRIVER |
| 最大I（ol）： | 0.035 A | 湿度敏感等级： | 3 |
| 功能数量： | 1 | 反相输出次数： | |
| 端子数量： | 32 | 实输出次数： | 4 |
| 最高工作温度： | 70 °C | 最低工作温度： | |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | QCCJ |
| 封装等效代码： | LDCC32,.5X.6 | 封装形状： | RECTANGULAR |
| 封装形式： | CHIP CARRIER | 峰值回流温度（摄氏度）： | 260 |
| 电源： | 3.3 V | Prop。Delay @ Nom-Sup： | 0.7 ns |
| 传播延迟（tpd）： | 0.25 ns | 认证状态： | Not Qualified |
| Same Edge Skew-Max（tskwd）： | 1 ns | 座面最大高度： | 3.556 mm |
| 子类别： | Clock Drivers | 最大供电电压 (Vsup)： | 3.63 V |
| 最小供电电压 (Vsup)： | 2.97 V | 标称供电电压 (Vsup)： | 3.3 V |
| 表面贴装： | YES | 温度等级： | COMMERCIAL |
| 端子面层： | Matte Tin (Sn) | 端子形式： | J BEND |
| 端子节距： | 1.27 mm | 端子位置： | QUAD |
| 处于峰值回流温度下的最长时间： | 30 | 宽度： | 11.43 mm |
| 最小 fmax： | 80 MHz | Base Number Matches： | 1 |
CY7B991V-2JXCT 数据手册
通过下载CY7B991V-2JXCT数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载CY7B991V
3.3V RoboClock®
Low Voltage Programmable Skew Clock Buffer
Features
Functional Description
■ All output pair skew <100 ps typical (250 max)
■ 3.75 to 80 MHz output operation
The CY7B991V Low voltage Programmable Skew Clock Buffer
(LVPSCB) offers user selectable control over system clock
functions. These multiple output clock drivers provide the system
integrator with functions necessary to optimize the timing of
high-performance computer systems. Each of the eight
individual drivers, arranged in four pairs of user controllable
outputs can drive terminated transmission lines with impedances
as low as 50Ω. This delivers minimal and specified output skews and
■ User selectable output functions
❐ Selectable skew to 18 ns
❐ Inverted and non-inverted
❐ Operation at 1⁄2 and 1⁄4 input frequency
❐ Operation at 2x and 4x input frequency (input as low as 3.75
MHz)
full swing logic levels (LVTTL).
Each output is hardwired to one of nine delay or function config-
urations. Delay increments of 0.7 to 1.5 ns are determined by the
operating frequency with outputs able to skew up to ±6 time units
from their nominal “zero” skew position. The completely
integrated PLL allows external load and transmission line delay
effects to be canceled. When this “zero delay” capability of the
LVPSCB is combined with the selectable output skew functions,
the user can create output-to-output delays of up to ±12 time
units.
■ Zero input to output delay
■ 50% duty cycle outputs
■ LVTTL outputs drive 50Ω terminated lines
■ Operates from a single 3.3V supply
■ Low operating current
■ 32-pin PLCC package
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
enable distribution of a low frequency clock that is multiplied by
two or four at the clock destination. This facility minimizes clock
distribution difficulty allowing maximum system clock speed and
flexibility.
■ Jitter 100 ps (typical)
Logic Block Diagram
TEST
PHASE
FREQ
DET
FB
VCO AND
TIME UNIT
GENERATOR
FILTER
REF
FS
4Q0
4Q1
4F0
4F1
SELECT
INPUTS
(THREE
LEVEL)
SKEW
SELECT
MATRIX
3Q0
3Q1
3F0
3F1
2Q0
2Q1
2F0
2F1
1Q0
1Q1
1F0
1F1
Cypress Semiconductor Corporation
Document Number: 38-07141 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 20, 2007
CY7B991V
3.3V RoboClock®
Pin Configuration
4
3
2
1
32 31 30
29
2F0
GND
1F1
1F0
5
6
3F1
4F0
28
27
4F1
7
8
9
26
25
24
23
CCQ
CY7B991V
V
CCN
V
CCN
4Q1
10
1Q0
1Q1
GND
GND
4Q0
GND
GND
11
12
22
21
13
14 15 16 17 18 19 20
Pin Definitions
Signal Name
IO
Description
REF
I
Reference frequency input. This input supplies the frequency and timing against which all functional
variations are measured.
FB
I
PLL feedback input (typically connected to one of the eight outputs).
Three level frequency range select. See Table 1.
Three level function select inputs for output pair 1 (1Q0, 1Q1). See Table 2
Three level function select inputs for output pair 2 (2Q0, 2Q1). See Table 2
Three level function select inputs for output pair 3 (3Q0, 3Q1). See Table 2
Three level function select inputs for output pair 4 (4Q0, 4Q1). See Table 2
Three level select. See test mode section under the block diagram descriptions.
Output pair 1. See Table 2
FS
I
1F0, 1F1
2F0, 2F1
3F0, 3F1
4F0, 4F1
TEST
I
I
I
I
I
1Q0, 1Q1
2Q0, 2Q1
3Q0, 3Q1
4Q0, 4Q1
VCCN
O
O
Output pair 2. See Table 2
O
Output pair 3. See Table 2
O
Output pair 4. See Table 2
PWR
PWR
PWR
Power supply for output drivers.
VCCQ
Power supply for internal circuitry.
GND
Ground.
Document Number: 38-07141 Rev. *C
Page 2 of 14
CY7B991V
3.3V RoboClock®
Skew Select Matrix
Block Diagram Description
The skew select matrix is comprised of four independent
sections. Each section has two low skew, high fanout drivers
(xQ0, xQ1), and two corresponding three level function select
(xF0, xF1) inputs. Table 2 shows the nine possible output
functions for each section as determined by the function select
inputs. All times are measured with respect to the REF input
assuming that the output connected to the FB input has 0tU
selected.
Phase Frequency Detector and Filter
The Phase Frequency Detector and Filter blocks accept inputs
from the reference frequency (REF) input and the feedback (FB)
input. They generate correction information to control the
frequency of the Voltage Controlled Oscillator (VCO). These
blocks, along with the VCO, form a Phase Locked Loop (PLL)
that tracks the incoming REF signal.
VCO and Time Unit Generator
Table 2. Programmable Skew Configurations[1]
The VCO accepts analog control inputs from the PLL filter block.
It generates a frequency that is used by the time unit generator
to create discrete time units, selected in the skew select matrix.
The operational range of the VCO is determined by the FS
control pin. The time unit (tU) is determined by the operating
frequency of the device and the level of the FS pin as shown in
Table 1.
Function Selects
Output Functions
1F1,2F1, 1F0,2F0, 1Q0,1Q1,
3F1, 4F1 3F0, 4F0 2Q0, 2Q1
3Q0, 3Q1 4Q0, 4Q1
LOW
LOW
LOW
MID
LOW
MID
–4tU
–3tU
–2tU
–1tU
0tU
Divide by 2 Divide by 2
–6tU
–4tU
–2tU
0tU
–6tU
–4tU
–2tU
0tU
Table 1. Frequency Range Select and tU Calculation[1]
fNOM (MHz)
HIGH
LOW
MID
1
Approximate
Frequency(MHz)At
Which tU = 1.0 ns
tU = -----------------------
FS[2, 3]
MID
fNOM × N
Min Max
where N =
MID
HIGH
LOW
MID
+1tU
+2tU
+3tU
+4tU
+2tU
+4tU
+6tU
+2tU
+4tU
+6tU
LOW
MID
15
25
40
30
50
80
44
26
16
22.7
38.5
62.5
HIGH
HIGH
HIGH
HIGH
HIGH
Divide by 4 Inverted
Notes
1. For all three state inputs, HIGH indicates a connection to V , LOW indicates a connection to GND, and MID indicates an open connection. Internal termination
CC
circuitry holds an unconnected input to V /2.
CC
2. The level to be set on FS is determined by the “normal” operating frequency (f
) of the V and Time Unit Generator (see ). Nominal frequency (f
) always
NOM
CO
NOM
appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB inputs is f
NOM
when the output connected to FB is undivided. The frequency of the REF and FB inputs is f
using a divided output as the FB input.
/2 or f
/4 when the part is configured for a frequency multiplication
NOM
NOM
3. When the FS pin is selected HIGH, the REF input must not transition upon power up until V has reached 2.8V.
CC
Document Number: 38-07141 Rev. *C
Page 3 of 14
CY7B991V
3.3V RoboClock®
Figure 1. Typical Outputs with Fb Connected to a Zero Skew Output Test Mode [4]
FBInput
REFInput
1Fx
2Fx
3Fx
4Fx
(N/A)
LM
– 6t
– 4t
– 3t
U
U
U
LL
LH
LM
(N/A)
LH
ML
ML
– 2t
– 1t
U
U
(N/A)
MM
MH
HL
MM
(N/A)
MH
0t
U
U
U
U
+1t
+2t
+3t
HM
(N/A)
HH
HL
HM
+4t
+6t
U
U
(N/A)
(N/A)
(N/A)
LL/HH
HH
DIVIDED
INVERT
Test Mode
The TEST input is a three level input. In normal system
operation, this pin is connected to ground, allowing the
CY7B991V to operate as explained in the “Block Diagram
Description” on page 3. For testing purposes, any of the three
level inputs can have a removable jumper to ground or be tied
LOW through a 100W resistor. This enables an external tester to
change the state of these pins.
If the TEST input is forced to its MID or HIGH state, the device
operates with its internal phase locked loop disconnected, and
input levels supplied to REF directly controls all outputs. Relative
output to output functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW), all outputs
function based only on the connection of their own function select
inputs (xF0 and xF1) and the waveform characteristics of the
REF input.
Note
4. FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 = MID).
Document Number: 38-07141 Rev. *C
Page 4 of 14
CY7B991V
3.3V RoboClock®
Operational Mode Descriptions
Figure 2. Zero Skew and Zero Delay Clock Driver
REF
LOAD
Z
Z
0
L1
L2
FB
SYSTEM
CLOCK
REF
FS
LOAD
LOAD
4Q0
4Q1
4F0
4F1
0
3Q0
3Q1
3F0
3F1
L3
L4
2F0
2F1
2Q0
2Q1
Z
0
1F0
1F1
1Q0
1Q1
LOAD
TEST
Z
0
LENGTH L1 = L2 = L3 = L4
Figure 2 shows the LVPSCB configured as a zero skew clock buffer. In this mode, the CY7B991V is the basis for a low skew clock
distribution tree. When all of the function select inputs (xF0, xF1) are left open, the outputs are aligned and drive a terminated
transmission line to an independent load. The FB input is tied to any output in this configuration and the operating frequency range
is selected with the FS pin. The low skew specification, coupled with the ability to drive terminated transmission lines (with impedances
as low as 50 ohms), enables efficient printed circuit board design.
Figure 3. Programmable Skew Clock Driver
REF
LOAD
Z
0
L1
L2
FB
REF
FS
SYS-
TEM
CLOCK
LOAD
LOAD
4Q0
4Q1
4F0
4F1
Z
0
3Q0
3Q1
3F0
3F1
L3
L4
2F0
2F1
2Q0
2Q1
Z
0
1F0
1F1
1Q0
1Q1
LOAD
TEST
Z
0
LENGTH L1 = L2
L3 < L2 by 6 inches
L4 > L2 by 6 inches
Figure 3 shows a configuration to equalize skew between metal traces of different lengths. In addition to low skew between outputs,
the LVPSCB is programmed to stagger the timing of its outputs. The four groups of output pairs are each programmed to different
output timing. Skew timing is adjusted over a wide range in small increments with the appropriate strapping of the function select pins.
In this configuration, the 4Q0 output is sent back to FB and configured for zero skew. The other three pairs of outputs are programmed
to yield different skews relative to the feedback. By advancing the clock signal on the longer traces or retarding the clock signal on
shorter traces, all loads receive the clock pulse at the same time.
Document Number: 38-07141 Rev. *C
Page 5 of 14
CY7B991V
3.3V RoboClock®
Figure 3 shows the FB input connected to an output with 0 ns
skew (xF1, xF0 = MID) selected. The internal PLL synchronizes
the FB and REF inputs and aligns their rising edges to make
certain that all outputs have precise phase alignment.
Figure 5. Frequency Multiplier with Skew Connections
REF
Clock skews are advanced by ±6 time units (tU) when using an
output selected for zero skew as the feedback. A wider range of
delays is possible if the output connected to FB is also skewed.
Since “Zero Skew”, +tU, and –tU are defined relative to output
groups, and the PLL aligns the rising edges of REF and FB, wider
output skews are created by proper selection of the xFn inputs.
For example, a +10 tU between REF and 3Qx is achieved by
connecting 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 = MID,
and 3F1 = High. (Since FB aligns at –4 tU, and 3Qx skews to +6
tU, a total of +10 tU skew is realized.) Many other configurations
are realized by skewing both the outputs used as the FB input
and skewing the other outputs.
FB
20 MHz
REF
FS
40 MHz
4Q0
4Q1
4F0
4F1
20 MHz
80 MHz
3Q0
3Q1
3F0
3F1
2F0
2F1
2Q0
2Q1
1Q0
1Q1
1F0
1F1
TEST
7B991V–12
Figure 4. Inverted Output Connections
Figure 5 shows the LVPSCB configured as a clock multiplier. The
3Q0 output is programmed to divide by four and is sent back to
FB. This causes the PLL to increase its frequency until the 3Q0
and 3Q1 outputs are locked at 20 MHz, while the 1Qx and 2Qx
outputs run at 80 MHz. The 4Q0 and 4Q1 outputs are
programmed to divide by two that results in a 40 MHz waveform
at these outputs. Note that the 20 and 40 MHz clocks fall simul-
taneously and are out of phase on their rising edge. This enables
the designer to use the rising edges of the 1⁄2 frequency and 1⁄4
frequency outputs without concern for rising edge skew. The
2Q0, 2Q1, 1Q0, and 1Q1 outputs run at 80 MHz and are skewed
by programming their select inputs accordingly. Note that the FS
pin is wired for 80 MHz operation as that is the frequency of the
fastest output.
REF
FB
REF
FS
4Q0
4Q1
4F0
4F1
3Q0
3Q1
3F0
3F1
2Q0
2Q1
2F0
2F1
1Q0
1Q1
1F0
1F1
Figure 6. Frequency Divider Connections
TEST
REF
7B991V–11
Figure 4 shows an example of the invert function of the LVPSCB.
In this example the 4Q0 output used as the FB input is
programmed for invert (4F0 = 4F1 = HIGH) while the other three
pairs of outputs are programmed for zero skew. When 4F0 and
4F1 are tied high, 4Q0 and 4Q1 become inverted zero phase
outputs. The PLL aligns the rising edge of the FB input with the
rising edge of the REF. This causes the 1Q, 2Q, and 3Q outputs
to become the “inverted” outputs to the REF input. By selecting
the output connected to FB, you can have two inverted and six
non-inverted outputs or six inverted and two non-inverted
outputs. The correct configuration is determined by the need for
more (or fewer) inverted outputs. 1Q, 2Q, and 3Q outputs are
also skewed to compensate for varying trace delays
independent of inversion on 4Q.
FB
REF
FS
20 MHz
10 MHz
4Q0
4F0
4Q1
4F1
5 MHz
3Q0
3Q1
3F0
3F1
20 MHz
2Q0
2Q1
2F0
2F1
1F0
1F1
1Q0
1Q1
TEST
7B991V–13
Figure 6 shows the LVPSCB in a clock divider application. 2Q0
is sent back to the FB input and programmed for zero skew. 3Qx
is programmed to divide by four. 4Qx is programmed to divide by
two. Note that the falling edges of the 4Qx and 3Qx outputs are
aligned. This enables use of the rising edges of the 1⁄2 frequency
and 1⁄4 frequency without concern for skew mismatch. The 1Qx
outputs are programmed to zero skew and are aligned with the
2Qx outputs. In this example, the FS input is grounded to
configure the device in the 15 to 30 MHz range since the highest
frequency output is running at 20 MHz.
Document Number: 38-07141 Rev. *C
Page 6 of 14
CY7B991V
3.3V RoboClock®
Figure 7 shows some of the functions that are selectable on the
3Qx and 4Qx outputs. These include inverted outputs and
outputs that offer divide-by-2 and divide-by-4 timing. An inverted
output enables the system designer to clock different
subsystems on opposite edges without suffering from the pulse
asymmetry typical of non-ideal loading. This function enables
each of the two subsystems to clock 180 degrees out of phase,
but still is aligned within the skew specification.
These divided outputs, coupled with the Phase Locked Loop,
enable the LVPSCB to multiply the clock rate at the REF input by
either two or four. This mode allows the designer to distribute a
low frequency clock between various portions of the system. It
also locally multiplies the clock rate to a more suitable frequency,
while still maintaining the low skew characteristics of the clock
driver. The LVPSCB performs all of the functions described in
this section at the same time. It can multiply by two and four or
divide by two (and four) at the same time that it shifts its outputs
over a wide range or maintains zero skew between selected
outputs.
The divided outputs offer a zero delay divider for portions of the
system that divide the clock by either two or four, and still remain
within a narrow skew of the “1X” clock. Without this feature, an
external divider is added, and the propagation delay of the
divider adds to the skew between the different clock signals.
.
Figure 7. Multi-Function Clock Driver
REF
LOAD
Z
0
80 MHz
INVERTED
FB
REF
FS
20 MHz
DISTRIBUTION
CLOCK
LOAD
LOAD
4Q0
4Q1
4F0
4F1
20 MHz
Z
0
3Q0
3Q1
2Q0
2Q1
3F0
3F1
2F0
2F1
80 MHz
ZERO SKEW
Z
0
1Q0
1Q1
1F0
LOAD
80 MHz
SKEWED –3.125 ns (–4tU)
1F1
TEST
Z
0
Document Number: 38-07141 Rev. *C
Page 7 of 14
CY7B991V
3.3V RoboClock®
Figure 8. Board-to-Board Clock Distribution
LOAD
LOAD
REF
Z
0
L1
FB
SYSTEM
CLOCK
REF
FS
L2
Z
0
4Q0
4Q1
4F0
4F1
3Q0
3Q1
3F0
3F1
LOAD
L3
2F0
2F1
2Q0
2Q1
Z
0
1F0
1F1
1Q0
1Q1
L4
FB
REF
TEST
FS
LOAD
4Q0
4Q1
4F0
4F1
3F0
3F1
2F0
2F1
Z
0
3Q0
3Q1
2Q0
2Q1
LOAD
1F0
1Q0
1Q1
1F1
TEST
Figure 8 shows the CY7B991V connected in series to construct a zero skew clock distribution tree between boards. Delays of the
downstream clock buffers are programmed to compensate for the wire length (that is, select negative skew equal to the wire delay)
necessary to connect them to the master clock source, approximating a zero delay clock tree. Cascaded clock buffers accumulate
low frequency jitter because of the non-ideal filtering characteristics of the PLL filter. Do not connect more than two clock buffers in a
series.
Static Discharge Voltage............................................>2001V
(MIL-STD-883, Method 3015)
Maximum Ratings
Operating outside these boundaries may affect the performance
and life of the device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Latch up Current......................................................>200 mA
Operating Range
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Range
Ambient Temperature
VCC
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
Output Current into Outputs (LOW)............................. 64 mA
Commercial
0°C to +70°C
3.3V ±
10%
Industrial
–40°C to +85°C
3.3V ±
10%
Document Number: 38-07141 Rev. *C
Page 8 of 14
CY7B991V
3.3V RoboClock®
Electrical Characteristics
Over the Operating Range[5]
CY7B991V
Parameter
VOH
Description
Test Conditions
Unit
Min
Max
Output HIGH Voltage
Output LOW Voltage
VCC = Min, IOH = –12 mA
VCC = Min, IOL = 35 mA
2.4
V
V
V
VOL
VIH
0.45
VCC
Input HIGH Voltage
(REF and FB inputs only)
2.0
–0.5
VIL
Input LOW Voltage
(REF and FB inputs only)
0.8
VCC
V
V
VIHH
VIMM
VILL
IIH
Three Level Input HIGH
Voltage (Test, FS, xFn)[6]
Min ≤ VCC ≤ Max.
Min ≤ VCC ≤ Max.
Min ≤ VCC ≤ Max.
0.87 * VCC
0.47 * VCC
0.0
Three Level Input MID
0.53 * VCC
0.13 * VCC
20
V
Voltage (Test, FS, xFn)[6]
Three Level Input LOW
Voltage (Test, FS, xFn)[6]
V
Input HIGH Leakage Current (REF VCC = Max, VIN = Max.
and FB inputs only)
μA
μA
IIL
Input LOW Leakage Current (REF VCC = Max, VIN = 0.4V
and FB inputs only)
–20
–50
IIHH
IIMM
IILL
Input HIGH Current (Test, FS, xFn) VIN = VCC
Input MID Current (Test, FS, xFn) VIN = VCC/2
Input LOW Current (Test, FS, xFn) VIN = GND
200
50
μA
μA
–200
–200
95
μA
IOS
Short Circuit Current[7]
VCC = MAx VOUT =GND (25° only)
mA
mA
ICCQ
Operating Current Used by Internal VCCN = VCCQ = Max, All
Com’l
Circuitry
Input Selects Open
Mil/Ind
100
19
ICCN
PD
‘
Output Buffer Current per Output VCCN = VCCQ = Max, IOUT = 0 mA
mA
Pair[8]
Input Selects Open, fMAX
Power Dissipation per Output
Pair[9]
VCCN = VCCQ = Max, IOUT = 0 mA
Input Selects Open, fMAX
104
mW
Notes
5. See the last page of this specification for Group A subgroup testing information.
6. These inputs are normally wired to V , GND, or left unconnected (actual threshold voltages vary as a percentage of V ). Internal termination resistors hold
CC
CC
unconnected inputs at V /2. If these inputs are switched, the function and timing of the outputs glitch and the PLL requires an additional t
CC
time before all
LOCK
datasheet limits are achieved.
7. CY7B991V is tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only.
8. Total output current per output pair is approximated by the following expression that includes device current plus load current:
CY7B991V: I
Where
= [(4 + 0.11F) + [((835 –3F)/Z) + (.0022FC)]N] x 1.1
CCN
F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
FC = F < C
9. These inputs are normally wired to V , GND, or left unconnected (actual threshold voltages vary as a percentage of V ). Internal termination resistors hold
CC
CC
unconnected inputs at V /2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional t
CC
time
LOCK
before all datasheet limits are achieved.
Document Number: 38-07141 Rev. *C
Page 9 of 14
CY7B991V
3.3V RoboClock®
Capacitance
Tested initially and after any design or process changes that may affect these parameters. [10]]
Parameter
CIN
Description
Test Conditions
Max
Unit
Input Capacitance
TA = 25°C, f = 1 MHz, VCC = 3.3V
10
pF
AC Test Loads and Waveforms
Figure 9. Test Loads and Waveforms
VCC
3.0V
2.0V
=1.5V
0.8V
2.0V
th
0.8V
R1=100
R2=100
R1
R2
V
th
V =1.5V
C = 30 pF
L
0.0V
C
L
(Includes fixture and probe capacitance)
≤ 1 ns
≤ 1 ns
TTL ACTest Load
TTL InputTest Waveform
Note
10. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-07141 Rev. *C
Page 10 of 14
CY7B991V
3.3V RoboClock®
Switching Characteristics – 5 Option
Over the Operating Range [2, 10]
CY7B991V–5
Typ
Parameter
Description
Unit
Min
15
Max
30
fNOM
Operating Clock Frequency in MHz
FS = LOW[1, 2]
FS = MID[1, 2]
FS = HIGH[1, 2]
MHz
25
50
40
80
tRPWH
tRPWL
tU
REF Pulse Width HIGH
REF Pulse Width LOW
Programmable Skew Unit
Zero Output Matched-Pair Skew (XQ0, XQ1)[14, 15]
Zero Output Skew (All Outputs)[[14, 15]
Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)[14, 18]
Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)[14, 18]
Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)14, 18]
Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)14, 18]
Device-to-Device Skew[13, 19]
5.0
5.0
ns
ns
See Table 1
tSKEWPR
tSKEW0
tSKEW1
tSKEW2
tSKEW3
tSKEW4
tDEV
0.1
0.25
0.5
0.7
1.0
0.7
1.0
1.25
+0.5
+1.0
2.5
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
0.25
0.6
0.5
0.5
0.5
tPD
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation[20]
Output HIGH Time Deviation from 50%[21]
Output LOW Time Deviation from 50%[21]
Output Rise Time[21, 22]
Output Fall Time[21, 22]
PLL Lock Time[22]
–0.5
–1.0
0.0
0.0
tODCV
tPWH
tPWL
tORISE
tOFALL
tLOCK
tJR
0.15
0.15
1.0
1.0
1.5
1.5
0.5
25
Cycle-to-Cycle Output Jitter
RMS[13]
Peak-to-Peak[13]
200
Notes
11. Test measurement levels for the CY7B991V are TTL levels (1.5V to 1.5V). Test conditionsassume signal transition times of 2 ns or less and output loading as shown
in the AC Test Loads and Waveforms unless otherwise specified.
12. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
13. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same t delay has been selected when all are
U
loaded with 30 pF and terminated with 50Ω to V /2 (CY7B991V).
CC
14. t
15. t
is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0t .
SKEWPR
U
is defined as the skew between outputs when they are selected for 0t . Other outputs are divided or inverted but not shifted.
SKEW0
U
16. C =0 pF. For C =30 pF, t =0.35 ns.
L
L
SKEW0
17. There are three classes of outputs: Nominal (multiple of t delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2
U
or Divide-by-4 mode).
18. t
19. t
is the output-to-output skew between any two devices operating under the same conditions (V ambient temperature, air flow, etc.)
DEV
CC
is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in t
and t
specifications.
ODCV
SKEW2
SKEW4
20. Specified with outputs loaded with 30 pF for the CY7B991V–5 and –7 devices. Devices are terminated through 50Ω to V /2.t
is measured at 2.0V. t
is
CC
PWH
PWL
measured at 0.8V.
21. t
22. t
and t
measured between 0.8V and 2.0V.
ORISE
LOCK
OFALL
is the time that is required before synchronization is achieved. This specification is valid only after V is stable and within normal operating limits. This parameter is
measured from the application of a new signal or frequency at REF or FB until t is within specified limits.
CC
PD
Document Number: 38-07141 Rev. *C
Page 11 of 14
CY7B991V
3.3V RoboClock®
Switching Characteristics – 7 Option
Over the Operating Range [2, 10]
CY7B991V–7
Typ
Parameter
Description
Unit
Min
15
Max
30
fNOM
Operating Clock
Frequency in MHz
FS = LOW[1, 2]
FS = MID[1, 2]
FS = HIGH[1, 2]
MHz
25
50
40
80
tRPWH
tRPWL
tU
REF Pulse Width HIGH
REF Pulse Width LOW
Programmable Skew Unit
5.0
5.0
ns
ns
See Table 1
tSKEWPR
tSKEW0
tSKEW1
tSKEW2
tSKEW3
tSKEW4
tDEV
Zero Output Matched Pair Skew (XQ0, XQ1)[14, 15]
Zero Output Skew (All Outputs)[14, 16]
0.1
0.25
0.75
1.0
1.5
1.2
1.7
1.65
+0.7
+1.2
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
0.3
0.6
1.0
0.7
1.2
Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)[13, 17]
Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)[14, 18]
Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)[14, 18]
Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)[14, 18]
Device-to-Device Skew[13, 19]
tPD
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation[19]
Output HIGH Time Deviation from 50%[20]
Output LOW Time Deviation from 50%[20]
Output Rise Time[20, 21]
Output Fall Time[20, 21]
PLL Lock Time[22]
–0.7
–1.2
0.0
0.0
tODCV
tPWH
tPWL
3.5
2.5
2.5
0.5
25
tORISE
tOFALL
tLOCK
tJR
0.15
0.15
1.5
1.5
Cycle-to-Cycle Output
Jitter
RMS[12]
Peak-to-Peak[12]
200
Document Number: 38-07141 Rev. *C
Page 12 of 14
CY7B991V
3.3V RoboClock®
Ordering Information
Operating
Range
Accuracy (ps)
Ordering Code
Package Type
32-Pb Plastic Leaded Chip Carrier
250
CY7B991V–2JC
CY7B991V–2JCT
CY7B991V–5JC
CY7B991V–5JCT
CY7B991V–5JI
CY7B991V–5JIT
CY7B991V–7JC
CY7B991V–7JCT
Commercial
Commercial
Commercial
Commercial
Industrial
32-Pb Plastic Leaded Chip Carrier – Tape and Reel
32-Pb Plastic Leaded Chip Carrier
500
750
32-Pb Plastic Leaded Chip Carrier – Tape and Reel
32-Pb Plastic Leaded Chip Carrier
32-Pb Plastic Leaded Chip Carrier – Tape and Reel
32-Pb Plastic Leaded Chip Carrier
Industrial
Commercial
Commercial
32-Pb Plastic Leaded Chip Carrier – Tape and Reel
Pb-Free
250
CY7B991V–2JXC
CY7B991V–2JXCT
CY7B991V–5JXC
CY7B991V–5JXCT
CY7B991V–5JXI
CY7B991V–5JXIT
CY7B991V–7JXC
CY7B991V–7JXCT
32-Pb Plastic Leaded Chip Carrier
Commercial
Commercial
Commercial
Commercial
Industrial
32-Pb Plastic Leaded Chip Carrier – Tape and Reel
32-Pb Plastic Leaded Chip Carrier
500
750
32-Pb Plastic Leaded Chip Carrier – Tape and Reel
32-Pb Plastic Leaded Chip Carrier
32-Pb Plastic Leaded Chip Carrier – Tape and Reel
32-Pb Plastic Leaded Chip Carrier
Industrial
Commercial
Commercial
32-Pb Plastic Leaded Chip Carrier – Tape and Reel
Package Diagram
Figure 10. 32-Pin Plastic Leaded Chip Carrier J65
51-85002-*B
Document Number: 38-07141 Rev. *C
Page 13 of 14
CY7B991V
3.3V RoboClock®
Document History Page
Document Title: CY7B991V 3.3V RoboClock® Low Voltage Programmable Skew Clock Buffer
Document Number: 38-07141
Orig. of
Change
REV.
ECN NO. Issue Date
Description of Change
**
110250
293239
12/17/01
See ECN
SZV
Change from Specification number: 38-00641 to 38-07141
*A
RGL
Added Pb-Free devices
Added typical value for Jitter (peak)
*B
*C
1199925
1286064
See ECN KVM/AESA Format change in Ordering Information Table
See ECN AESA Change status to final
© Cypress Semiconductor Corporation, 2001-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07141 Rev. *C
Revised June 20, 2007
Page 14 of 14
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
2
trademarks referenced herein are property of the respective corporations. Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
2
2
2
Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. RoboClock is a registered trademark
of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7B991V-2JXCT CAD模型
引脚图
封装焊盘图
CY7B991V-2JXCT 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| CY7B991V-2JC | CYPRESS | Low Voltage Programmable Skew Clock Buffer | 完全替代 |
|
| CY7B991V-2JXC | CYPRESS | Low Voltage Programmable Skew Clock Buffer | 完全替代 |
|
| CY7B991V-2JCT | CYPRESS | Low Voltage Programmable Skew Clock Buffer | 功能相似 |
|
CY7B991V-2JXCT 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| CY7B991V-5JC | CYPRESS | Low Voltage Programmable Skew Clock Buffer | 获取价格 |
|
| CY7B991V-5JCT | CYPRESS | Low Voltage Programmable Skew Clock Buffer | 获取价格 |
|
| CY7B991V-5JI | CYPRESS | Low Voltage Programmable Skew Clock Buffer | 获取价格 |
|
| CY7B991V-5JIT | CYPRESS | Low Voltage Programmable Skew Clock Buffer | 获取价格 |
|
| CY7B991V-5JXC | CYPRESS | Low Voltage Programmable Skew Clock Buffer | 获取价格 |
|
| CY7B991V-5JXCT | CYPRESS | Low Voltage Programmable Skew Clock Buffer | 获取价格 |
|
| CY7B991V-5JXI | CYPRESS | Low Voltage Programmable Skew Clock Buffer | 获取价格 |
|
| CY7B991V-5JXIT | CYPRESS | Low Voltage Programmable Skew Clock Buffer | 获取价格 |
|
| CY7B991V-7JC | CYPRESS | Low Voltage Programmable Skew Clock Buffer | 获取价格 |
|
| CY7B991V-7JCT | CYPRESS | Low Voltage Programmable Skew Clock Buffer | 获取价格 |
|
CY7B991V-2JXCT 相关文章
Bourns 密封通孔金属陶瓷微调电位计产品选型手册(英文版)
- 2024-09-20
- 6
Bourns 精密环境传感器产品选型手册(英文版)
- 2024-09-20
- 9
Bourns POWrTher 负温度系数(NTC)热敏电阻手册 (英文版)
- 2024-09-20
- 8
Bourns GMOV 混合过压保护组件产品选型手册(英文版)
- 2024-09-20
- 6
