CY7B9940V-2AXIT [CYPRESS]
High Speed Multifrequency PLL Clock Buffer; 高速多频PLL时钟缓冲器
| 型号： | CY7B9940V-2AXIT |
| 厂家： | 
CYPRESS |
| 描述： | High Speed Multifrequency PLL Clock Buffer |
| 文件： | 总11页 (文件大小：313K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RoboClockII™ Junior,
CY7B9930V, CY7B9940V
High Speed Multifrequency
PLL Clock Buffer
Features
■ 12–100 MHz (CY7B9930V), or 24–200 MHz (CY7B9940V)
■ Single 3.3V ± 10% supply
input/output operation
■ 44-pin TQFP package
■ Matched pair output skew < 200 ps
■ Zero input-to-output delay
Functional Description
The CY7B9930V and CY7B9940V High-Speed Multifrequency
PLL Clock Buffers offer user-selectable control over system
clock functions. This multiple output clock driver provides the
system integrator with functions necessary to optimize the timing
of high performance computer or communication systems.
■ 10 LVTTL 50% duty-cycle outputs capable of driving 50ω
terminated lines
■ Commercial temperature range with eight outputs at 200
MHz
Ten configurable outputs can each drive terminated transmission
lines with impedances as low as 50Ω while delivering minimal and
specified output skews at LVTTL levels. The outputs are arranged
in three banks. The FB feedback bank consists of two outputs,
which allows divide-by functionality from 1 to 12. Any one of
these ten outputs can be connected to the feedback input as well
as driving other inputs.
■ Industrial temperature range with eight outputs at 200 MHz
■ 3.3V LVTTL/LV differential (LVPECL), fault-tolerant and hot
insertable reference inputs
■ Multiply ratios of (1–6, 8, 10, 12)
■ Operation up to 12x input frequency
Selectable reference input is a fault tolerance feature that allows
smooth change over to secondary clock source, when the
primary clock source is not in operation. The reference inputs are
configurable to accommodate both LVTTL or differential
(LVPECL) inputs. The completely integrated PLL reduces jitter
and simplifies board layout.
■ Individual output bank disable for aggressive power
management and EMI reduction
■ Output high impedance option for testing purposes
■ Fully integrated PLL with lock indicator
■ Low cycle-to-cycle jitter (<100 ps peak-peak)
Block Diagram
FBKA
LOCK
Control Logic
Divide
Generator
Phase
Freq.
Detector
VCO
Filter
FS
REFA+
REFA–
REFB+
REFB–
REFSEL
3
3
Output_Mode
QFA0
QFA1
Divide
Matrix
3
3
FBDS0
FBDS1
Feedback Bank
Bank 2
2QA0
2QA1
2QB0
2QB1
DIS2
DIS1
1QA0
1QA1
Bank 1
1QB0
1QB1
Cypress Semiconductor Corporation
Document Number: 38-07271 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 8, 2007
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RoboClockII™ Junior,
CY7B9930V, CY7B9940V
Divide Matrix
Block Diagram Description
The Divide Matrix is comprised of three independent banks: two
banks of clock outputs and one bank for feedback. Each clock
output bank has two pairs of low-skew, high fanout output buffers
([1:2]Q[A:B][0:1]), and an output disable (DIS[1:2]).
Phase Frequency Detector and Filter
These two blocks accept signals from the REF inputs (REFA+,
REFA–, REFB+ or REFB–) and the FB input (FBKA). Correction
information is then generated to control the frequency of the
Voltage Controlled Oscillator (VCO). These two blocks, along
with the VCO, form a Phase-Locked Loop (PLL) that tracks the
incoming REF signal.
The feedback bank has one pair of low-skew, high fanout output
buffers (QFA[0:1]). One of these outputs may connect to the
selected feedback input (FBKA+). This feedback bank also has
two divider function selects FBDS[0:1].
The RoboClockII™ Junior has a flexible REF input scheme.
These inputs allow the use of either differential LVPECL or single
ended LVTTL inputs. To configure as single ended LVTTL inputs,
leave the complementary pin to 1.5V), then use the other input
pin as an LVTTL input. The REF inputs are also tolerant to hot
insertion.
The divide capabilities for each bank are shown in Table 2.
Table 2. Output Divider Function
Function
Output Divider Function
Selects
The REF inputs can be changed dynamically. When changing
from one reference input to the other reference input of the same
frequency, the PLL is optimized to ensure that the clock outputs
period is not less than the calculated system budget (tMIN = tREF
(nominal reference clock period) – tCCJ (cycle-to-cycle jitter) –
Feedback
FBDS1
FBDS0
Bank 1
Bank 2
Bank
LOW
LOW
LOW
MID
LOW
MID
/1
/1
/1
/1
/1
/1
/1
/1
/1
/1
/1
/1
/1
/1
/1
/1
/1
/1
/1
/2
t
PDEV (max. period deviation)) while reacquiring lock.
HIGH
LOW
MID
/3
/4
VCO, Control Logic, and Divide Generator
MID
/5
The VCO accepts analog control inputs from the PLL filter block.
The FS control pin setting determines the nominal operational
frequency range of the divide by one output (fNOM) of the device.
fNOM is directly related to the VCO frequency. There are two
versions of the RoboClockII Junior, a low speed device
(CY7B9930V) where fNOM ranges from 12 MHz to 100 MHz, and
a high speed device (CY7B9940V), which ranges from 24 MHz
to 200 MHz. The FS setting for each device is shown in Table 1.
The fNOM frequency is seen on “divide-by-one” outputs.
MID
HIGH
LOW
MID
/6
HIGH
HIGH
HIGH
/8
/10
/12
HIGH
Output Disable Description
The outputs of Bank 1 and Bank 2 can be independently put into
a HOLD OFF or high impedance state. The combination of the
Output_Mode and DIS[1:2] inputs determines the clock outputs’
state for each bank. When the DIS[1:2] is LOW, the outputs of
the corresponding bank are enabled. When the DIS[1:2] is HIGH,
the outputs for that bank are disabled to a high impedance (HI-Z)
or HOLD OFF state depending on the Output_Mode input.
Table 3 defines the disabled output functions.
Table 1. Frequency Range Select
CY7B9930V
fNOM (MHz)
CY7B9940V
fNOM (MHz)
FS[1]
LOW
Min.
Max.
26
Min.
Max.
52
12
24
48
24
48
96
MID
52
100
HIGH
100
200[2]
Notes
1. The level to be set on FS is determined by the “nominal” operating frequency (f
) of the V . f
always appears on an output when the output is operating in
NOM
CO NOM
the undivided mode. The REF and FB are at f
2. The maximum output frequency is 200 MHz.
when the output connected to FB is undivided.
NOM
Document Number: 38-07271 Rev. *C
Page 2 of 11
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RoboClockII™ Junior,
CY7B9930V, CY7B9940V
The HOLD OFF state is designed as a power saving feature. An
output bank is disabled to the HOLD OFF state in a maximum of
six output clock cycles from the time when the disable input
(DIS[1:2]) is HIGH. When disabled to the HOLD OFF state,
outputs are driven to a logic LOW state on its falling edge. This
ensures the output clocks are stopped without glitch. When a
bank of outputs is disabled to HI-Z state, the respective bank of
outputs go HI-Z immediately.
If the feedback clock is removed after LOCK has gone HIGH, a
Watchdog circuit is implemented to indicate the out-of-lock
condition after a timeout period by deasserting LOCK LOW. This
timeout period is based upon a divided down reference clock.
This assumes that there is activity on the selected REF input. If
there is no activity on the selected REF input then the LOCK
detect pin may not accurately reflect the state of the internal PLL.
Factory Test Mode Description
Table 3. DIS[1:2] Pin Functionality
The device enters factory test mode when the OUTPUT_MODE
is driven to MID. In factory test mode, the device operates with
its internal PLL disconnected; the input level supplied to the
reference input is used in place of the PLL output. In TEST mode
the selected FB input must be tied LOW. All functions of the
device remain operational in factory test mode except the
internal PLL and output bank disables. The OUTPUT_MODE
input is designed as a static input. Dynamically toggling this input
from LOW to HIGH may temporarily cause the device to go into
factory test mode (when passing through the MID state).
OUTPUT_MODE
HIGH/LOW
HIGH
DIS[1:2]/FBDIS
Output Mode
ENABLED
LOW
HIGH
HIGH
X
HI-Z
LOW
HOLD-OFF
FACTORY TEST
MID
Lock Detect Output Description
The LOCK detect output indicates the lock condition of the
integrated PLL. Lock detection is accomplished by comparing
the phase difference between the reference and feedback
inputs. Phase error is declared when the phase difference
between the two inputs is greater than the specified device
propagation delay limit (tPD).
Factory Test Reset
When in factory test mode (OUTPUT_MODE = MID), the device
is reset to a deterministic state by driving the DIS2 input HIGH.
When the DIS2 input is driven HIGH in factory test mode, all
clock outputs go to HI-Z; after the selected reference clock pin
has five positive transitions, all the internal finite state machines
(FSM) are set to a deterministic state. The deterministic state of
the state machines depends on the configurations of the divide
selects and frequency select input. All clock outputs stay in high
impedance mode and all FSMs stay in the deterministic state
until DIS2 is deasserted. When DIS2 is deasserted (with
OUTPUT_MODE still at MID), the device reenters factory test
mode.
When in the locked state, after four or more consecutive
feedback clock cycles with phase errors, the LOCK output is
forced LOW to indicate out-of-lock state.
When in the out-of-lock state, 32 consecutive phase errorless
feedback clock cycles are required to allow the LOCK output to
indicate lock condition (LOCK = HIGH).
Document Number: 38-07271 Rev. *C
Page 3 of 11
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RoboClockII™ Junior,
CY7B9930V, CY7B9940V
Pin Definitions
44-Pin TQFP
44 43 42 41 40 39 38 37 36 35 34
GND
2QB1
VCCN
2QB0
GND
1
33
32
31
30
29
28
27
26
25
24
23
VCCQ
2
REFA+
REFA –
REFSEL
REFB–
REFB+
FS
3
4
5
CY7B9930V/40V
GND
6
2QA1
VCCN
2QA0
GND
7
8
GND
9
VCCQ
DIS2
10
11
GND
DIS1
12 13
14 15
22
20 21
16 17 18
19
Name
I/O
Input
Type
Description
FBKA
LVTTL
Feedback Input.
REFA+, REFA– Input
REFB+, REFB–
LVTTL/
LVDIFF
Reference Inputs: These inputs operate as either differential PECL or single ended TTL
reference inputs to the PLL. When operating as a single ended LVTTL input, leave the
complementary input must be left open.
REFSEL
Input
LVTTL
Reference Select Input: The REFSEL input controls reference input configuration. When
LOW, it uses the REFA pair as the reference input. When HIGH, it uses the REFB pair as
the reference input. This input has an internal pull down.
FS[3]
Input
Input
Input
3 Level
Input
Frequency Select: Set this input according to the nominal frequency (fNOM). See Table 1.
FBDS[0:1][3]
DIS[1:2]
3 Level
Input
Feedback Divider Function Select. These inputs determine the function of the QFA0 and
QFA1 outputs. See Table 2.
LVTTL
Output Disable: Each input controls the state of the respective output bank. When HIGH,
the output bank is disabled to the “HOLD OFF” or “HI-Z” state; the disable state is deter-
mined by OUTPUT_MODE. When LOW, the [1:4]Q[A:B][0:1] is enabled. See Table 3.
These inputs each have an internal pull down.
LOCK
Output
LVTTL
PLL Lock Indicator: When HIGH, this output indicates that the internal PLL is locked to
the reference signal. When LOW, the PLL is attempting to acquire lock.
Output_Mode[3] Input
3 Level
Input
Output Mode: This pin determines the clock outputs’ disable state. When this input is HIGH,
the clock outputs disable to high impedance (HI-Z). When this input is LOW, the clock
outputs disables to “HOLD OFF” mode. When in MID, the device enters factory test mode.
QFA[0:1]
Output
LVTTL
Clock Feedback Output: This pair of clock outputs connects to the FB input. These outputs
have numerous divide options. The function is determined by the setting of the FBDS[0:1]
pins.
[1:2]Q[A:B][0:1] Output
LVTTL
PWR
PWR
PWR
Clock Output.
VCCN
VCCQ
GND
Output Buffer Power: Power supply for each output pair.
Internal Power: Power supply for the internal circuitry.
Device Ground.
Note
3. For all tri-state inputs, HIGH indicates a connection to V , LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry
CC
holds an unconnected input to V /2.
CC
Document Number: 38-07271 Rev. *C
Page 4 of 11
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RoboClockII™ Junior,
CY7B9930V, CY7B9940V
Static discharge voltage................................................. >2000V
MIL-STD-883, Method 3015)
Absolute Maximum Conditions
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Latch up current......................................................... >±200mA
Operating Range
Storage temperature ...........................................−40°C to +125°C
Ambient Temperature with power applied........−40°C to +125°C
Supply voltage to ground potential ........................−0.5V to +4.6V
DC input voltage............................................... −0.3V to VCC+0.5V
Output current into outputs (LOW) ...................................40 mA
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VCC
3.3V ±10%
3.3V ±10%
–40°C to +85°C
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Max.
Unit
LVTTL Compatible Output Pins (QFA[0:1], [1:4]Q[A:B][0:1], LOCK)
VOH
VOL
IOZ
LVTTL HIGH voltage QFA[0:1], [1:2]Q[A:B][0:1]
VCC = Min., IOH = –30 mA
IOH = –2 mA, VCC = Min.
VCC = Min., IOL= 30 mA
2.4
2.4
–
–
–
V
V
LOCK
LVTTL LOW voltage QFA[0:1], [1:2]Q[A:B][0:1]
LOCK
0.5
0.5
100
V
IOL= 2 mA, VCC = Min.
–
V
High impedance state leakage current
–100
μA
LVTTL Compatible Input Pins (FBKA, REFA±, REFB±, REFSEL, DIS[1:2])
VIH
VIL
LVTTL Input HIGH
LVTTL Input LOW
LVTTL VIN >VCC
FBKA+, REF[A:B]±
REFSEL, DIS[1:2]
FBKA+, REF[A:B]±
REFSEL, DIS[1:2]
FBKA+, REF[A:B]±
FBKA+, REF[A:B]±
REFSEL, DIS[1:2]
FBKA+, REF[A:B]±
REFSEL, DIS[1:2]
Min. < VCC < Max.
2.0
2.0
–0.3
–0.3
–
VCC+0.3
VCC+0.3
0.8
V
V
Min. < VCC < Max.
V
0.8
V
II
VCC = GND, VIN = 3.63V
VCC = Max., VIN = VCC
100
μA
μA
μA
μA
μA
IlH
LVTTL Input HIGH
Current
–
500
V
IN = VCC
–
500
IlL
LVTTL Input LOW
Current
VCC = Max., VIN = GND
–500
–500
–
–
3-Level Input Pins (FBDS[0:1], FS, Output_Mode)
VIHH
VIMM
VILL
IIHH
Three level input HIGH[4]
Three level input MID[4]
Three level input LOW[4]
Min. < VCC < Max.
Min. < VCC < Max.
Min. < VCC < Max.
VIN = VCC
0.87*VCC
–
V
V
0.47*VCC 0.53*VCC
0.13*VCC
V
Three level input
HIGH current
Three level input pins
–
200
50
–
μA
IIMM
IILL
Three level input MID Three level input pins
current
VIN = VCC/2
VIN = GND
–50
–200
μA
μA
Three level input
LOW current
Three level input pins
LVDIFF Input Pins (REF[A:B]±)
VDIFF
VIHHP
VILLP
Input differential voltage
400
1.0
VCC
VCC
mV
V
Highest input HIGH voltage
Lowest input LOW voltage
GND
0.8
VCC – 0.4
VCC
V
VCOM
Common mode range (crossing voltage)
V
Note
4. These inputs are normally wired to V , GND, or left unconnected (actual threshold voltages vary as a percentage of V ). Internal termination resistors hold the
CC
CC
unconnected inputs at V /2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional t
CC
time before
LOCK
all data sheet limits are achieved.
Document Number: 38-07271 Rev. *C
Page 5 of 11
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RoboClockII™ Junior,
CY7B9930V, CY7B9940V
Electrical Characteristics Over the Operating Range (continued)
Parameter
Description
Test Conditions
Min.
Max.
Unit
Operating Current
[5]
ICCI
Internal operating
current
CY7B9930V
CY7B9940V
CY7B9930V
CY7B9940V
VCC = Max., fMAX
–
–
–
–
200
200
40
mA
mA
mA
mA
ICCN
Output current
VCC = Max.,
CLOAD = 25 pF,
LOAD = 50Ω at VCC/2,
fMAX
dissipation/pair[6]
50
R
Capacitance
Parameter
Description
Input capacitance
Test Conditions
Min.
Max.
Unit
CIN
TA = 25°C, f = 1 MHz, VCC = 3.3V
–
5
pF
Switching Characteristics
Over the Operating Range[7, 8, 9, 10, 11]
CY7B9930/40V-2 CY7B9930/40V-5
Parameter
Description
Unit
Min.
12
24
12
24
–
Max.
100
200
100
200
185
200
250
Min.
12
24
12
24
–
Max.
100
200
100
200
185
250
550
fin
Clock input frequency
Clock input frequency
CY7B9930V
MHz
MHz
MHz
MHz
ps
CY7B9940V
CY7B9930V
CY7B9940V
fout
tSKEWPR
tSKEWBNK
tSKEW0
Matched pair skew[12, 13]
Intrabank skew[12, 13]
–
–
ps
Output-Output skew (same frequency and phase, rise to rise, fall
to fall)[12, 13]
–
–
ps
tSKEW1
tCCJ1-3
tCCJ4-12
Output-Output skew (same frequency and phase, other banks at
different frequency, rise to rise, fall to fall)[12, 13]
–
–
–
250
150
100
–
–
650
150
100
ps
Cycle-to-cycle jitter (divide by 1 output frequency,
FB = divide by 1, 2, 3)
ps Peak-
Peak
Cycle-to-cycle jitter (divide by 1 output frequency,
FB = divide by 4, 5, 6, 8, 10, 12)
–
ps Peak-
Peak
tPD
Propagation delay, REF to FB Rise
Propagation delay difference between two devices[14]
REF input (pulse width HIGH)[15]
REF input (pulse width LOW)[15]
Output rise/fall time[16]
–250
–
250
200
–
–500
500
200
–
ps
ps
ns
ns
ns
tPDDELTA
tREFpwh
tREFpwl
2.0
2.0
0.15
2.0
2.0
–
–
tr/tf
2.0
0.15
2.0
Notes
5.
I
measurement is performed with Bank1 and FB Bank configured to run at maximum frequency (f
= 100 MHz for CY7B9930V, f
= 200 MHz for CY7B9940V),
CCI
NOM
NOM
and all other clock output banks to run at half the maximum frequency. FS and OUTPUT_MODE are asserted to the HIGH state.
6. This is dependent upon frequency and number of outputs of a bank being loaded. The value indicates maximum I
at maximum frequency and maximum load of
CCN
25 pF terminated to 50Ω at V /2.
CC
7. This is for non-three level inputs.
8. Assumes 25 pF Max. Load Capacitance up to 185 Mhz. At 200 MHz the max load is 10 pF.
9. Both outputs of pair must be terminated, even if only one is being used.
10. Each package must be properly decoupled.
11. AC parameters are measured at 1.5V, unless otherwise indicated.
12. Test Load C = 25 pF, terminated to V /2 with 50Ω.
L
CC
13. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when all outputs
are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF.
14. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
15. Tested initially and after any design or process changes that may affect these parameters.
16. Rise and fall times are measured between 2.0V and 0.8V.
Document Number: 38-07271 Rev. *C
Page 6 of 11
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RoboClockII™ Junior,
CY7B9930V, CY7B9940V
Switching Characteristics
Over the Operating Range[7, 8, 9, 10, 11] (continued)
CY7B9930/40V-2 CY7B9930/40V-5
Parameter
Description
PLL lock time from power up
Unit
Min.
Max.
10
Min.
Max.
10
tLOCK
–
–
–
–
ms
tRELOCK1
PLL relock time (from same frequency, different phase) with
stable power supply
500
500
μs
tRELOCK2
PLL Relock Time (from different frequency, different phase) with
Stable Power Supply[17]
–
1000
–
1000
μs
tODCV
tPWH
tPWL
tPDEV
tOAZ
Output duty cycle deviation from 50%[11]
Output HIGH time deviation from 50%[18]
Output LOW time deviation from 50%[18]
Period deviation when changing from reference to reference[19]
DIS[1:2] HIGH to output high impedance from ACTIVE[12, 20]
–1.0
–
1.0
1.5
–1.0
–
1.0
1.5
ns
ns
ns
UI
ns
ns
–
2.0
–
2.0
–
0.025
10
–
0.025
10
1.0
0.5
1.0
0.5
tOZA
DIS[1:2] LOW to output ACTIVE from output is high
impedance[20, 21]
14
14
AC Test Loads and Waveform
See note. [22]
3.3V
R1
R2
For LOCK output only
For all other outputs
OUTPUT
R1 = 910Ω
R1 = 100Ω
R2 = 100Ω
C < 25 pF up to 185 MHz
L
C
L
Ω
R2 = 910
C < 30 pF
L
10 pF from 185 to 200 MHz
(Includes fixture and
probe capacitance)
(a) LVTTL AC Test Load
3.3V
GND
2.0V
0.8V
2.0V
0.8V
< 1 ns
< 1 ns
(b)TTL Input Test Waveform
Notes
17. f
18. t
must be within the frequency range defined by the same FS state.
NOM
is measured at 2.0V. t
is measured at 0.8V.
PWH
PWL
19. UI = Unit Interval. Examples: 1 UI is a full period. 0.1 UI is 10% of period.
20. Measured at 0.5V deviation from starting voltage.
21. For t
minimum, C = 0 pF. For t
maximum, C = 25 pF to 18 MHz, 10 pF from 185 to 200 MHz.
OZA
L
OZA L
22. These figures are for illustration only. The actual ATE loads may vary.
Document Number: 38-07271 Rev. *C
Page 7 of 11
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RoboClockII™ Junior,
CY7B9930V, CY7B9940V
AC Timing Diagrams
See note. [11]
t
REFpwl
QFA0 or
t
REFpwh
[1:4]Q[A:B]0
REF
tPD
t
t
SKEWPR
SKEWPR
t
PWH
t
PWL
QFA1 or
2.0V
[1:4]Q[A:B]1
FB
Q
0.8V
t
CCJ1-3,4-12
[1:4]QA[0:1]
t
t
SKEWBNK
SKEWBNK
[1:4]QB[0:1]
REF TO DEVICE 1 and 2
t
ODCV
t
ODCV
t
PD
Q
FB DEVICE1
FB DEVICE2
t
SKEW0,1
t
SKEW0,1
t
PDELTA
t
PDELTA
Other Q
Document Number: 38-07271 Rev. *C
Page 8 of 11
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RoboClockII™ Junior,
CY7B9930V, CY7B9940V
Ordering Information
Propagation
Delay (ps)
Max. Speed
(MHz)
Ordering Code
Package Type
Operating Range
500
500
100
100
200
200
100
200
100
200
CY7B9930V-5AC [23]
CY7B9930V-5AI [23]
CY7B9940V-5AC
CY7B9940V-5AI [23]
CY7B9930V-2AC [23]
CY7B9940V-2AC
44-Lead Thin Quad Flat Pack
44-Lead Thin Quad Flat Pack
44-Lead Thin Quad Flat Pack
44-Lead Thin Quad Flat Pack
44-Lead Thin Quad Flat Pack
44-Lead Thin Quad Flat Pack
44-Lead Thin Quad Flat Pack
44-Lead Thin Quad Flat Pack
Commercial
Industrial
500
Commercial
Industrial
500
250
Commercial
Industrial
250
250
CY7B9930V-2AI [23]
CY7B9940V-2AI [23]
250
Pb-free
500
100
100
200
200
200
200
200
200
200
200
CY7B9930V-5AXC
CY7B9930V-5AXCT
CY7B9940V-5AXC
CY7B9940V-5AXCT
CY7B9940V-5AXI
CY7B9940V-5AXIT
CY7B9940V-2AXC
CY7B9940V-2AXCT
CY7B9940V-2AXI
CY7B9940V-2AXIT
44-Lead Thin Quad Flat Pack
Commercial
Commercial
Commercial
500
44-Lead Thin Quad Flat Pack–Tape and Reel
44-Lead Thin Quad Flat Pack
500
500
44-Lead Thin Quad Flat Pack–Tape and Reel
44-Lead Thin Quad Flat Pack
500
Industrial
500
44-Lead Thin Quad Flat Pack–Tape and Reel
44-Lead Thin Quad Flat Pack
250
Commercial
Industrial
250
44-Lead Thin Quad Flat Pack–Tape and Reel
44-Lead Thin Quad Flat Pack
250
250
44-Lead Thin Quad Flat Pack–Tape and Reel
Note
23. It is a obsolete device.
Document Number: 38-07271 Rev. *C
Page 9 of 11
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RoboClockII™ Junior,
CY7B9930V, CY7B9940V
Package Diagrams
44-Lead Thin Plastic Quad Flat Pack A44
ꢌꢌ ,EAD 4HIN 0LASTIC 1UAD &LATPACK ꢀꢃ 8 ꢀꢃ 8 ꢀꢂꢌMM
ꢀꢁꢂꢃꢃ¼ꢃꢂꢁꢄ 31
ꢀꢃꢂꢃꢃ¼ꢃꢂꢀꢃ 31
',0(16,216ꢀ,1ꢀ0,//,0(7(56
ꢌꢌ
ꢋꢌ
ꢃ² -).ꢂ
ꢀ
ꢋꢋ
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2ꢂꢃꢂꢃꢉ -).ꢂ
ꢃꢂꢁꢃ -!8ꢂ
34!.$ꢅ/&&
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ꢀꢂꢃꢃ 2%&ꢂ
ꢃꢂꢉꢃ
"ꢂ3ꢂ#ꢂ
ꢀꢀ
ꢁꢋ
$%4!),
!
ꢀꢁ
ꢁꢁ
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3%!4).' 0,!.%
ꢀꢂꢆꢃ -!8ꢂ
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3%% $%4!),
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RoboClockII is a trademark of Cypress Semiconductor.
Document Number: 38-07271 Rev. *C
Page 10 of 11
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RoboClockII™ Junior,
CY7B9930V, CY7B9940V
Document History Page
Document Title: RoboClockII™ Junior, CY7B9930V, CY7B9940V High Speed Multifrequency PLL Clock Buffer
Document Number: 38-07271
Orig. of
Change
REV.
ECN NO. Issue Date
Description of Change
**
110536
115109
128463
12/02/01
7/03/02
7/29/03
SZV
Change from Spec number: 38-01141
*A
*B
HWT
RGL
Add 44TQFP package for both CY7B9930/40V – Industrial Operating Range
Added clock input frequency (fin) specifications in the switching characteristics
table.
Added Min. values for the clock output frequency (fout) in the switching charac-
teristics table.
*C
1346903
8/8/07
WWZ/VED/ Update the ordering info to reflect the current status and Pb-free part numbers.
ARI Implemented new template. Updated the package diagram.
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07271 Rev. *C
Revised August 8, 2007
Page 11 of 11
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
trademarks referenced herein are property of the respective corporations.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips.
All products and company names mentioned in this document may be the trademarks of their respective holders.
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