CY7B995_07 [CYPRESS]
2.5/3.3V 200-MHz High-Speed Multi-Phase PLL Clock Buffer; 2.5 / 3.3V 200MHz的高速多相位锁相环时钟缓冲器
| 型号： | CY7B995_07 |
| 厂家： | 
CYPRESS |
| 描述： | 2.5/3.3V 200-MHz High-Speed Multi-Phase PLL Clock Buffer |
| 文件： | 总13页 (文件大小：383K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RoboClock®, CY7B995
2.5/3.3V 200-MHz High-Speed
Multi-Phase PLL Clock Buffer
Features
Description
■ 2.5V or 3.3V operation
The CY7B995 RoboClock® is a low voltage, low power,
eight-output, 200 MHz clock driver. It features output phase
programmability which is necessary to optimize the timing of high
performance computer and communication systems.
■ Split output bank power supplies
■ Output frequency range: 6 MHz to 200 MHz
■ 45 ps typical cycle-cycle jitter
The user can program both the frequency and the phase of the
output banks through nF[0:1] and DS[0:1] pins. The adjustable
phase feature allows the user to skew the outputs to lead or lag
the reference clock. Any one of the outputs can be connected to
feedback to achieve different reference frequency multiplication,
and divide ratios and zero input-output delay.
■ ± 2% max output duty cycle
■ Selectable output drive strength
■ Selectable positive or negative edge synchronization
■ Eight LVTTL outputs driving 50 Ω terminated lines
■ LVCMOS/LVTTL over-voltage tolerant reference input
The device also features split output bank power supplies, which
enable the user to run two banks (1Qn and 2Qn) at a power
supply level, different from that of the other two banks (3Qn and
4Qn). The three-level PE/HD pin also controls the synchroni-
zation of the output signals to either the rising, or the falling edge
of the reference clock and selects the drive strength of the output
buffers. The high drive option (PE/HD = MID) increases the
output current from ± 12 mA to ± 24 mA.
■ Selectable phase-locked loop (PLL) frequency range and lock
indicator
■ Phase adjustments in 625/1250 ps steps up to ± 7.5 ns
■ (1-6, 8, 10, 12) x multiply and (1/2,1/4)x divide ratios
■ Spread-Spectrum compatible
■ Power down mode
■ Selectable reference divider
■ Industrial temperature range: –40°C to +85°C
■ 44-pin TQFP package
Logic Block Diagram
TEST PE/HD FS VDDQ1
3
PD#/DIV
REF
3
3
3
/R
/N
LOCK
PLL
FB
3
3
DS1:0
1Q0
1Q1
3
Phase
Select
1F1:0
3
2Q0
2Q1
3
3
Phase
Select
2F1:0
3F1:0
4F1:0
3Q0
3
3
Phase
Select
and /K
3Q1
VDDQ3
4Q0
3
3
Phase
Select
and /M
4Q1
sOE#
VDDQ4
Cypress Semiconductor Corporation
Document #: 38-07337 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 27, 2007
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RoboClock®, CY7B995
Pinouts
Figure 1. Pin Diagram - 44 Pin TQFP Package Top view
44 43 42 41 40 39 38 37 36 35 34
33 1F0
4F1
sOE#
1
32
31
30
29
DS1
2
DS0
PD#/DIV
PE/HD
VDDQ4
3
LOCK
4
5
VDDQ1
CY7B995
6
28 VDDQ1
VDDQ4
4Q1
7
27
26
25
24
23
1Q0
1Q1
VSS
VSS
VSS
8
4Q0
VSS
VSS
VSS
9
10
11
12 13 14 15 16 17 18 19 20 21 22
Document #: 38-07337 Rev. *D
Page 2 of 13
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RoboClock®, CY7B995
Table 1. Pin Definitions - 44 Pin TQFP Package
Pin
Name
REF
IO[1]
Type
Description
39
17
37
I
I
I
LVTTL/LVCMOS Reference Clock Input.
FB
LVTTL
Feedback Input.
TEST
3-Level
When MID or HIGH, disables PLL[3]. REF goes to all outputs. Set LOW
for normal operation.
2
sOE#
I, PD LVTTL
Synchronous Output Enable. When HIGH, it stops clock outputs
(except 2Q0 and 2Q1) in a LOW state (for PE/HD = H or M) – 2Q0, and
2Q1 may be used as the feedback signal to maintain phase lock. When
TEST is held at MID level and sOE# is HIGH, the nF[1:0] pins act as output
disable controls for individual banks when nF[1:0] = LL. Set sOE# LOW
for normal operation.
4
PE/HD
I, PU 3-Level
Selects Positive or Negative Edge Control, and High or Low output
Drive Strength. When LOW/HIGH, the outputs are synchronized with the
negative/positive edge of the reference clock respectively. When at MID
level, the output drive strength is increased and the outputs synchronize
with the positive edge of the reference clock. See Table 10 on page 5.
34, 33, 36, 35, nF[1:0]
43, 42, 1, 44
I
3-Level
Selects Frequency and Phase of the Outputs. See Table 4, Table 5,
Table 6, Table 8, and Table 9 on page 4.
41
FS
I
3-Level
LVTTL
Selects VCO Operating Frequency Range. See Table 7 on page 4.
26,27,20,21, nQ[1:0]
13,14,7,8
O
Four banks of two outputs. See Table 6 on page 4 for frequency
settings.
32, 31
3
DS[1:0]
I
3-Level
Selects Feedback Divider. See Table 3 on page 4.
PD#/DIV I, PU 3-Level
Power down and Reference Divider Control. When LOW, shuts off
entire chip. When at MID level, enables the reference divider. See Table 2
for settings.
30
LOCK
O
LVTTL
PLL Lock Indication Signal. HIGH indicates lock, LOW indicates the
PLL is not locked, and outputs may not be synchronized to the input.
5,6
V
DDQ4[2] PWR Power
Power supply for Bank 4 Output Buffers. See Table 11 on page 5 for
supply level constraints.
15,16
19,28,29
18,40
V
V
DDQ3 [2] PWR Power
Power supply for Bank 3 Output Buffers. See Table 11 on page 5 for
supply level constraints.
DDQ1[2] PWR Power
Power supply for Bank 1 and Bank 2 Output Buffers. See Table 11 on
page 5 for supply level constraints.
[2]
VDD
PWR Power
PWR Power
Power supply for the Internal Circuitry. See Table 11 on page 5 for
supply level constraints.
9-12, 22-25, 38 VSS
Ground
Table 2. Reference Divider Settings
Device Configuration
PD#/DIV
R–Reference Divider
The outputs of the CY7B995 can be configured to run at
frequencies ranging from 6 MHz to 200 MHz. The feedback input
divider is controlled by the 3-level DS[0:1] pins as indicated in
Table 3 on page 4, and the reference input divider is controlled
by the 3-level PD#/DIV pin as indicated in Table 2.
H
M
L[4]
1
2
N/A
Notes
1. PD indicates an internal pull down and ‘PU’ indicates an internal pull up.
2. A bypass capacitor (0.1μF) must be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins, their high
frequency filtering characteristic is cancelled by the lead inductance of the traces.
3. When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections
remain in effect unless nF[1:0] = LL.
4. When PD#/DIV = LOW, the device enters power down mode.
Document #: 38-07337 Rev. *D
Page 3 of 13
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RoboClock®, CY7B995
Table 3. Feedback Divider Settings
Configuration
Output Frequency
FB Input
Connected to
1Q[0:1] and
[6]
3Q[0:1]
4Q[0:1]
N-Feedback Input Permitted Output Divider
DS[1:0]
2Q[0:1]
Divider
Connected to FB
4Qn
(N / R) x M x (N / R) x (M / (N / R) x FREF
FREF K) x FREF
LL
LM
LH
2
3
1 or 2
1
4
1,2 or 4
1 or 2
1,2 or 4
1 or 2
1 or 2
1
The 3-level FS control pin setting determines the nominal
operating frequency range of the divide-by-one outputs of the
device. The CY7B995 PLL operating frequency range that corre-
sponds to each FS level is given in Table 7.
ML
MM
MH
HL
5
1
6
Table 7. Frequency Range Select
8
FS
L
PLL Frequency Range
24 to 50 MHz
HM
HH
10
12
1
M
H
48 to 100 MHz
96 to 200 MHz
In addition to the reference and feedback dividers, the CY7B995
includes output dividers on Bank3 and Bank4, which are
controlled by 3F[1:0] and 4F[1:0] as indicated in Table 4 and
Table 5, respectively.
Selectable output skew is in discrete increments of time units
(tU).The value of tU is determined by the FS setting and the
maximum nominal frequency. The equation used to determine
the tU value is: tU = 1 / (fNOM x MF)
Table 4. Output Divider Settings – Bank 3
3F[1:0]
LL
K - Bank3 Output Divider
where MF is a multiplication factor which is determined by the FS
setting as indicated in Table 8.
2
4
1
Table 8. MF Calculation
HH
Other[5]
FS
L
MF
32
16
8
fNOM at which tU is 1.0 ns (MHz)
31.25
62.5
125
Table 5. Output Divider Settings – Bank 4
M
H
4F[1:0]
LL
Other[5]
M- Bank4 Output Divider
2
1
Table 9. Output Skew Settings
The divider settings and the FB input to any output connection
needed to produce various output frequencies are summarized
in Table 6.
Skew
nF[1:0]
Skew
Skew
(1Q[0:1],2Q[0:1])
(3Q[0:1])
(4Q[0:1])
LL[7]
LM
LH
–4tU
–3tU
Divide By 2
–6tU
Divide By 2
–6tU
Table 6. Output Frequency Settings.
Configuration
Output Frequency
–2tU
–4tU
–4tU
FB Input
1Q[0:1] and
[6]
3Q[0:1]
4Q[0:1]
ML
MM
MH
HL
–1tU
–2tU
–2tU
Connected to
2Q[0:1]
Zero Skew
+1tU
Zero Skew
+2tU
Zero Skew
+2tU
1Qn or 2Qn
3Qn
(N / R) x FREF (N / R) x (1 / (N / R) x (1 /
K) x FREF M) x FREF
+2tU
+4tU
+4tU
(N / R) x K x (N / R) x FREF (N / R) x (K /
FREF M) x FREF
HM
HH
+3tU
+6tU
+6tU
Inverted[8]
+4tU
Divide By 4
Notes
5. These states are used to program the phase of the respective banks. See Table 8 and Table 9.
6. These outputs are undivided copies of the VCO clock. The formulas in this column can be used to calculate the VCO operating frequency (FNOM) at a given
reference frequency (FREF), and divider and feedback configuration. The user must select a configuration and a reference frequency that generates a VCO
frequency, and is within the range specified by FS pin. See Table 7.
Document #: 38-07337 Rev. *D
Page 4 of 13
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RoboClock®, CY7B995
In addition to determining whether the outputs synchronize to the
rising or the falling edge of the reference signal, the 3-level
PE/HD pin controls the output buffer drive strength as indicated
in Table 10 on page 5. Refer to the AC Timing Definitions section
for a description of input-to-output and output-to-output phase
relationships.
Table 11. Power Supply Constraints
VDD
3.3V
2.5V
VDDQ1[10]
3.3V or 2.5V 3.3V or 2.5V 3.3V or 2.5V
2.5V 2.5V 2.5V
VDDQ3[10]
VDDQ4[10]
Table 10. PE/HD Settings
Governing Agencies
PE/HD
Synchronization
Negative
Output Drive Strength[9]
Low Drive
The following agencies provide specifications that apply to the
CY7B995. The agency name and relevant specification is listed
below.
L
M
H
Positive
High Drive
Positive
Low Drive
Table 12. Governing Agencies and Specifications
Agency Name
Specification
JESD 51 (Theta JA)
JESD 65 (Skew, Jitter)
1596.3 (Jiter Specs)
94 (Moisture Grading)
The CY7B995 features split power supply buses for Banks 1 and
2, Bank 3 and Bank 4, which enables the user to obtain both 3.3V
and 2.5V output signals from one device. The core power supply
(VDD) must be set at a level that is equal to or higher than any of
the output power supplies.
JEDEC
IEEE
UL-194_V0
MIL
883E Method 1012.1
(Therma Theta JC)
Absolute Maximum Conditions
Parameter
VDD
Description
Operating Voltage
Condition
Functional @ 2.5V ± 5%
Functional @ 3.3V ± 10%
Relative to VSS
Min
2.25
Max
2.75
3.63
–
Unit
V
V
VDD
Operating Voltage
Input Voltage
2.97
VIN(MIN)
VIN(MAX)
VSS – 0.3
–
V
Input Voltage
Relative to VDD
VDD + 0.3
5.5
V
VREF(MAX) Reference Input Voltage
VREF(MAX) Reference Input Voltage
VDD = 3.3V
V
VDD = 2.5V
4.6
V
TS
Temperature, Storage
Non Functional
–65
–40
–
+150
+85
155
42
°C
°C
°C
°C/W
°C/W
V
TA
Temperature, Operating Ambient
Temperature, Junction
Functional
TJ
Functional
ØJC
ØJA
ESDHBM
UL-94
MSL
FIT
Dissipation, Junction to Case
Dissipation, Junction to Ambient
Mil-Spec 883E Method 1012.1
JEDEC (JESD 51)
–
–
74
ESD Protection (Human Body Model) MIL-STD-883, Method 3015
2000
–
Flammability Rating
Moisture Sensitivity Level
Failure in Time
@1/8 in.
V–0
1
Manufacturing Testing
10
ppm
Notes
7. LL disables outputs if TEST = MID and sOE# = HIGH.
8. When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE/HD = HIGH or MID, sOE# disables them LOW when PE/HD = LOW.
9. Please refer to “DC Parameters” section for I /I specifications.
OH OL
10. V Q1/3/4 must not be set at a level higher than that of V . They can be set at different levels from each other, e.g., V = 3.3V, V Q1 = 3.3V, V Q3 = 2.5V
DD
DD
DD
DD
DD
and V Q4 = 2.5V.
DD
Document #: 38-07337 Rev. *D
Page 5 of 13
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RoboClock®, CY7B995
.
DC Specifications at 2.5V
Parameter
Description
2.5 Operating Voltage
Input LOW Voltage
Input HIGH Voltage
Input HIGH Voltage
Condition
Min
Max
Unit
V
VDD
VIL
2.5V ± 5%
2.375 2.625
REF, FB, and sOE# Inputs
–
1.7
0.7
–
V
VIH
V
[11]
VIHH
3-Level Inputs, (TEST, FS, nF[1:0], DS[1:0], PD#/DIV,
PE/HD). (These pins are normally wired to VDD, GND, or
unconnected)
VDD
–
–
V
–0.4
[11]
VIMM
Input MID Voltage
VDD/2 VDD/2
V
– 0.2
–
+ 0.2
0.4
5
[11]
VILL
Input LOW Voltage
V
IIL
I3
Input Leakage Current
VIN = VDD/GND,VDD = Max; (REF and FB Inputs)
–5
–
μA
μA
μA
μA
3-Level Input DC Current HIGH, VIN = VDD
MID, VIN = VDD/2
3-Level Inputs
(TEST, FS, nF[1:0],
DS[1:0], PD#/DIV,
PE/HD)
200
50
–
–50
–200
–25
–
LOW, VIN = VSS
IPU
IPD
VOL
Input Pull-Up Current
VIN = VSS, VDD = Max
–
μA
μA
V
Input Pull-Down Current VIN = VDD, VDD = Max, (sOE#)
100
0.4
0.4
0.4
–
Output LOW Voltage
Output HIGH Voltage
IOL = 12 mA (PE/HD = L/H), (nQ[0:1])
–
I
OL = 20 mA (PE/HD = MID),(nQ[0:1])
OL = 2 mA (LOCK)
–
V
I
V
VOH
IOH = –12 mA (PE/HD = L/H),(nQ[0:1])
2.0
2.0
2.0
–
V
I
OH = –20 mA (PE/HD = MID),(nQ[0:1])
OH = –2 mA (LOCK)
–
V
I
V
IDDQ
Quiescent Supply Current VDD = Max, TEST = MID, REF = LOW, sOE# = LOW,
Outputs Not Loaded
2
mA
IDDPD
Power down Current
PD#/DIV, sOE# = LOW
Test,nF[1:0],DS[1:0] = HIGH; VDD = Max
10(typ.)
25
μA
IDD
CIN
Dynamic Supply Current At 100 MHz
Input Pin Capacitance
150
mA
pF
4
Document #: 38-07337 Rev. *D
Page 6 of 13
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RoboClock®, CY7B995
DC Specifications at 3.3V
Parameter
Description
3.3 Operating Voltage
Input LOW Voltage
Input HIGH Voltage
Input HIGH Voltage
Condition
Min
2.97
–
Max
3.63
0.8
–
Unit
V
VDD
VIL
3.3V ± 10%
REF, FB and sOE# Inputs
V
VIH
2.0
V
[11]
VIHH
3-Level Inputs
VDD
–
–
V
(TEST, FS, nF[1:0], DS[1:0],PD#/DIV, PE/HD); (These pins –0.6
are normally wired to VDD,GND or unconected
[11]
VIMM
Input MID Voltage
VDD/2– VDD/2+
V
0.3
0.3
0.6
5
[11]
VILL
Input LOW Voltage
–
V
IIL
Input Leakage Current
VIN = VDD/GND,VDD = Max
(REF and FB inputs)
–5
μA
I3
3-Level Input DC Current HIGH, VIN = VDD
MID, VIN = VDD/2
3-Level Inputs,
(TEST, FS, nF[1:0],
DS[1:0], PD#/DIV,
PE/HD)
–
200
50
–
μA
μA
μA
–50
–200
LOW, VIN = VSS
IPU
IPD
VOL
Input Pull Up Current
VIN = VSS, VDD = Max
–25
–
–
100
0.4
0.4
0.4
–
μA
μA
V
Input Pull Down Current VIN = VDD, VDD = Max, (sOE#)
Output LOW Voltage
Output HIGH Voltage
IOL = 12 mA (PE/HD = L/H), (nQ[0:1])
IOL = 24 mA (PE/HD = MID),(nQ[0:1])
–
–
V
I
OL = 2 mA (LOCK)
V
VOH
IOH = –12 mA (PE/HD = L/H),(nQ[0:1])
IOH = –24 mA (PE/HD = MID),(nQ[0:1])
2.4
2.4
2.4
–
V
–
V
I
OH = –2 mA (LOCK)
V
IDDQ
Quiescent Supply Current VDD = Max, TEST = MID,
REF = LOW, sOE# = LOW,
2
mA
Outputs Not Loaded
IDDPD
Power Down Current
PD#/DIV, sOE# = LOW, Test,nF[1:0],DS[1:0] = HIGH,
DD = Max
10(typ.)
25
μA
V
IDD
CIN
Dynamic Supply Current At 100 MHz
Input Pin Capacitance
230
mA
pF
4
AC Input Specifications
Parameter
TR,TF
Description
Input Rise/Fall Time
Input Clock Pulse
Input Duty Cycle
Condition
Min
–
Max
10
Unit
ns/V
ns
0.8V – 2.0V
TPWC
HIGH or LOW
2
–
TDCIN
10
2
90
%
FREF
Reference Input
Frequency[12]
FS = LOW
FS = MID
FS = HIGH
50
MHz
4
100
200
8
Document #: 38-07337 Rev. *D
Page 7 of 13
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RoboClock®, CY7B995
Switching Characteristics
Parameter
FOR
Description
Output frequency range
VCO Lock Range
Condition
Min
6
Type
Max
200
400
3.5
Unit
MHz
MHz
MHz
ps
–
–
–
–
VCOLR
200
0.25
–
VCOLBW
tSKEWPR
VCO Loop Bandwidth
Matched-Pair Skew[13]
Skew between the earliest and the latest output
transitions within the same bank.
100
tSKEW0
tSKEW1
Output-Output Skew[13]
Skew between the earliest and the latest output
transitions among all outputs at 0tU.
–
–
–
–
200
200
ps
ps
Skew between the earliest and the latest output
transitions among all outputs for which the same
phase delay has been selected.
tSKEW2
tSKEW3
tSKEW4
tSKEW5
tPART
Skew between the nominal output rising edge to the
inverted output falling edge.
–
–
–
–
–
–
–
–
–
–
500
500
500
650
750
ps
ps
ps
ps
ps
Skew between non-inverted outputs running at
different frequencies.
Output-Output Skew[13]
Part-Part Skew
Skew between nominal to inverted outputs running at
different frequencies.
Skew between nominal outputs at different power
supply levels.
Skew between the outputs of any two devices under
identical settings and conditions (VDDQ, VDD, temp,
air flow, frequency, etc.).
tPD0
Ref to FB Propagation
Delay[14]
–250
–
+250
ps
%
tODCV
Output Duty Cycle
Fout < 100 MHz, Measured at VDD/2.
Fout > 100 MHz, Measured at VDD/2.
48
45
–
–
–
–
52
55
tPWH
tPWL
tR/tF
Output High Time
Deviation from 50%
Measured at 2.0V for VDD = 3.3V and at 1.7V for VDD
= 2.5V.
1.5
ns
ns
ns
Output Low Time
Deviation from 50%
Measured at 0.8V for VDD = 3.3V and at 0.7V for VDD
= 2.5V.
–
–
–
2.0
1.5
Output Rise/Fall Time
Measured at 0.8V–2.0V for VDD = 3.3V and
0.7V–1.7V for VDD = 2.5V.
0.15
tLOCK
tCCJ
PLL Lock Time[15,16]
Cycle-Cycle Jitter
–
–
–
0.5
ms
ps
Divide by one output frequency, FS = L, FB = divide
by any.
45
100
Divide by one output frequency, FS = M/H, FB = divide
by any.
–
55
150
ps
Notes
11. These Inputs are normally wired to VDD, GND or unconnected. Internal termination resistors bias unconnected inputs to V /2.
DD
12. IF PD#/DIV is in HIGH level (R-reference divider = 1). Reference Input Frequency = F
IF PD#/DIV is in MID level (R-reference divider = 2). Reference Input
REF.
Frequency = F
x2.
REF
13. Test Load = 20 pF, terminated to V /2. All outputs are equally loaded.
CC
14. t is measured at 1.5V for V = 3.3V and at 1.25V for V = 2.5V with REF rise/fall times of 0.5 ns between 0.8V–2.0V.
PD
DD
DD
15. t
is the time that is required before outputs synchronize to REF. This specification is valid with stable power supplies which are within normal operating limits.
LOCK
16. Lock detector circuit may be unreliable for input frequencies lower than 4 MHz, or for input signals which contain significant jitter.
Document #: 38-07337 Rev. *D
Page 8 of 13
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RoboClock®, CY7B995
AC Timing Definitions
Figure 2. Timing Definition
tREF
tPWL
tPWH
REF
tPD
t0DCV
t0DCV
FB
tCCJ1-12
Q
tSKEWPR
tSKEWPR
tSKEW0,1
tSKEW0,1
OTHER Q
tSKEW1
tSKEW1
INVERTED Q
tSKEW3
tSKEW3
tSKEW3
DIVIDE BY 2 OUTPUT
DIVIDE BY 4 OUTPUT
tSKEW1,3,4
tSKEW1,3,4
With PE HIGH (LOW), the REF rising (falling) edges are aligned
to the FB rising (falling) edges. Also, when PE is HIGH (LOW),
all divided outputs’ rising (falling) edges are aligned to the rising
(falling) edges of the undivided, non-inverted outputs.
Regardless of PE setting, divide-by-4 outputs’, rising edges align
to the divide-by-2 outputs’ rising edges.
In cases where a non-divided output is connected to the FB input
pin, the divided output rising edges can be either 0 or 180
degrees phase aligned to the REF input rising edges (as set
randomly at power-up). If the divided outputs are required as
rising-edge (falling-edge) aligned to the REF input’s rising
(falling) edge, set the PE pin HIGH (LOW) and connect the
lowest frequency divided output to the FB input pin. This setup
provides a consistent input-output and output-output phase
relationship.
Document #: 38-07337 Rev. *D
Page 9 of 13
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RoboClock®, CY7B995
AC Test Loads and Waveforms
Figure 3. For Lock Output and all other Outputs
VDDQ
Output
150Ω
20pF
Output
20pF
150Ω
For Lock Output
For All Other Outputs
Figure 4. 3.3V LVTTL and 2.5V LVTTL Output Waveforms
tORISE
tOFALL
tORISE
tOFALL
tPWH
tPWH
1.7V
2.0V
VTH =1.25V
VTH =1.5V
tPWL
tPWL
0.7V
0.8V
2.5V LVTTL OUTPUT WAVEFORM
3.3V LVTTL OUTPUT WAVEFORM
Figure 5. 3.3V LVTTL and 2.5V LVTTL Input Test Waveforms
≤ 1ns
≤ 1ns
≤ 1ns
≤ 1ns
2.5V
3.0V
1.7V
2.0V
VTH =1.25V
VTH =1.5V
0.7V
0V
0.8V
0V
2.5V LVTTL INPUT TEST WAVEFORM
3.3V LVTTL INPUT TEST WAVEFORM
Document #: 38-07337 Rev. *D
Page 10 of 13
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RoboClock®, CY7B995
Ordering Information
Part Number
CY7B995AC
CY7B995ACT
CY7B995AI
Package Type
44 TQFP
Product Flow
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Industrial, –40° to 85°C
Industrial, –40° to 85°C
Status
Obsolete
44 TQFP – Tape and Reel
44 TQFP
Obsolete
Not for new design
Obsolete
CY7B995AIT
Pb-free
44 TQFP – Tape and Reel
CY7B995AXC
CY7B995AXCT
CY7B995AXI
CY7B995AXIT
44 TQFP
Commercial, 0° to 70°C
Commercial, 0° to 70°C
Industrial, –40° to 85°C
Industrial, –40° to 85°C
Active
Active
Active
Active
44 TQFP – Tape and Reel
44 TQFP
44 TQFP – Tape and Reel
Document #: 38-07337 Rev. *D
Page 11 of 13
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RoboClock®, CY7B995
Package Drawing and Dimension
Figure 6. 44-Pb Thin Plastic Quad Flat Pack (10 x 10 x 1.0 mm) A44SB
51-85155*A
Document #: 38-07337 Rev. *D
Page 12 of 13
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RoboClock®, CY7B995
Document History Page
Document Title: CY7B995 Roboclock® 2.5/3.3V 200-MHz High-speed Multi-phase PLL Clock Buffer
Document Number: 38-07337
Orig. of
Change
REV.
ECN No. Issue Date
Description of Change
**
122626
205743
01/10/03
See ECN
RGL
New Data Sheet
*A
RGL
Changed Pin 5 from VDD to VDDQ4, Pin 16 from VDD to VDDQ3 and Pin
29 from VDD to VDDQ1
Added pin 1 indicator in the Pin Configuration Drawing
*B
362760
See ECN
RGL
RGL
Added description on the AC Timing Waveforms
Added typical value for cycle-to-cycle jitter
*C
*D
389237
See ECN
See ECN
Added Lead-free devices
1562063
PYG/AESA Added Status column to Ordering Information table
© Cypress Semiconductor Corporation, 2003-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07337 Rev. *D
Revised September 27, 2007
Page 13 of 13
RoboClock is a registered trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
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相关型号：
CY7B9973V-AXCT
PLL Based Clock Driver, 7B Series, 12 True Output(s), 0 Inverted Output(s), PQFP52, TQFP-52
CYPRESS
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