CY7C006-25JC [CYPRESS]
16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy; 16K X 8/9双口静态RAM与扫描电镜，诠释，忙
| 型号： | CY7C006-25JC |
| 厂家： | 
CYPRESS |
| 描述： | 16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy |
| 文件： | 总16页 (文件大小：322K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
with Sem, In t, Busy
CY7C006
CY7C016
16K x 8/9 Dual-Port Static RAM
with Sem, Int, Busy
schemes are included on the CY7C006/016 to handle situa-
tions when multiple processors access the same piece of data.
Two ports are provided, permitting independent, asynchro-
nous access for reads and writes to any location in memory.
Features
• True dual-ported memory cells which allow
simultaneous reads of the same memory location
The CY7C006/016 can be utilized as
a standalone
• 16K x 8 organization (CY7C006)
• 16K x 9 organization (CY7C016)
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
128-/144-Kbit dual-port static RAM or multiple devices can be
combined in order to function as a 16-/18-bit or wider mas-
ter/slave dual-port static RAM. An M/S pin is provided for im-
plementing 16-/18-bit or wider memory applications without
the need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor/multi-
processor designs, communications status buffering, and du-
al-port video/graphics memory.
• Low operating power: I = 140 mA (typ.)
CC
• Fully asynchronous operation
• Automatic power-down
• TTL compatible
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags, BUSY and INT, are provided on each port. BUSY signals
that the port is trying to access the same location currently
being accessed by the other port. The Interrupt flag (INT) per-
mits communication between ports or systems by means of a
mail box. The semaphores are used to pass a flag, or token,
from one port to the other to indicate that a shared resource is
in use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared re-
source is in use. An automatic power-down feature is con-
trolled independently on each port by a Chip Enable (CE) pin
or SEM pin.
• Expandable data bus to 16/18 bits or more using
Master/Slave chip select when using more than one
device
• Busy arbitration scheme provided
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Available in 68-pin PLCC (7C006), 64-pin (7C006) and
80-pin (7C016) TQFP
• Pin compatible and functional equivalent to
IDT7006/IDT7016
Functional Description
The CY7C006 and CY7C016 are available in 68-pin PLCC
(CY7C006), 64-pin (CY7C006) TQFP, and 80-pin (CY7C016) TQFP.
The CY7C006 and CY7C016 are high-speed CMOS 16K x 8
and 16K x 9 dual-port static RAMs. Various arbitration
R/W
L
R/W
R
Logic Block Diagram
CE
OE
CE
OE
L
R
R
L
(7C016)I/O
I/O
I/O (7C016)
8R
8L
7L
I/O
7R
I/O
CONTROL
I/O
CONTROL
I/O
0L
I/O
0R
[1,2]
BUSY
R
[1,2]
L
BUSY
A
13L
A
A
13R
0R
ADDRESS
DECODER
ADDRESS
DECODER
MEMORY
ARRAY
A
0L
INTERRUPT
SEMAPHORE
ARBITRATION
CE
OE
L
L
L
CE
R
OE
R
R/W
R/W
R
SEM
SEM
R
L
[2]
C006-1
[2]
INT
R
INT
L
M/S
Notes:
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
December 22, 1999
CY7C006
CY7C016
Pin Configurations
68-Pin PLCC
Top View
60
59
A
10
11
12
13
I/O
5L
2L
I/O
I/O
A
4L
3L
58
57
A
3L
4L
I/O
A
5L
2L
56
55
A
1L
GND
14
15
A
0L
I/O
6L
54
INT
I/O
7L
L
16
17
53 BUSY
V
CC
L
CY7C006
GND
M/S
52
GND
18
19
20
21
I/O
0R
51
50
I/O
BUSY
1R
R
I/O
V
INT
R
49
48
2R
A
0R
CC
22
23
A
1R
I/O
3R
47
46
45
44
I/O
I/O
24
25
26
4R
A
2R
A
5R
3R
4R
I/O6
A
R
C006-2
64-Pin TQFP
Top View
I/O
A
4L
2L
1
48
47
46
45
44
A
A
I/O
I/O
2
3
4
5
3L
4L
3L
2L
A
1L
A
0L
I/O
5L
GND
I/O
6L
43
42
41
INT
L
6
7
8
I/O
7L
BUSY
L
GND
M/S
CY7C006
V
CC
GND
40
39
9
BUSY
I/O
0R
10
R
I/O
1R
38
37
36
INT
R
11
12
13
I/O
2R
A
0R
A
1R
A
2R
A
3R
V
CC
I/O
3R
35
34
14
15
16
I/O
4R
I/O
5R
33
A
4R
C006-3
Note:
3. I/O for CY7C016 only.
2
CY7C006
CY7C016
Pin Configurations (continued)
80-Pin TQFP
Top View
NC
1
2
NC
60
59
I/O
I/O
I/O
I/O
2L
A
5L
A
4L
3
4
3L
4L
5L
58
57
A
A
3L
2L
5
6
7
8
56
55
54
53
A
1L
A
0L
GND
I/O
6L
I/O
7L
INT
L
BUSY
V
L
9
10
CC
52
51
GND
M/S
CY7C016
NC
GND
I/O
11
12
13
14
50
49
48
47
0R
BUSY
R
I/O
1R
INT
R
I/O
2R
CC
3R
4R
5R
6R
A
0R
A
1R
A
2R
A
3R
V
15
16
46
45
I/O
I/O
I/O
I/O
17
44
A
4R
18
19
20
43
42
41
NC
NC
NC
C006-4
Pin Definitions
Left Port
Right Port
Description
I/O
I/O
Data Bus Input/Output
Address Lines
0L–7L(8L)
0L–13L
0R–7R(8R)
A
0R–13R
A
CE
CE
Chip Enable
L
R
OE
OE
Output Enable
L
R
R/W
R/W
Read/Write Enable
L
R
SEM
SEM
Semaphore Enable. When asserted LOW, allows access to eight sema-
phores. The three least significant bits of the address lines will determine
L
R
which semaphore to write or read. The I/O pin is used when writing to a
0
semaphore. Semaphores are requested by writing a 0 into the respective
location.
INT
INT
Interrupt Flag. INT is set when right port writes location 3FFE and is
L
L
R
cleared when left port reads location 3FFE. INT is set when left port writes
R
location 3FFF and is cleared when right port reads location 3FFF.
BUSY
M/S
BUSY
Busy Flag
L
R
Master or Slave Select
Power
V
CC
GND
Ground
3
CY7C006
CY7C016
Selection Guide
7C006-15
7C016-15
7C006-25
7C016-25
7C006-35
7C016-35
7C006-55
7C016-55
Maximum Access Time (ns)
15
25
35
55
Maximum Operating
Current (mA)
260
220
210
200
Maximum Standby
70
60
50
40
Current for I
(mA)
SB1
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Ambient
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
V
CC
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
5V ± 10%
5V ± 10%
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
[4]
DC Input Voltage ......................................... –0.5V to +7.0V
Electrical Characteristics Over the Operating Range
7C006-15
7C016-15
7C006-25
7C016-25
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Test Conditions
= Min., I = –4.0 mA
Min. Typ. Max. Min. Typ. Max. Unit
V
V
V
2.4
2.4
V
V
OH
CC
CC
OH
V
= Min., I = 4.0 mA
0.4
0.8
0.4
OL
OL
V
V
2.2
2.2
V
IH
IL
Input LOW Voltage
0.8
+10
+10
V
I
I
I
Input Leakage Current
GND ≤ V ≤ V
CC
–10
–10
+10 –10
+10 –10
260
µA
µA
IX
I
Output Leakage Current Outputs Disabled, GND ≤ V ≤ V
CC
OZ
CC
O
Operating Current
V
= Max., I
= 0 mA
Com’l
Ind
170
50
160
160
40
40
90
90
3
220 mA
270
CC
OUT
Outputs Disabled
I
I
I
Standby Current
(Both Ports TTL Levels) f = f
CE and CE ≥ V ,
Com’l
Ind
70
170
15
60
75
mA
SB1
SB2
SB3
L
R
IH
[5]
MAX
Standby Current
(One Port TTL Level)
CE or CE ≥ V ,
Com’l
Ind
110
3
130 mA
150
L
R
IH
[5]
f = f
MAX
Standby Current
(Both Ports CMOS
Levels)
Both Ports
CE and CE ≥ V – 0.2V,
Com’l
Ind
15
15
mA
R
CC
3
V
≥ V – 0.2V
IN
CC
[5]
or V ≤ 0.2V, f = 0
IN
I
Standby Current
(One Port CMOS Level) CE or CE ≥ V – 0.2V,
One Port
Com’l
100
150
80
80
120 mA
130
SB4
L
R
CC
Ind
V
≥ V – 0.2V or
IN
CC
V
≥ 0.2V, Active
IN
[5]
MAX
Port Outputs, f = f
Notes:
4. Pulse width < 20 ns.
5.
fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3.
4
CY7C006
CY7C016
Electrical Characteristics (continued)
7C006-35
7C016-35
7C006-55
7C016-55
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Test Conditions
= Min., I = –4.0 mA
Min. Typ. Max. Min. Typ. Max. Unit
V
V
V
2.4
2.4
V
V
OH
CC
CC
OH
V
= Min., I = 4.0 mA
0.4
0.4
OL
OL
V
V
2.2
2.2
V
IH
IL
Input LOW Voltage
0.8
0.8
+10
+10
V
I
I
I
Input Leakage Current
GND ≤ V ≤ V
CC
–10
–10
+10 –10
µA
µA
IX
I
Output Leakage Current Outputs Disabled, GND ≤ V ≤ V
CC
+10 –10
210
250
50
OZ
CC
O
Operating Current
V
= Max., I
= 0 mA
Com’l
Ind
150
150
30
30
80
80
3
140
140
20
20
70
70
3
200 mA
240
CC
OUT
Outputs Disabled
I
I
I
Standby Current
(Both Ports TTL Levels) f = f
CE and CE ≥ V ,
Com’l
Ind
40
55
mA
SB1
SB2
SB3
L
R
IH
[5]
MAX
65
Standby Current
(One Port TTL Level)
CE or CE ≥ V ,
Com’l
Ind
120
130
15
100 mA
115
L
R
IH
[5]
f = f
MAX
Standby Current
(Both Ports CMOS
Levels)
Both Ports
CE and CE ≥ V – 0.2V,
Com’l
Ind
15
15
mA
R
CC
3
15
3
V
≥ V – 0.2V
IN
CC
[5]
or V ≤ 0.2V, f = 0
IN
I
Standby Current
(One Port CMOS Level) CE or CE ≥ V – 0.2V,
One Port
Com’l
70
70
100
110
60
60
90
95
mA
SB4
L
R
CC
Ind
V
≥ V – 0.2V or
IN
CC
V
≤ 0.2V, Active
IN
[5]
MAX
Port Outputs, f = f
Capacitance[6]
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Max.
10
Unit
pF
C
C
Input Capacitance
Output Capacitance
IN
A
V
= 5.0V
CC
10
pF
OUT
AC Test Loads and Waveforms
5V
5V
R1=893
R2=347
Ω
Ω
R1=893
R2=347
Ω
R
TH
=250
Ω
OUTPUT
C = 5 pF
OUTPUT
C=30 pF
OUTPUT
C = 30 pF
Ω
V
TH
=1.4V
(b) ThéveninEquivalent (Load)
(c) Three-State Delay (Load 3)
(a) Normal Load (Load 1)
C006-6
C006-7
C006-5
ALL INPUT PULSES
OUTPUT
3.0V
GND
90%
90%
10%
3 ns
10%
C = 30 pF
≤
3 ns
≤
Load (Load 2)
C006-8
C006-9
Note:
6. Tested initially and after any design or process changes that may affect these parameters.
5
CY7C006
CY7C016
[7]
Switching Characteristics Over the Operating Range
7C006-15
7C016-15
7C006-25
7C016-25
7C006-35
7C016-35
7C006-55
7C016-55
Parameter
Description
Min.
Max. Min. Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
3
25
35
3
55
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
15
25
35
55
AA
3
OHA
ACE
DOE
LZOE
15
10
25
13
35
20
55
25
[8, 9, 10]
[8, 9, 10]
3
3
0
3
3
0
3
3
0
3
3
0
OE HIGH to High Z
10
10
15
15
15
25
15
15
35
25
25
55
HZOE
[8, 9, 10]
CE LOW to Low Z
LZCE
[8, 9, 10]
CE HIGH to High Z
HZCE
[10]
[10]
CE LOW to Power-Up
CE HIGH to Power-Down
PU
PD
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
15
12
12
0
25
20
20
0
35
30
30
0
55
45
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
SCE
AW
HA
CE LOW to Write End
Address Set-Up to Write End
Address Hold From Write End
Address Set-Up to Write Start
Write Pulse Width
0
0
0
0
SA
12
10
0
20
15
0
25
15
0
40
25
0
PWE
SD
Data Set-Up to Write End
Data Hold From Write End
R/W LOW to High Z
[11]
HD
[9, 10]
10
15
20
25
HZWE
[9, 10]
R/W HIGH to Low Z
3
3
3
3
LZWE
[12]
WDD
Write Pulse to Data Delay
30
25
50
30
60
35
80
60
[12]
Write Data Valid to Read Data Valid
DDD
[13]
BUSY TIMING
t
t
t
t
t
t
t
t
BUSY LOW from Address Match
15
15
15
15
20
20
20
17
20
20
20
25
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
BLA
BHA
BLC
BHC
PS
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set-Up for Priority
5
0
5
0
5
0
5
0
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to Data Valid
WB
13
17
25
30
WH
BDD
[14]
Note 13
Note 13
Note 13
Note 13
Notes:
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
OI/IOH and 30-pF load capacitance.
I
8. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE
.
9. Test conditions used are Load 3.
10. This parameter is guaranteed but not tested.
11. Must be met by the device writing to the RAM under all operating conditions.
12. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
13. Test conditions used are Load 2.
14. tBDD is a calculated parameter and is the greater of tWDD – tPWE (actual) or tDDD – tSD (actual).
6
CY7C006
CY7C016
[7]
Switching Characteristics Over the Operating Range (continued)
7C006-15
7C016-15
7C006-25
7C016-25
7C006-35
7C016-35
7C006-55
7C016-55
Parameter
Description
Min.
Max. Min. Max.
Min.
Max.
Min.
Max.
Unit
[13]
INTERRUPT TIMING
t
t
INT Set Time
15
15
25
25
25
25
30
30
ns
ns
INS
INT Reset Time
INR
SEMAPHORE TIMING
t
t
t
SEM Flag Update Pulse (OEor SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
10
5
10
5
15
5
20
5
ns
ns
ns
SOP
SWRD
SPS
5
5
5
5
Switching Waveforms
[15, 16]
Read Cycle No. 1 (Either Port Address Access)
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
C006-10
[15, 17, 18]
Read Cycle No. 2 (Either Port CE/OE Access)
SEM or CE
t
HZCE
t
ACE
OE
t
HZOE
t
DOE
t
LZOE
t
LZCE
DATA VALID
DATA OUT
t
PU
t
PD
I
CC
I
SB
C006-11
Notes:
15. R/W is HIGH for read cycle.
16. Device is continuously selected CE = LOW and OE = LOW. This waveform cannot be used for semaphore reads.
17. Address valid prior to or coincident with CE transition LOW.
18. CEL = L, SEM = H when accessing RAM. CE = H, SEM = L when accessing semaphores.
7
CY7C006
CY7C016
Switching Waveforms (continued)
[19, 20]
Read Timing with Port-to-Port Delay (M/S=L)
t
WC
ADDRESS
R/W
R
MATCH
t
PWE
R
t
t
SD
HD
DATA IN
VALID
R
ADDRESS
L
MATCH
t
DDD
DATA
OUTL
VALID
t
WDD
C006-12
[21, 22, 23]
Write Cycle No. 1: OE Three-State Data I/Os (Either Port)
t
WC
ADDRESS
t
SCE
SEM OR CE
R/W
t
t
HA
AW
t
PWE
t
SA
t
t
HD
SD
DATA IN
OE
DATA VALID
t
t
HZOE
LZOE
HIGH IMPEDANCE
DATA OUT
C006-13
Notes:
19. BUSY = HIGH for the writing port.
20. CEL = CER = LOW.
21. The internal write time of the memory is defined by the overlap of CEor SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
22. If OEis LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on
the bus for the required tSD. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as short as the
specified tPWE
.
23. R/W must be HIGH during all address transitions.
8
CY7C006
CY7C016
Switching Waveforms (continued)
[20, 22, 24]
Write Cycle No. 2: R/W Three-State Data I/Os (Either Port)
t
WC
ADDRESS
t
t
HA
SCE
SEM OR CE
R/W
t
AW
t
SA
t
PWE
t
t
SD
HD
DATA VALID
DATA IN
t
t
LZWE
HZWE
HIGH IMPEDANCE
DATA OUT
C006-14
[25]
Semaphore Read After Write Timing, Either Side
t
AA
t
OHA
A –A
0
VALID ADDRESS
VALID ADDRESS
2
t
AW
t
ACE
t
HA
SEM
t
t
SOP
SCE
t
SD
I/O
0
DATA VALID
DATA
VALID
IN
OUT
t
HD
t
SA
t
PWE
R/W
OE
t
t
DOE
SWRD
t
SOP
WRITE CYCLE
READ CYCLE
C006-15
Notes:
24. Data I/O pins enter high-impedance when OE is held LOW during write.
25. CE = HIGH for the duration of the above timing (both write and read cycle).
9
CY7C006
CY7C016
Switching Waveforms (continued)
[26, 27, 28]
Semaphore Contention
A
–A
0L 2L
MATCH
R/W
L
SEM
L
t
SPS
A
–A
0R 2R
MATCH
R/W
R
SEM
R
C006-16
[19]
Read with BUSY (M/S=HIGH)
t
WC
ADDRESS
R
MATCH
t
PWE
R/W
R
t
t
HD
SD
DATA IN
VALID
R
t
PS
ADDRESS
L
MATCH
t
BLA
t
BHA
BUSY
DATA
L
t
BDD
t
DDD
VALID
OUTL
t
WDD
C006-17
Write Timing with Busy Input (M/S=LOW)
t
PWE
R/W
t
t
WH
WB
BUSY
C006-18
Notes:
26. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
27. Semaphores are reset (available to both ports) at cycle start.
28. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
10
CY7C006
CY7C016
Switching Waveforms (continued)
[29]
Busy Timing Diagram No. 1 (CE Arbitration)
CE Valid First:
L
ADDRESS
L,R
ADDRESS MATCH
CE
L
t
PS
CE
R
t
t
BHC
BLC
BUSY
R
C006-19
Valid First:
CE
R
ADDRESS
ADDRESS MATCH
L,R
CE
R
t
PS
CE
L
t
t
BHC
BLC
BUSY
L
C006-20
[28]
Busy Timing Diagram No. 2 (Address Arbitration)
Left AddressValid First:
t
or t
WC
RC
ADDRESS
ADDRESS
L
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
R
t
t
BHA
BLA
BUSY
R
C006-21
Right Address Valid First:
t
or t
WC
RC
ADDRESS
ADDRESS
R
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
L
t
t
BHA
BLA
BUSY
L
C006-22
Notes:
29. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
30. HA depends on which enable pin (CEL or R/WL) is deasserted first.
31. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
t
11
CY7C006
CY7C016
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INT :
R
t
WC
ADDRESS
L
WRITE 3FFF
[30]
t
HA
CE
L
R/W
L
INT
R
[31]
t
INS
C006-23
Right Side Clears INT :
R
t
RC
ADDRESS
R
READ 3FFF
CE
R
t
INR
R/W
R
OE
R
INT
C006-24
R
Right Side Sets INT :
L
t
WC
ADDRESS
R
WRITE 3FFF
[30]
t
HA
CE
R
R
R/W
INT
L
[30]
t
INS
C006-25
Left Side Clears INT :
L
t
RC
ADDRESS
R
READ 3FFF
CE
L
L
t
INR
R/W
OE
L
INT
L
C006-26
12
CY7C006
CY7C016
Interrupts
Architecture
The interrupt flag (INT) permits communications between ports.
When the left port writes to location 3FFF(HEX), the right port’s inter-
The CY7C006/016 consists of a an array of 16K words of 8/9
bits each of dual-port RAM cells, I/O and address lines, and
control signals (CE, OE, R/W). These control pins permit indepen-
dent access for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY pin is pro-
vided on each port. Two Interrupt (INT) pins can be utilized for
port-to-port communication. Two Semaphore (SEM) control pins are
used for allocating shared resources. With the M/S pin, the
CY7C006/016 can function as a Master (BUSY pins are outputs) or
as a slave (BUSY pins are inputs). The CY7C006/016 has an auto-
matic power-down feature controlled by CE. Each port is provided
with its own Output Enable control (OE), which allows data to be read
from the device.
rupt flag (INT ) is set. This flag is cleared when the right port reads
R
that same location. Setting the left port’s interrupt flag (INT ) is ac-
L
complished when the right port writes to location 3FFE(HEX). This
flagisclearedwhentheleft port reads location3FFE(HEX). Themes-
sage at 3FFE(HEX) and 3FFF(HEX) is user-defined. See Table 2 for
input requirements for INT. INT and INT are push-pull outputs and
R
L
do not require pull-up resistors to operate.
Busy
The CY7C006/016 provides on-chip arbitration to resolve si-
multaneous memory location access (contention). If both
ports’ CEs are asserted and an address match occurs within t of
PS
each other the Busy logic will determine which port has access. If t
PS
Functional Description
is violated, one port will definitely gain permission to the location, but
it is not guaranteed which one. BUSY will be asserted t after an
BLA
Write Operation
address match or t
after CE is taken LOW. BUSY and BUSY
BLC
L R
in master mode are push-pull outputs and do not require pull-up re-
sistors to operate.
Data must be set up for a duration of t before the rising edge
SD
of R/W in order to guarantee a valid write. A write operation is con-
trolled by either the OE pin (see Write Cycle No.1 waveform) or the
R/W pin (see Write Cycle No. 2 waveform). Data can be written to the
Master/Slave
An M/S pin is provided in order to expand the word width by config-
uring the device as either a master or a slave. The BUSY output of
the master is connected to the BUSY input of the slave. This will allow
the device to interface to a master device with no external compo-
nents. Writing of slave devices must be delayed until after the BUSY
device t
after the OE is deasserted or t
after the falling
HZOE
HZWE
edge of R/W. Required inputs for non-contention operations are sum-
marized in Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must be met before the data is read on the output; oth-
erwise the data read is not deterministic. Data will be valid on
input has settled (t
). Otherwise, the slave chip may begin a write
BLA
cycle during a contention situation. When presented a HIGH input,
the M/S pin allows the device to be used as a master and therefore
the BUSY line is an output. BUSY can then be used to send the
arbitration outcome to a slave.
the port t
after the data is presented on the other port.
DDD
Table 1. Non-Contending Read/Write
Semaphore Operation
Inputs
Outputs
The CY7C006/016 provides eight semaphore latches which
are separate from the dual-port memory locations. Sema-
phores are used to reserve resources that are shared between
the two ports.The state of the semaphore indicates that a re-
source is in use. For example, if the left port wants to request
a given resource, it sets a latch by writing a 0 to a semaphore
location. The left port then verifies its success in setting the
latch by reading it. After writing to the semaphore, SEM or OE
CE R/W OE SEM
I/O
Operation
Power-Down
0–7/8
H
H
X
H
X
L
H
L
High Z
Data Out
Read Data in
Semaphore
X
H
L
X
H
X
L
X
L
High Z
I/O Lines Disabled
Write to Semaphore
Read
Data In
Data Out
Data In
must be deasserted for t
phore. The semaphore value will be available t
before attempting to read the sema-
SOP
H
L
H
H
L
+ t
after the
SWRD DOE
rising edge of the semaphore write. If the left port was successful
(reads a 0), it assumes control over the shared resource, otherwise
(reads a 1) it assumes the right port has control and continues to poll
the semaphore.When the right side has relinquished control of the
semaphore (by writinga 1), the left sidewill succeedin gainingcontrol
of the semaphore. If the left side no longer requires the semaphore,
a 1 is written to cancel its request.
L
X
X
Write
L
X
Illegal Condition
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available t afterCE or t afterOE are
ACE
DOE
asserted. If the user of the CY7C006/016 wishes to access a sema-
phore flag, then the SEM pin must be asserted instead of the CE pin.
Table 2. Interrupt Operation Example (assumes BUSY =BUSY =HIGH)
L
R
Left Port
Right Port
Function
Set Left INT
R/W
X
CE
X
OE
X
A
INT
L
R/W
L
CE
L
OE
X
A
INT
X
0L–13L
0R–13R
X
3FFE
X
Reset Left INT
Set Right INT
Reset Right INT
X
L
L
3FFE
3FFF
X
H
X
L
L
X
L
L
X
X
X
X
X
X
L
X
X
X
X
X
L
L
3FFF
H
13
CY7C006
CY7C016
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip enable for the semaphore latches (CE must
the right port would immediately own the semaphore as soon as the
left port released it. Table 3 shows sample semaphore operations.
remain HIGH during SEM LOW). A
represents the semaphore
0–2
When reading a semaphore, all eight data lines output the
semaphore value. The read value is latched in an output reg-
ister to prevent the semaphore from changing state during a
write from the other port. If both ports attempt to access the
address. OE and R/W are used in the same manner as a normal
memory access.When writing or reading a semaphore, the other ad-
dress pins have no effect.
When writing to the semaphore, only I/O is used. If a 0 is written
semaphore within t
be obtained by one side or the other, but there is no guarantee which
side will control the semaphore.
of each other, the semaphore will definitely
0
SPS
to the left port of an unused semaphore, a 1 will appear at the same
semaphore address on the right port. That semaphore can now only
be modified by the side showing 0 (the left port in this case). If the left
port now relinquishes control by writing a 1 to the semaphore, the
semaphorewill be set to1 for both sides. However, if the right port had
requested the semaphore (written a 0) while the left port had control,
Initialization of the semaphore is not automatic and must be
reset during initialization program at power-up. All Sema-
phores on both sides should have a one written into them at
initialization from both sides to assure that they will be free
when needed.
Table 3. Semaphore Operation Example
Function
I/O
Left
I/O
Right
Status
0-7/8
0-7/8
No action
1
1
Semaphore free
Left port writes semaphore
0
0
1
1
0
1
1
1
0
1
1
1
0
0
1
1
0
1
1
1
Left port obtains semaphore
Right port writes 0 to semaphore
Left port writes 1 to semaphore
Left port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 1 to semaphore
Right port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 0 to semaphore
Left port writes 1 to semaphore
Right side is denied access
Right port is granted access to semaphore
No change. Left port is denied access
Left port obtains semaphore
No port accessing semaphore address
Right port obtains semaphore
No port accessing semaphore
Left port obtains semaphore
No port accessing semaphore
Ordering Information
16K x8 Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
15
CY7C006-15AC
A65
J81
A65
J81
A65
J81
A65
J81
A65
J81
A65
J81
A65
J81
64-Lead Thin Quad Flat Package
68-Lead Plastic Leaded Chip Carrier
64-Lead Thin Quad Flat Package
68-Lead Plastic Leaded Chip Carrier
64-Lead Thin Quad Flat Package
68-Lead Plastic Leaded Chip Carrier
64-Lead Thin Quad Flat Package
68-Lead Plastic Leaded Chip Carrier
64-Lead Thin Quad Flat Package
68-Lead Plastic Leaded Chip Carrier
64-Lead Thin Quad Flat Package
68-Lead Plastic Leaded Chip Carrier
64-Lead Thin Quad Flat Package
68-Lead Plastic Leaded Chip Carrier
Commercial
CY7C006-15JC
CY7C006-25AC
CY7C006-25JC
CY7C006-25AI
CY7C006-25JI
CY7C006-35AC
CY7C006-35JC
CY7C006-35AI
CY7C006-35JI
CY7C006-55AC
CY7C006-55JC
CY7C006-55AI
CY7C006-55JI
25
35
55
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
14
CY7C006
CY7C016
Ordering Information (continued)
16K x9 Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
80-Lead Thin Quad Flat Package
80-Lead Thin Quad Flat Package
80-Lead Thin Quad Flat Package
80-Lead Thin Quad Flat Package
80-Lead Thin Quad Flat Package
80-Lead Thin Quad Flat Package
80-Lead Thin Quad Flat Package
15
CY7C016-15AC
A80
A80
A80
A80
A80
A80
A80
Commercial
Commercial
Industrial
25
CY7C016-25AC
CY7C016-25AI
CY7C016-35AC
CY7C016-35AI
CY7C016-55AC
CY7C016-55AI
35
55
Commercial
Industrial
Commercial
Industrial
Document #: 38-00416-B
Package Diagrams
64-Lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65
51-85046-B
15
CY7C006
CY7C016
Package Diagrams (continued)
80-Pin Thin Plastic Quad Flat Pack A80
51-85065-B
68-Lead Plastic Leaded Chip Carrier J81
51-85005-A
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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