CY7C024V-20AC [CYPRESS]
Dual-Port SRAM, 4KX16, 20ns, CMOS, PQFP100, PLASTIC, TQFP-100;
| 型号： | CY7C024V-20AC |
| 厂家： | 
CYPRESS |
| 描述： | Dual-Port SRAM, 4KX16, 20ns, CMOS, PQFP100, PLASTIC, TQFP-100 静态存储器 |
| 文件： | 总19页 (文件大小：248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1
CY7C024V/025V/026V
PRELIMINARY
CY7C0241V/0251V/036V
3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM
• Automatic power-down
Features
• Expandable data bus to 32/36 bits or more using Mas-
ter/Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Pin select for Master or Slave
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
• 4/8/16K x 16 organization (CY7C024V/025V/026V)
• 4/8K x 18 organization (CY7C0241V/0251V)
• 16K x 18 organization (CY7C036V)
• 0.35-micron CMOS for optimum speed/power
[1]
• High-speed access: 15 /20/25 ns
• Low operating power
• Commercial and industrial temperature ranges
• Available in 100-pin TQFP
Active: I = 115 mA (typical)
—
CC
• Pin-compatible and functionally equivalent to
IDT70V24, 70V25, and 7V0261.
— Standby: I
= 10 A (typical)
µ
SB3
• Fully asynchronous operation
Logic Block Diagram
R/W
R/W
UB
L
R
R
UB
L
CE
CE
LB
L
R
R
LB
L
OE
OE
R
L
8/9
8/9
8/9
8/9
[2]
[2]
I/O
–I/O
I/O
–I/O
8/9L
8/9L
15/17L
15/17R
[3]
I/O –I/O
[3]
I/O
Control
I/O
Control
I/O –I/O
0L
7/8L
0L
7/8R
12/13/14
12/13/14
[4]
[4]
Address
Decode
Address
Decode
True Dual-Ported
A
A
–A
A
A
–A
11/12/13R
0L
0L
11/1213L
0R
0R
RAM Array
12/13/14
12/13/14
–A[4]
–A[4]
11/12/13R
11/12/13L
CE
CE
OE
Interrupt
Semaphore
Arbitration
L
R
R
OE
L
R/W
R/W
SEM
L
R
R
SEM
L
[5]
[5]
BUSY
BUSY
INT
UB
L
R
R
R
R
INT
L
UB
L
LB
M/S
LB
L
Notes:
1. Call for availability.
2. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.
3. I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices.
4. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices.
5. BUSY is an output in master mode and an input in slave mode.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
October 18, 1999
CY7C024V/025V/026V
CY7C0241V/0251V/036V
PRELIMINARY
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). Two flags
are provided on each port (BUSY and INT). BUSY signals that
the port is trying to access the same location currently being
accessed by the other port. The interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from
one port to the other to indicate that a shared resource is in
use. The semaphore logic is comprised of eight shared latch-
es. Only one side can control the latch (semaphore) at any
time. Control of a semaphore indicates that a shared resource
is in use. An automatic power-down feature is controlled inde-
pendently on each port by a chip select (CE) pin.
Functional Description
The CY7C024V/025V/026V and CY7C0241V/0251V/036V
are low-power CMOS 4K, 8K, and 16K x16/18 dual-port static
RAMs. Various arbitration schemes are included on the devic-
es to handle situations when multiple processors access the
same piece of data. Two ports are provided, permitting inde-
pendent, asynchronous access for reads and writes to any
location in memory. The devices can be utilized as standalone
16/18-bit dual-port static RAMs or multiple devices can be
combined in order to function as a 32/36-bit or wider mas-
ter/slave dual-port static RAM. An M/S pin is provided for im-
plementing 32/36-bit or wider memory applications without the
need for separate master and slave devices or additional dis-
crete logic. Application areas include interprocessor/multipro-
cessor designs, communications status buffering, and dual-
port video/graphics memory.
The CY7C024V/025V/026V and CY7C0241V/0251V/036V
are available in 100-pin Thin Quad Plastic Flatpacks (TQFP).
Pin Configurations
100-Pin TQFP
Top View
100 9998 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
73
NC
NC
NC
NC
1
NC
NC
NC
NC
2
3
4
72
71
70
69
A
5L
I/O
10L
5
6
7
8
A
4L
I/O
11L
I/O
12L
A
A
A
3L
2L
1L
0L
68
I/O
13L
67
66
GND
9
A
I/O
I/O
14L
15L
10
11
12
13
INT
BUSY
GND
M/S
L
65
64
63
62
L
V
CC
CY7C024V (4K x 16)
CY7C025V (8K x 16)
GND
I/O
0R
14
BUSY
INT
R
R
61
60
59
I/O
1R
I/O
2R
15
16
17
A
0R
A
1R
V
CC
58
I/O
3R
18
19
20
21
57
56
55
54
53
A
2R
A
3R
I/O
4R
I/O
5R
I/O
6R
A
4R
NC
NC
22
23
NC
NC
NC
NC
NC
52
51
24
25
NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 4748 49 50
Notes:
6.
7.
A
A
12L on the CY7C025.
12R on the CY7C025.
2
CY7C024V/025V/026V
CY7C0241V/0251V/036V
PRELIMINARY
Pin Configurations (continued)
Top View
100-Pin TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
73
NC
NC
NC
NC
1
NC
NC
2
3
4
I/O
8L
17L
11L
72
71
70
69
I/O
I/O
A
5L
5
6
7
8
A
4L
I/O
12L
I/O
13L
A
A
A
3L
2L
1L
0L
68
I/O
14L
67
66
GND
9
A
I/O
I/O
15L
16L
10
11
12
13
INT
BUSY
GND
M/S
L
65
64
63
62
L
V
CC
CY7C0241V (4K x 18)
CY7C0251V (8K x 18)
GND
I/O
0R
14
BUSY
INT
R
61
60
59
R
I/O
1R
I/O
2R
15
16
17
A
A
A
0R
1R
V
CC
58
I/O
3R
18
19
20
21
57
56
55
54
53
2R
3R
I/O
I/O
I/O
I/O
4R
A
5R
A
4R
6R
8R
NC
22
23
NC
NC
I/O
17R
52
51
NC
NC
24
25
NC
26 27 28 29 30 31 32 3334 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
NC
1
NC
NC
NC
NC
I/O10L
I/O11L
I/O12L
I/O13L
GND
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
A6L
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
A5R
NC
I/O14L
I/O15L
VCC
GND
CY7C026V (16K x 16)
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
NC
NC
NC
NC
24
25
NC
NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Notes:
8.
9.
A
A
12L on the CY7C0251.
12R on the CY7C0251.
3
CY7C024V/025V/026V
CY7C0241V/0251V/036V
PRELIMINARY
Pin Configurations (continued)
100-Pin TQFP
Top View
100 9998 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
73
NC
NC
NC
1
NC
NC
2
3
4
I/O
8L
A
13L
72
71
70
69
I/O
17L
I/O
11L
A
A
A
A
A
5L
4L
3L
2L
1L
0L
5
6
7
8
I/O
I/O
I/O
12L
13L
14L
68
67
66
GND
9
A
I/O
I/O
15L
16L
10
11
12
13
INT
BUSY
GND
M/S
L
65
64
63
62
L
V
CC
CY7C036V (16K x 18)
GND
I/O
0R
14
BUSY
INT
R
61
60
59
58
R
I/O
1R
I/O
2R
15
16
17
18
19
20
21
A
A
A
0R
1R
V
CC
I/O
3R
57
56
55
54
53
2R
3R
I/O
I/O
I/O
I/O
4R
A
5R
A
4R
A
13R
6R
8R
22
23
NC
NC
I/O
17R
52
51
NC
NC
24
25
NC
26 27 28 29 30 31 32 3334 35 36 37 38 39 40 41 42 43 44 45 46 4748 49 50
Selection Guide
CY7C024V/025V/026V
CY7C024V/025V/026V
CY7C024V/025V/026V
CY7C0241V/0251V/036V CY7C0241V/0251V/036V CY7C0241V/0251V/036V
[1]
-15
-20
-25
Maximum Access Time (ns)
Typical Operating Current (mA)
15
20
25
125
35
120
35
115
30
Typical Standby Current for I
(Both ports TTL level)
(mA)
SB1
Typical Standby Current for I
(Both ports CMOS Level)
(µA)
10 µA
10 µA
10 µA
SB3
Shaded areas contain advance information.
4
CY7C024V/025V/026V
CY7C0241V/0251V/036V
PRELIMINARY
Pin Definitions
Left Port
Right Port
Description
CE
CE
Chip Enable
L
R
R/W
R/W
Read/Write Enable
Output Enable
L
R
OE
OE
R
L
A
–A
A
–A
Address (A –A for 4K devices; A –A for 8K devices; A –A for 16K)
0 11 0 12 0 13
0L
13L
0R
13R
I/O –I/O
I/O –I/O
17R
Data Bus Input/Output
Semaphore Enable
0L
17L
0R
SEM
SEM
R
L
UB
UB
Upper Byte Select (I/O –I/O for x16 devices; I/O –I/O for x18 devices)
8 15 9 17
L
R
LB
LB
Lower Byte Select (I/O –I/O for x16 devices; I/O –I/O for x18 devices)
0 7 0 8
L
R
INT
INT
Interrupt Flag
Busy Flag
L
R
BUSY
M/S
BUSY
R
L
Master or Slave Select
Power
V
CC
GND
NC
Ground
No Connect
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
Latch-Up Current.................................................... >200 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Ambient
Power Applied.............................................–55°C to +125°C
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
V
CC
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
3.3V ± 300 mV
3.3V ± 300 mV
DC Voltage Applied to
Outputs in High Z State ...........................–0.5V to V +0.5V
CC
Shaded areas contain advance information.
[10]
DC Input Voltage .................................–0.5V to V +0.5V
CC
Note:
10. Pulse width < 20 ns.
5
CY7C024V/025V/026V
CY7C0241V/0251V/036V
PRELIMINARY
Electrical Characteristics Over the Operating Range
CY7C024V/025V/026V
CY7C0241V/0251V/036V
[1]
-15
-20
-25
Parameter
Description
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
V
V
V
V
Output HIGH Voltage (V =3.3V)
2.4
2.4
2.4
V
OH
OL
IH
CC
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
0.4
0.8
0.4
0.4
V
2.0
2.0
2.0
V
0.8
10
0.8
10
V
IL
I
I
I
Output Leakage Current
Input Leakage Current
–10
–10
10 –10
10 –10
–10
–10
µA
µA
mA
mA
mA
mA
mA
mA
µA
µA
mA
mA
OZ
10
10
IX
Operating Current (V = Max.,
Com’l.
Indust.
Com’l.
Indust.
Com’l.
Indust.
125 185
120 175
140 195
115 165
135 185
CC
CC
I
= 0 mA) Outputs Disabled
OUT
I
I
I
I
Standby Current (Both Ports TTL
Level) CE & CE ≥ V , f = f
35
50
35
45
75
85
10
10
70
80
45
55
30
40
65
75
10
10
60
70
40
50
SB1
SB2
SB3
SB4
L
R
IH
MAX
Standby Current (One Port TTL
Level) CE | CE ≥ V , f = f
MAX
80 120
10 250
75 105
110
120
250
250
95
95
L
R
IH
105
250
250
80
Standby Current(BothPortsCMOS Com’l.
Level) CE & CE ≥ V −0.2V, f = 0
L
R
CC
Indust.
Standby Current (One Port CMOS Com’l.
[11]
MAX
Level) CE | CE ≥ V , f = f
L
R
IH
Indust.
105
90
Shaded areas contain advance information.
Capacitance[12]
Parameter
Description
Test Conditions
Max.
Unit
C
C
Input Capacitance
Output Capacitance
T = 25°C, f = 1 MHz,
CC
10
10
pF
pF
IN
A
V
= 3.3V
OUT
AC Test Loads and Waveforms
3.3V
3.3V
R
TH
= 250
Ω
R1 = 590
Ω
Ω
OUTPUT
C = 30pF
OUTPUT
C = 30 pF
R1 = 590
Ω
OUTPUT
R2 = 435
C = 5 pF
R2 = 435
Ω
V
TH
= 1.4V
(a) Normal Load (Load 1)
(c)Three-State Delay(Load 2)
(b) Thévenin Equivalent (Load 1)
(Used for t , t , t
, & t
LZ HZ HZWE
LZWE
including scope and jig)
ALL INPUTPULSES
3.0V
GND
90%
90%
10%
3 ns
10%
3 ns
≤
≤
Notes:
11. MAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3
f
.
12. Tested initially and after any design or process changes that may affect these parameters.
6
CY7C024V/025V/026V
CY7C0241V/0251V/036V
PRELIMINARY
[13]
Switching Characteristics Over the Operating Range
CY7C024V/025V/026V
CY7C0241V/0251V/036V
[1]
-15
-20
-25
Parameter
Description
Min.
Max.
Min.
20
Max.
Min.
25
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
15
20
25
AA
3
3
3
OHA
[14]
15
10
20
12
25
13
ACE
DOE
LZOE
[15, 16, 17]
[15, 16, 17]
3
3
0
3
3
0
3
3
0
OE HIGH to High Z
10
10
12
12
15
15
HZOE
[15, 16, 17]
CE LOW to Low Z
LZCE
[15, 16, 17]
CE HIGH to High Z
HZCE
[17]
[17]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable Access Time
PU
15
15
20
20
25
25
PD
[14]
ABE
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
15
12
12
0
20
15
15
0
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
[14]
CE LOW to Write End
SCE
Address Valid to Write End
Address Hold From Write End
Address Set-Up to Write Start
Write Pulse Width
AW
HA
[14]
SA
0
0
0
12
10
0
15
15
0
20
15
0
PWE
SD
Data Set-Up to Write End
Data Hold From Write End
R/W LOW to High Z
HD
[16, 17]
10
12
15
HZWE
[16, 17]
LZWE
R/W HIGH to Low Z
3
3
0
[18]
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
30
25
45
30
50
35
WDD
[18]
DDD
Notes:
13. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
OI/IOH and 30-pF load capacitance.
14. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time.
I
15. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE
.
16. Test conditions used are Load 3.
17. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing
with Busy waveform.
18. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
7
CY7C024V/025V/026V
CY7C0241V/0251V/036V
PRELIMINARY
[13]
Switching Characteristics Over the Operating Range (continued)
CY7C024V/025V/026V
CY7C0241V/0251V/036V
[1]
-15
-20
-25
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
[19]
BUSY TIMING
t
t
t
t
t
t
t
t
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
15
15
15
15
20
20
20
17
20
20
20
17
ns
ns
ns
ns
ns
ns
ns
ns
BLA
BHA
BLC
BHC
PS
BUSY HIGH from CE HIGH
Port Set-Up for Priority
5
0
5
0
5
0
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
WB
13
15
17
WH
[20]
BUSY HIGH to Data Valid
15
20
25
BDD
[19]
INTERRUPT TIMING
t
t
INT Set Time
INT Reset Time
15
15
20
20
20
20
ns
ns
INS
INR
SEMAPHORE TIMING
t
t
t
t
SEM Flag Update Pulse (OE or SEM)
10
5
10
5
12
5
ns
ns
ns
ns
SOP
SWRD
SPS
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
5
5
5
15
20
25
SAA
Data Retention Mode
Timing
The CY7C024V/025V/026V and CY7C0241V/0251V/036V
are designed with battery backup in mind. Data retention volt-
age and supply current are guaranteed over temperature. The
following rules ensure data retention:
Data Retention Mode
3.0V
V
CC
3.0V
V
CC
2.0V
>
t
RC
1. Chip Enable (CE) must beheldHIGHduringdataretention, with-
in V to V – 0.2V.
CC
CC
V
CC
to V – 0.2V
CC
V
IH
CE
2. CE must be kept between V – 0.2V and 70% of V
CC
CC
during the power-up and power-down transitions.
3. The RAM can begin operation >t after V reaches the
minimum operating voltage (3.0 volts).
RC
CC
[21]
Parameter
ICC
Test Conditions
@ VCC = 2V
Max.
Unit
50
µA
DR1
DR
Notes:
19. Test conditions used are Load 2.
20. BDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
t
21. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
8
CY7C024V/025V/026V
CY7C0241V/0251V/036V
PRELIMINARY
Switching Waveforms
[22, 23, 24]
Read Cycle No.1 (Either Port Address Access)
t
RC
ADDRESS
t
AA
t
t
OHA
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
[22, 25, 26]
Read Cycle No.2 (Either Port CE/OE Access)
t
ACE
CE and
LB or UB
t
HZCE
t
DOE
OE
t
HZOE
t
LZOE
DATA VALID
DATA OUT
t
LZCE
t
PU
t
PD
I
CC
CURRENT
I
SB
[22, 24, 25, 26]
Read Cycle No. 3 (Either Port)
t
RC
ADDRESS
t
t
OHA
AA
UB or LB
t
t
HZCE
t
LZCE
t
ABE
CE
HZCE
t
ACE
t
LZCE
DATA OUT
Notes:
22. R/W is HIGH for read cycles.
23. Device is continuously selected CE = VIL and UB or LB = V . This waveform cannot be used for semaphore reads.
IL
24. OE = VIL
.
25. Address valid prior to or coincident with CE transition LOW.
26. To access RAM, CE= VIL, UB or LB = V , SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
IL
9
CY7C024V/025V/026V
CY7C0241V/0251V/036V
PRELIMINARY
Switching Waveforms (continued)
[27, 28, 29, 30]
Write Cycle No.1: R/W Controlled Timing
t
WC
ADDRESS
OE
[33]
t
HZOE
t
AW
[31,32]
CE
[30]
PWE
t
SA
t
t
HA
R/W
DATA OUT
DATA IN
[33]
t
HZWE
t
LZWE
NOTE 34
NOTE 34
t
t
HD
SD
[27, 28, 29, 35]
Write Cycle No. 2: CE Controlled Timing
t
WC
ADDRESS
t
AW
[31,32]
CE
t
SA
t
t
HA
SCE
R/W
t
t
HD
SD
DATA IN
Notes:
27. R/W must be HIGH during all address transitions.
28. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB.
29. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
30. If OEis LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on
the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE
31. To access RAM, CE= VIL, SEM = VIH
32. To access upper byte, CE = V , UB = VIL, SEM = VIH
.
.
.
IL
To access lower byte, CE = VIL, LB = VIL, SEM = VIH
.
33. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
34. During this period, the I/O pins are in the output state, and input signals must not be applied.
35. If the CEor SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
10
CY7C024V/025V/026V
CY7C0241V/0251V/036V
PRELIMINARY
Switching Waveforms (continued)
[36]
Semaphore Read After Write Timing, Either Side
t
t
OHA
SAA
A
–A
2
VALID ADRESS
VALID ADRESS
0
t
AW
t
ACE
t
HA
SEM
t
t
SOP
SCE
t
SD
I/O
0
DATA VALID
DATA
VALID
IN
OUT
t
HD
t
SA
t
PWE
R/W
OE
t
t
DOE
SWRD
t
SOP
WRITE CYCLE
[37, 38, 39]
READ CYCLE
Timing Diagram of Semaphore Contention
A
0L
–A
2L
MATCH
R/W
L
SEM
L
t
SPS
A
–A
MATCH
0R
2R
R/W
R
SEM
R
Notes:
36. CE = HIGH for the duration of the above timing (both write and read cycle).
37. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
38. Semaphores are reset (available to both ports) at cycle start.
39. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
11
CY7C024V/025V/026V
CY7C0241V/0251V/036V
PRELIMINARY
Switching Waveforms (continued)
[40]
Timing Diagram of Read with BUSY (M/S=HIGH)
t
WC
ADDRESS
R
MATCH
t
PWE
R/W
R
t
t
HD
SD
DATA IN
VALID
R
t
PS
ADDRESS
L
MATCH
t
BLA
t
BHA
BUSY
L
t
BDD
t
DDD
DATA
VALID
OUTL
t
WDD
Write Timing with Busy Input (M/S=LOW)
t
PWE
R/W
t
t
WH
WB
BUSY
Note:
40. CEL = CER = LOW.
12
CY7C024V/025V/026V
CY7C0241V/0251V/036V
PRELIMINARY
Switching Waveforms (continued)
[41]
Busy Timing Diagram No.1 (CE Arbitration)
CE Valid First:
L
ADDRESS
L,R
ADDRESS MATCH
CE
L
t
PS
CE
R
t
t
BHC
BLC
BUSY
R
CE Valid First:
R
ADDRESS
L,R
ADDRESS MATCH
CE
R
t
PS
CE
L
L
t
t
BHC
BLC
BUSY
[41]
Busy Timing Diagram No.2 (Address Arbitration)
Left Address Valid First:
t
or t
WC
RC
ADDRESS
L
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
R
t
t
BHA
BLA
BUSY
R
Right Address Valid First:
t
or t
WC
RC
ADDRESS
R
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
L
t
t
BHA
BLA
BUSY
L
Note:
41. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
13
CY7C024V/025V/026V
CY7C0241V/0251V/036V
PRELIMINARY
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INT :
R
t
WC
ADDRESS
L
WRITE 1FFF (OR 1/3FFF)
[42]
t
HA
CE
L
R/W
INT
L
R
[43]
t
INS
Right Side Clears INT :
R
t
RC
READ 7FFF
(OR 1/3FFF)
ADDRESS
R
CE
R
[43]
t
INR
R/W
R
OE
R
INT
R
:
Right SideSets INT
L
t
WC
ADDRESS
R
WRITE 1FFE (OR 1/3FFE)
[42]
HA
t
CE
R
R
R/W
INT
L
[43]
INS
t
Left Side Clears INT :
L
t
RC
READ 7FFE
OR 1/3FFE)
ADDRESS
R
L
CE
[43]
INR
t
R/W
L
OE
INT
L
L
Notes:
42.
tHA depends on which enable pin (CEL or R/WL) is deasserted first.
43. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
14
CY7C024V/025V/026V
CY7C0241V/0251V/036V
PRELIMINARY
and an address match occurs within t of each other, the busy
Architecture
PS
logic will determine which port has access. If t is violated,
PS
The CY7C024V/025V/026V and CY7C0241V/0251V/036V
consist of an array of 4K, 8K, and 16K words of 16 and 18 bits
each of dual-port RAM cells, I/O and address lines, and control
signals (CE, OE, R/W). These control pins permit independent
access for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY pin is
provided on each port. Two Interrupt (INT) pins can be utilized
for port-to-port communication. Two semaphore (SEM) control
pins are used for allocating shared resources. With the M/S
pin, the devices can function as a master (BUSY pins are out-
puts) or as a slave (BUSY pins are inputs). The devices also
have an automatic power-down feature controlled by CE. Each
port is provided with its own output enable control (OE), which
allows data to be read from the device.
one port will definitely gain permission to the location, but it is
not predictable which port will get that permission. BUSY will
be asserted t
taken LOW.
after an address match or t
after CE is
BLA
BLC
Master/Slave
A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the
slave. This will allow the device to interface to a master device
with no external components. Writing to slave devices must be
delayed until after the BUSY input has settled (t
or t
),
BLC
BLA
otherwise, the slave chip may begin a write cycle during a con-
tention situation. When tied HIGH, the M/S pin allows the de-
vice to be used as a master and, therefore, the BUSY line is
an output. BUSY can then be used to send the arbitration out-
come to a slave.
Functional Description
Write Operation
Semaphore Operation
Data must be set up for a duration of t before the rising edge
SD
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1 wave-
form) or the CE pin (see Write Cycle No. 2 waveform). Required
inputs for non-contention operations are summarized in Table 1.
The CY7C024V/025V/026V and CY7C0241V/0251V/036V
provide eight semaphore latches, which are separate from the
dual-port memory locations. Semaphores are used to reserve
resources that are shared between the two ports. The state of
the semaphore indicates that a resource is in use. For exam-
ple, if the left port wants to request a given resource, it sets a
latch by writing a zero to a semaphore location. The left port
then verifies its success in setting the latch by reading it. After
writing to the semaphore, SEM or OE must be deasserted for
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output; other-
wise the data read is not deterministic. Data will be valid on the
port t
after the data is presented on the other port.
DDD
t
before attempting to read the semaphore. The sema-
SOP
Read Operation
phore value will be available t
+ t
after the rising edge
SWRD
DOE
of the semaphore write. If the left port was successful (reads
a zero), it assumes control of the shared resource, otherwise
(reads a one) it assumes the right port has control and contin-
ues to poll the semaphore. When the right side has relin-
quished control of the semaphore (by writing a one), the left
side will succeed in gaining control of the semaphore. If the left
side no longer requires the semaphore, a one is written to
cancel its request.
When reading the device, the user must assert both the OE
and CE pins. Data will be available t
after CE or t
after
ACE
DOE
OE is asserted. If the user wishes to access a semaphore flag,
then the SEM pin must be asserted instead of the CE pin, and
OE must also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (FFF for the
CY7C024V/41V, 1FFF for the CY7C025V/51V, 3FFF for the
CY7C026V/36V) is the mailbox for the right port and the sec-
ond-highest memory location (FFE for the CY7C024V/41V,
1FFE for the CY7C025V/51V, 3FFE for the CY7C026V/36V) is
the mailbox for the left port. When one port writes to the other
port’s mailbox, an interrupt is generated to the owner. The in-
terrupt is reset when the owner reads the contents of the mail-
box. The message is user defined.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A
represents the
0–2
semaphore address. OE and R/W are used in the same man-
ner as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O is used. If a zero is
0
written to the left port of an available semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes con-
trol by writing a one to the semaphore, the semaphore will be
set to one for both sides. However, if the right port had request-
ed the semaphore (written a zero) while the left port had con-
trol, the right port would immediately own the semaphore as
soon as the left port released it. Table 3 shows sample sema-
phore operations.
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the busy signal (to a port)
prevents the port from setting the interrupt to the winning port.
Also, an active busy to a port prevents that port from reading
its own mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not con-
nect the interrupt pin to the processor’s interrupt request input pin.
The operation of the interrupts and their interaction with Busy
are summarized in Table 2.
When reading a semaphore, all sixteen/eighteen data lines
output the semaphore value. The read value is latched in an
output register to prevent the semaphore from changing state
during a write from the other port. If both ports attempt to ac-
Busy
The CY7C024V/025V/026V and CY7C0241V/0251V/036V
provide on-chip arbitration to resolve simultaneous memory
location access (contention). If both ports’ CEs are asserted
cess the semaphore within t
of each other, the semaphore
SPS
will definitely be obtained by one side or the other, but there is
no guarantee which side will control the semaphore.
15
CY7C024V/025V/026V
CY7C0241V/0251V/036V
PRELIMINARY
Table 1. Non-Contending Read/Write
Inputs
Outputs
CE
H
X
L
R/W
X
OE
X
X
X
X
X
L
UB
X
H
L
LB
X
H
H
L
SEM
H
H
H
H
H
H
H
H
X
I/O –I/O
I/O –I/O
8
Operation
Deselected: Power-Down
Deselected: Power-Down
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
9
17
0
High Z
High Z
X
High Z
High Z
High Z
L
Data In
High Z
L
L
H
L
Data In
Data In
High Z
L
L
L
Data In
Data Out
High Z
L
H
H
H
X
L
H
L
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
L
L
H
L
Data Out
Data Out
High Z
L
L
L
Data Out
High Z
X
H
X
H
H
L
X
X
H
X
X
X
H
X
Outputs Disabled
H
H
L
Data Out
Data Out
Data In
Data Out
Data Out
Data In
Read Data in Semaphore Flag
Read Data in Semaphore Flag
L
L
X
L
Write D into Semaphore Flag
IN0
X
X
H
H
L
Data In
Data In
Write D into Semaphore Flag
IN0
L
L
X
X
X
X
L
X
L
L
L
Not Allowed
Not Allowed
X
[44]
Table 2. Interrupt Operation Example (assumes BUSY =BUSY =HIGH)
L
R
Left Port
Right Port
Function
Set Right INT Flag
R/W
CE
L
OE
X
A
INT
X
R/W
X
CE
X
OE
X
A
INT
L
L
L
0L–13L
L
R
R
R
0R–13R
R
[47]
[46]
L
X
X
FFF
X
L
R
[45]
Reset Right INT Flag
X
X
X
X
X
X
L
L
FFF (or 1/3FFF)
H
R
[45]
Set Left INT Flag
X
X
L
L
L
X
1FFE (or
1/3FFE)
X
X
L
[47]
[46]
Reset Left INT Flag
X
L
L
1FFE
H
X
X
X
X
L
Table 3. Semaphore Operation Example
Function I/O –I/O Left I/O –I/O Right
Status
0
17
0
17
No action
1
0
0
1
1
0
1
1
1
0
1
1
Semaphore free
Left Port has semaphore token
Left port writes 0 to semaphore
Right port writes 0 to semaphore
Left port writes 1 to semaphore
Left port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 1 to semaphore
Right port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 0 to semaphore
1
1
0
0
1
1
0
1
1
1
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
Left port writes 1 to semaphore
Notes:
44. See Functional Description for specific highest memory locations by device.
45. If BUSYR=L, then no change.
46. If BUSYL=L, then no change.
47. See Functional Description for specific addresses by device.
16
CY7C024V/025V/026V
CY7C0241V/0251V/036V
PRELIMINARY
Ordering Information
4K x16 3.3V Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
(ns)
Ordering Code
CY7C024V-15AC
Package Type
Range
Commercial
Commercial
Industrial
[1]
15
A100
A100
A100
A100
A100
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
20
CY7C024V-20AC
CY7C024V-20AI
CY7C024V-25AC
CY7C024V-25AI
25
Commercial
Industrial
8K x16 3.3V Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
[1]
15
CY7C025V-15AC
A100
A100
A100
A100
A100
Commercial
Commercial
Industrial
20
25
CY7C025V-20AC
CY7C025V-20AI
CY7C025V-25AC
CY7C025V-25AI
Commercial
Industrial
16K x18 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Package
Operating
Range
Ordering Code
CY7C026V-15AC
Name
A100
A100
A100
A100
A100
Package Type
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
[1]
15
Commercial
Commercial
Industrial
20
CY7C026V-20AC
CY7C026V-20AI
CY7C026V-25AC
CY7C026V-25AI
25
Commercial
Industrial
4K x18 3.3V Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C0241V-15AC
CY7C0241V-20AC
CY7C0241V-20AI
CY7C0241V-25AC
CY7C0241V-25AI
Package Type
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
[1]
15
A100
A100
A100
A100
A100
Commercial
Commercial
Industrial
20
25
Commercial
Industrial
8K x18 3.3V Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C0251V-15AC
CY7C0251V-20AC
CY7C0251V-20AI
CY7C0251V-25AC
CY7C0251V-25AI
Package Type
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
[1]
15
A100
A100
A100
A100
A100
Commercial
Commercial
Industrial
20
25
Commercial
Industrial
Shaded areas contain advance information.
17
CY7C024V/025V/026V
CY7C0241V/0251V/036V
PRELIMINARY
Ordering Information (continued)
16K x18 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Package
Operating
Ordering Code
CY7C036V-15AC
Name
A100
A100
A100
A100
A100
Package Type
Range
Commercial
Commercial
Industrial
[1]
15
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
20
CY7C036V-20AC
CY7C036V-20AI
CY7C036V-25AC
CY7C036V-25AI
25
Commercial
Industrial
Shaded areas contain advance information.
Document #: 38–00678–B
Package Diagram
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-B
18
CY7C024V/025V/026V
CY7C0241V/0251V/036V
PRELIMINARY
Troubleshooting—If a problem occurs with the part, power
down the device to ground and then power up again at slower
ramp rate (greater than 100 ns) in order to confirm that the
problem might be due to the POR circuit. If the dual-port func-
tions properly once the ramp rate is slowed to 100 ns or great-
er, then the POR circuit is at fault.
CY7C036 Dual Port Design Consideration –
Data Sheet Addendum
This design consideration applies to the Internal Power-On-
Reset (POR) circuit used on the CY7C036 and its derivatives
listed below.
Applicable devices—All speed/package/temperature combi-
nations of the following:
Power supply ramp—The devices will function properly and
meet all data sheet specifications if the power supply ramp rate
is greater than 100 ns. If ramp is less than 100 ns, you may
see a non-destructive failure in which the device will not re-
spond to changes in address or clock, but the I/Os will respond
to the output enable.
• CY7C024V
• CY7C025V
• CY7C026V
• CY7C0241V
• CY7C0251V
• CY7C036V
Applications consideration—If the power supply ramps in less
than 100 ns, a small resistor (20–50Ω), a large capacitor, or an
RC network can be connected at the output of the power sup-
ply to ground. The addition of a resistor will help clean up the
power lines, while the capacitor will slow down the ramp rate
without the loss of any power. Contact your local Cypress FAE
for assistance as needed.
Cypress design change—Cypress design team has identified
the root cause. A permanent circuit change and die revision
will be available beginning in October and will be identified by
the letter “A” in the part number.
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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