CY7C057V-12ACT [CYPRESS]
Dual-Port SRAM, 32KX36, 12ns, CMOS, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-144;
| 型号： | CY7C057V-12ACT |
| 厂家： | 
CYPRESS |
| 描述： | Dual-Port SRAM, 32KX36, 12ns, CMOS, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-144 静态存储器 |
| 文件： | 总23页 (文件大小：773K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C056V CY7C057V CY7C037V CY7C038V3.3V 16K/32K
FLEx36™ Asynchronous Dual-Port Static RAM
x 36
CY7C056V
CY7C057V
3.3V 16K/32K x 36
FLEx36™ Asynchronous Dual-Port Static
• On-Chip arbitration logic
Features
• Semaphores included to permit software handshaking
between ports
• True dual-ported memory cells that allow simultaneous
access of the same memory location
• INT flag for port-to-port communication
• Byte Select on Left Port
• 16K x 36 organization (CY7C056V)
• 32K x 36 organization (CY7C057V)
• 0.25-micron CMOS for optimum speed/power
• High-speed access: 12/15/20 ns
• Low operating power
• Bus Matching on Right Port
• Depth Expansion via dual chip enables
• Pin select for Master or Slave
• Commercial and Industrial Temperature Ranges
• Available in 144-Pin TQFP or 172-Ball BGA
• Pb-Free packages available
— Active: ICC = 250 mA (typical)
— Standby: ISB3 = 10 µA (typical)
• Fully asynchronous operation
• Automatic power-down
• Compact packages:
— 144-Pin TQFP (20 x 20 x 1.4 mm)
— 172-Ball BGA (1.0-mm pitch) (15 x 15 x.51 mm)
• Expandable data bus to 72 bits or more using
Master/Slave Chip Select when using more than one
device
Logic Block Diagram
R/WL
R/WR
B0–B3
CE0L
CE1L
Left
Port
Control
Logic
Right
CE0R
CE1R
Port
Control
Logic
CEL
CER
OEL
OER
BA
WA
9
9
9
9
9
9
9
9
I/O0L–I/O8L
9/18/36
I/O9L–I/O17L
I/O18L–I/O26L
I/O27L–I/O35L
Bus
Match
I/O
Control
I/O
Control
I/OR
BM
SIZE
14/15
14/15
Address
Decode
Address
Decode
True Dual-Ported
[1]
[1]
A0L–A13/14L
A0R–A13/14R
RAM Array
14/15
14/15
Interrupt
Semaphore
Arbitration
SEML
SEMR
[2]
[2]
BUSYL
INTL
BUSYR
INTR
M/S
Notes:
1. A –A for 16K; A –A for 32K devices.
0
13
0
14
2. BUSY is an output in Master mode and an input in Slave mode.
Cypress Semiconductor Corporation
Document #: 38-06055 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 6, 2005
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CY7C056V
CY7C057V
Each port has independent control pins: Chip Enable (CE)[3]
,
Functional Description
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. TheInterrupt Flag
(INT) permits communication between ports or systems by
means of a mail box. The semaphores are used to pass a flag,
or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch
(semaphore) at any time. Control of a semaphore indicates
that a shared resource is in use. An automatic Power-Down
feature is controlled independently on each port by Chip Select
(CE0 and CE1) pins.
The CY7C056V and CY7C057V are low-power CMOS 16K
and 32K x 36 dual-port static RAMs. Various arbitration
schemes are included on the devices to handle situations
when multiple processors access the same piece of data. Two
ports are provided, permitting independent, asynchronous
access for reads and writes to any location in memory. The
devices can be utilized as standalone 36-bit dual-port static
RAMs or multiple devices can be combined in order to function
as a 72-bit or wider master/slave dual-port static RAM. An M/S
pin is provided for implementing 72-bit or wider memory appli-
cations without the need for separate master and slave
devices or additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications
status buffering, and dual-port video/graphics memory.
The CY7C056V and CY7C057V are available in 144-Pin Thin
Quad Plastic Flatpack (TQFP) and 172-Ball Ball Grid Array
(BGA) packages.
Note:
3. CE is LOW when CE ≤ V and CE ≥ V .
0
IL
1
IH
Document #: 38-06055 Rev. *B
Page 2 of 23
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CY7C056V
CY7C057V
Pin Configurations
144-Pin Thin Quad Flatpack (TQFP)
Top View
I/O33L
I/O34L
1
2
108
I/O33R
I/O34R
107
106
I/O35L
A0L
I/O35R
A0R
3
4
105
104
103
102
A1L
5
6
7
A1R
A2R
A2L
A3R
A4R
A5R
A6R
A7R
A3L
A4L
8
101
100
A5L
A6L
A7L
9
10
99
98
97
11
12
BM
SIZE
B0
B1
13
14
15
96
95
94
WA
B2
B3
BA
16
17
18
19
93
92
91
90
OER
R/WR
OEL
R/WL
VDD
VSS
VDD
VSS
CY7C056V (16K x 36)
CY7C057V (32K x 36)
VDD
VSS
20
21
89
88
CE0L
CE1L
M/S
CE0R
CE1R
VDD
22
23
24
25
87
86
85
84
83
82
SEML
INTL
SEMR
INTR
BUSYR
BUSYL
A8L
26
27
A8R
A9R
A10R
28
29
30
31
A9L
81
80
A10L
79
78
77
A11R
A12R
A13R
A11L
A12L
A13L
[4]
NC
I/O26L
I/O25L
I/O24L
32
33
[5]
NC
76
75
34
35
36
I/O26R
74
73
I/O25R
I/O24R
Notes:
4. This pin is A14L for CY7C057V.
5. This pin is A14R for CY7C057V.
Document #: 38-06055 Rev. *B
Page 3 of 23
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CY7C056V
CY7C057V
Pin Configurations (continued)
172-Ball Ball Grid Array (BGA)
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
I/O32L I/O30L
NC
VSS
I/O13L VDD I/O11L I/O11R VDD I/O13R
VSS
NC
I/O30R I/O32R
A
B
C
D
E
F
A0L
NC
I/O33L
A1L
I/O29
I/O17L I/O14L I/O12L I/O9L I/O9R I/O12R I/O14R I/O17R I/O29R I/O33R
A0R
NC
I/O31L I/O27L
NC
I/O15L I/O10L I/O10R I/O15R
NC
I/O27R I/O31R A1R
A2L
A3L
I/O35L I/O34L I/O28L I/O16L
VSS
VSS I/O16R I/O28R I/O34R I/O35R A3R
A2R
A4R
VDD
OER
VSS
A9R
A11R
A4L
A5L
NC
A7L
B3L
A8L
VSS
NC
B0L
B1L
NC
NC
NC
NC
NC
NC
BM
NC
A7R
BA
A5R
A6R
VDD
OEL
VSS
A9L
A6L
SIZE
B2L
CE0L
CE1L
M/S
CE0R
CE1R
VDD
WA
G
H
J
R/WL
A10L
A12L
A13L
A8R
VDD
NC
R/WR
A10R
A12R
NC
NC
NC
NC
A11L
BUSYL
SEML
NC
NC
SEMR
K
INTL
I/O26L I/O25L I/O19L
VSS
VSS I/O19R I/O25R I/O26R INTR
A13R BUSYR
L
M
N
P
[4]
[5]
NC
NC
I/O22L I/O18L
NC
I/O7L
I/O3L
VDD
I/O2L I/O2R I/O7R
NC
I/O18R I/O22R NC
NC
I/O24L I/O20L
I/O23L I/O21L
I/O8L
NC
I/O6L
VSS
I/O5L
I/O4L
I/O0L I/O0R I/O3R I/O5R
I/O6R
VSS
I/O8R I/O20R I/O24R
I/O1L I/O1R
VDD
I/O4R
NC
I/O21R I/O23R
Selection Guide
CY7C056V
CY7C057V
-12
CY7C056V
CY7C057V
-15
CY7C056V
CY7C057V
-20
Unit
ns
Maximum Access Time
12
250
55
15
240
50
20
230
45
Typical Operating Current
Typical Standby Current for ISB1 (Both Ports TTL Level)
Typical Standby Current for ISB3 (Both Ports CMOS Level)
mA
mA
µA
10 µA
10 µA
10 µA
Document #: 38-06055 Rev. *B
Page 4 of 23
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CY7C056V
CY7C057V
Pin Definitions
Left Port
A0L–A13/14L
SEML
Right Port
A0R–A13/14R
Description
Address (A0–A13 for 16K; A0–A14 for 32K devices)
Semaphore Enable
SEMR
CE0L, CE1L
INTL
CE0R, CE1R
INTR
Chip Enable (CE is LOW when CE0 ≤ VIL and CE1 ≥ VIH)
Interrupt Flag
BUSYL
BUSYR
I/O0R–I/O35R
OER
Busy Flag
I/O0L–I/O35L
OEL
Data Bus Input/Output
Output Enable
Read/Write Enable
R/WL
R/WR
B0–B3
Byte Select Inputs. Asserting these signals enables read and write opera-
tions to the corresponding bytes of the memory array.
BM, SIZE
WA, BA
See Bus Matching for details.
See Bus Matching for details.
Master or Slave Select
Ground
M/S
VSS
VDD
Power
Maximum Ratings[6]
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... >2001V
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Ambient
Power Applied.............................................–55°C to +125°C
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VDD
Supply Voltage to Ground Potential............... –0.5V to +4.6V
3.3V ± 165 mV
3.3V ± 165 mV
DC Voltage Applied to
Outputs in High Z State............................–0.5V to VDD+0.5V
DC Input Voltage.................................. –0.5V to VDD+0.5V[7]
Shaded areas contain advance information.
Notes:
6. The voltage on any input or I/O pin can not exceed the power pin during power-up.
7. Pulse width < 20 ns.
Document #: 38-06055 Rev. *B
Page 5 of 23
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CY7C056V
CY7C057V
Electrical Characteristics Over the Operating Range[8, 9]
CY7C056V
CY7C057V
-12
-15
-20
Parameter
Description
Output HIGH Voltage
VOH
(VDD = Min., IOH = –4.0 mA)
2.4
2.4
2.4
V
VOL
Output LOW Voltage
(VDD = Min., IOL = +4.0 mA)
0.4
0.8
0.4
0.8
0.4
0.8
V
V
V
VIH
VIL
IOZ
ICC
Input HIGH Voltage
Input LOW Voltage
2.0
2.0
2.0
Output Leakage Current
–10
10 –10
10 –10
240 360
265 385
10 µA
230 340 mA
mA
Operating Current (VDD = Max.,
IOUT = 0 mA) Outputs Disabled
Commercial
Industrial
250 385
55 75
ISB1
Standby Current (Both Ports TTL
Level and Deselected)
f = fMAX
Commercial
Industrial
50
70
45
65 mA
65
95
mA
ISB2
Standby Current (One Port TTL
Level and Deselected)
f = fMAX
Commercial
Industrial
180 240
175 230
190 255
165 210 mA
mA
ISB3
Standby Current (Both Ports CMOS
Level and Deselected) f =0
Commercial
Industrial
0.01
1
0.01
0.01
1
1
0.01
1
mA
mA
ISB4
Standby Current (One Port CMOS
Level and Deselected) f = fMAX
Commercial
Industrial
160 210
155 200
170 215
145 180 mA
mA
[10]
Capacitance[11]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
DD = 3.3V
Max.
10
Unit
pF
CIN
V
COUT
10
pF
Notes:
8. Cross Levels are V – 0.2V< V < 0.2V.
DD
Z
9. Deselection for a port occurs if CE is HIGH or if CE is LOW.
0
1
10. f
= 1/t = All inputs cycling at f = 1/t (except Output Enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level
MAX
RC RC
standby I
.
SB3
11. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06055 Rev. *B
Page 6 of 23
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CY7C056V
CY7C057V
AC Test Load and Waveforms
3.3V
Z0 = 50Ω
R = 50Ω
OUTPUT
R1 = 590Ω
[12]
C
OUTPUT
V
TH
= 1.5V
C = 5 pF
R2 = 435Ω
(b) Three-State Delay (Load 2)
(a) Normal Load (Load 1)
3.0V
VSS
90%
10%
90%
10%
3 ns
ALL INPUT PULSES
3 ns
≤
≤
7
6
5
4
3
2
1
20[13]
30 60 80 100
200
Capacitance (pF)
(b) Load Derating Curve
Notes:
12. External AC Test Load Capacitance = 10 pF.
13. (Internal I/O pad Capacitance = 10 pF) + AC Test Load.
Document #: 38-06055 Rev. *B
Page 7 of 23
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CY7C056V
CY7C057V
Switching Characteristics Over the Operating Range[14]
CY7C056V
CY7C057V
-12
-15
-20
Parameter
Description
Min.
12
Max.
Min.
Max.
Min.
20
Max.
Unit
Read Cycle
tRC
Read Cycle Time
15
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
12
15
20
tOHA
tACE
tDOE
3
3
[3, 15]
12
8
15
10
20
12
[3, 16, 17, 18]
tLZOE
0
3
3
0
0
3
3
0
0
3
3
0
[3, 16, 17, 18]
tHZOE
OE HIGH to High Z
10
10
10
10
10
10
12
12
12
[3, 14, 17, 18]
tLZCE
CE LOW to Low Z
[3, 16, 17, 18]
tHZCE
tLZBE
tHZBE
CE HIGH to High Z
Byte Enable to Low Z
Byte Enable to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable Access Time
[3, 18]
tPU
[3, 18]
[15]
tPD
12
12
15
15
20
20
tABE
Write Cycle
tWC
Write Cycle Time
12
10
10
0
15
12
12
0
20
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[3, 15]
tSCE
CE LOW to Write End
tAW
tHA
Address Valid to Write End
Address Hold From Write End
Address Set-Up to Write Start
Write Pulse Width
[15]
tSA
0
0
0
tPWE
tSD
10
10
0
12
10
0
15
15
0
Data Set-Up to Write End
Data Hold From Write End
R/W LOW to High Z
tHD
[17, 18]
tHZWE
10
10
12
[17, 18]
tLZWE
R/W HIGH to Low Z
3
3
3
[19]
tWDD
Write Pulse to Data Delay
25
20
30
25
45
30
[19]
tDDD
Write Data Valid to Read Data Valid
Busy Timing[20]
tBLA
tBHA
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
12
12
12
15
15
15
20
20
20
ns
ns
ns
tBLC
Notes:
14. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I and 10-pF load capacitance.
OI OH
15. To access RAM, CE = L and SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire t
time.
SCE
16. At any given temperature and voltage condition for any given device, t
17. Test conditions used are Load 2.
is less than t
and t
is less than t
.
HZCE
LZCE
HZOE
LZOE
18. This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading port,
refer to Read Timing with Busy waveform.
19. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
20. Test conditions used are Load 1.
Document #: 38-06055 Rev. *B
Page 8 of 23
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CY7C056V
CY7C057V
Switching Characteristics Over the Operating Range[14] (continued)
CY7C056V
CY7C057V
-12
-15
-20
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Busy Timing[20]
tBHC
tPS
tWB
tWH
BUSY HIGH from CE HIGH
Port Set-Up for Priority
12
15
20
ns
ns
ns
ns
ns
5
0
5
0
5
0
R/W LOW after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
11
13
15
[21]
tBDD
12
15
20
Interrupt Timing[20]
tINS
INT Set Time
12
12
15
15
20
20
ns
ns
tINR
INT Reset Time
Semaphore Timing
tSOP
tSWRD
tSPS
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
10
5
10
5
10
5
ns
ns
ns
ns
5
5
5
tSAA
12
15
20
Data Retention Mode
Timing
The CY7C056V and CY7C057V are designed with battery
backup in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules ensure data
retention:
Data Retention Mode
3.15V
V
CC
3.15V
V
CC
> 2.0V
t
RC
1. Chip Enable (CE)[3] must be held HIGH during data
retention, within VDD to VDD – 0.2V.
V
CC
to V – 0.2V
CC
V
IH
CE
2. CE must be kept between VDD – 0.2V and 70% of VDD
during the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VDD reaches the
minimum operating voltage (3.15 volts).
Parameter
ICCDR1
Test Conditions[22]
Max.
Unit
µA
@ VDDDR = 2V
50
Notes:
21. t
is a calculated parameter and is the greater of t
–t
(actual) or t
–t (actual).
DDD SD
BDD
WDD PWE
22. CE = V , V = V to V , T = 25°C. This parameter is guaranteed but not tested.
DD
in
SS
DD
A
Document #: 38-06055 Rev. *B
Page 9 of 23
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CY7C056V
CY7C057V
Switching Waveforms
Read Cycle No. 1 (Either Port Address Access)[23, 24, 25]
t
RC
ADDRESS
DATA OUT
t
AA
t
t
OHA
OHA
PREVIOUS DATAVALID
DATA VALID
Read Cycle No. 2 (Either Port CE/OE Access)[23, 26, 27]
t
ACE
CE0, CE1, B0,B1,
B2, B3, WA, BA
SELECT VALID
t
HZCE
t
DOE
OE
t
HZOE
t
LZOE
DATA VALID
DATA OUT
t
LZCE
t
PU
t
PD
ICC
CURRENT
ISB
Read Cycle No. 3 (Either Port)[23, 25, 26, 27]
t
RC
ADDRESS
t
AA
t
OHA
B0, B1, B2,
B3, WA, BA
BYTE SELECT VALID
t
HZCE
t
t
LZCE
LZCE
t
ABE
CE0, CE1
CHIP SELECT VALID
t
ACE
t
HZCE
DATA OUT
Notes:
23. R/W is HIGH for read cycles.
24. Device is continuously selected. CE = V , CE =V , and B , B , B , B , WA, BA are valid. This waveform cannot be used for semaphore reads.
0
IL
1
IH
0
1
2
3
25. OE = V
.
IL
26. Address valid prior to or coinciding with CE transition LOW and CE transition HIGH.
0
1
27. To access RAM, CE = V , CE =V , B , B , B , B , WA, BA are valid, and SEM = V . To access semaphore, CE = V , CE =V and SEM = V or CE
0
IL
1
IH
0
1
2
3
IH
0
IH
1
IL
IL
0
and SEM=V , and CE = B = B = B = B , =V .
IH
IL
1
0
1
2
3
Document #: 38-06055 Rev. *B
Page 10 of 23
[+] Feedback
CY7C056V
CY7C057V
Switching Waveforms (continued)
Write Cycle No. 1: R/W Controlled Timing[28, 29, 30, 31]
t
WC
ADDRESS
OE
[34]
t
HZOE
t
AW
[32, 33]
CE0, CE1
CHIP SELECT VALID
[31]
t
t
t
HA
SA
PWE
R/W
[34]
HZWE
t
t
LZWE
NOTE 35
NOTE 35
DATAOUT
DATA IN
t
t
HD
SD
Write Cycle No. 2: CE Controlled Timing[28, 29, 30, 36]
t
WC
ADDRESS
t
AW
[32, 33]
CHIP SELECT VALID
CE0, CE1
t
t
t
HA
SA
SCE
R/W
t
t
HD
SD
DATA IN
Notes:
28. R/W must be HIGH during all address transitions.
29. A write occurs during the overlap (t or t ) of CE =V and CE =V or SEM=V and B LOW.
0–3
SCE
PWE
0
IL
1
IH
IL
30. t is measured from the earlier of CE /CE or R/W or (SEM or R/W) going HIGH at the end of Write Cycle.
HA
0
1
31. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
or (t
+ t ) to allow the I/O drivers to turn off and data
PWE
HZWE SD
to be placed on the bus for the required t . If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be
SD
as short as the specified t
.
PWE
32. To access RAM, CE = V , CE =SEM = V .
0
IL
1
IH
33. To access byte B , CE = V , B = V , CE =SEM = V
.
.
.
.
0
0
IL
0
IL
1
IH
IH
IH
IH
To access byte B , CE = V , B = V , CE =SEM = V
1
2
0
0
IL
IL
1
2
IL
IL
1
1
To access byte B , CE = V , B = V , CE =SEM = V
To access byte B , CE = V , B = V , CE =SEM = V
3
0
IL
3
IL
1
34. Transition is measured ±150 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
35. During this period, the I/O pins are in the output state, and input signals must not be applied.
36. If the CE LOW and CE HIGH or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance
0
1
state.
Document #: 38-06055 Rev. *B
Page 11 of 23
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CY7C056V
CY7C057V
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[37]
t
t
OHA
SAA
A0–A2
VALID ADRESS
VALID ADRESS
t
AW
t
ACE
t
HA
SEM
t
t
SOP
SCE
t
SD
I/O0
DATA VALID
DATA
VALID
IN
OUT
t
HD
t
t
PWE
SA
R/W
OE
t
t
DOE
SWRD
t
SOP
WRITE CYCLE
READ CYCLE
Timing Diagram of Semaphore Contention[38, 39, 40]
A0L–A2L
MATCH
R/WL
SEM L
t
SPS
A0R–A2R
MATCH
R/WR
SEMR
Notes:
37. CE = HIGH and CE = LOW for the duration of the above timing (both write and read cycle).
0
1
38. I/O = I/O = LOW (request semaphore); CE = CE = HIGH and CE = CE =LOW.
0R
0L
0R
0L
1R
1L
39. Semaphores are reset (available to both ports) at cycle start.
40. If t is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
SPS
Document #: 38-06055 Rev. *B
Page 12 of 23
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CY7C056V
CY7C057V
Switching Waveforms (continued)
Timing Diagram of Write with BUSY (M/S = HIGH)[41]
t
WC
ADDRESSR
R/WR
MATCH
t
PWE
t
t
HD
SD
DATA IN R
VALID
t
PS
ADDRESSL
MATCH
t
BLA
t
BHA
BUSYL
t
BDD
t
DDD
DATAOUTL
VALID
t
WDD
Write Timing with Busy Input (M/S = LOW)
t
PWE
R/W
t
t
WH
WB
BUSY
Note:
41. CE = CE = LOW; CE = CE = HIGH.
0L
0R
1L
1R
Document #: 38-06055 Rev. *B
Page 13 of 23
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CY7C056V
CY7C057V
Switching Waveforms (continued)
Busy Timing Diagram No. 1 (CE Arbitration)[42]
CEL Valid First:
ADDRESSL,R
CE0L, CE1L
ADDRESS MATCH
CHIP SELECT VALID
t
PS
CE0R, CE1R
CHIP SELECT VALID
t
t
BHC
BLC
BUSYR
CER Valid First:
ADDRESS
ADDRESS MATCH
L,R
CE0L, CE1L
CHIP SELECT VALID
t
PS
CE0R, CE1R
BUSYL
CHIP SELECT VALID
t
t
BHC
BLC
Busy Timing Diagram No. 2 (Address Arbitration)[42]
Left Address Valid First:
t
or t
WC
RC
ADDRESSL
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESSR
BUSYR
t
t
BHA
BLA
Right Address Valid First:
t
or t
WC
RC
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESSL
BUSR
t
t
BHA
BLA
Note:
42. If t is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
PS
Document #: 38-06055 Rev. *B
Page 14 of 23
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CY7C056V
CY7C057V
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR:
t
WC
ADDRESSL
WRITE 3FFF (7FFF for CY7C057V)
[43]
t
HA
CE0L, CE1L
R/WL
CHIP SELECT VALID
INTR
[44]
INS
t
Right Side Clears INTR:
t
RC
READ 3FFF
(7FFF for CY7C057V)
ADDRESSR
CE0R, CE1R
CHIP SELECT VALID
[44]
t
INR
R/W
R
OER
INTR
Right Side Sets INTL:
t
WC
ADDRESSR
WRITE 3FFE (7FFE for CY7C057V)
[43]
t
HA
CE0R, CE1R
R/WR
CHIP SELECT VALID
INTR
[44]
INS
t
Left Side Clears INTL:
t
RC
READ 3FFE
(7FFF for CY7C057V)
ADDRESSL
CE0L, CE1L
R/WL
CHIP SELECT VALID
[44]
t
INR
OEL
INTL
Notes:
43. t depends on which enable pin (CE /CE or R/W ) is deasserted first.
HA
0L
1L
L
44. t
or t
depends on which enable pin (CE /CE or R/W ) is asserted last.
INS
INR 0L 1L L
Document #: 38-06055 Rev. *B
Page 15 of 23
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CY7C056V
CY7C057V
both ports’ Chip Enables[3] are asserted and an address match
occurs within tPS of each other, the busy logic will determine
which port has access. If tPS is violated, one port will definitely
gain permission to the location, but it is not predictable which
port will get that permission. BUSY will be asserted tBLA after
an address match or tBLC after CE is taken LOW.
Architecture
The CY7C056V and CY7C057V consist of an array of 16K and
32K words of 36 bits each of dual-port RAM cells, I/O and
address lines, and control signals (CE0/CE1, OE, R/W). These
control pins permit independent access for reads or writes to
any location in memory. To handle simultaneous writes/reads
to the same location, a BUSY pin is provided on each port. Two
Interrupt (INT) pins can be utilized for port-to-port communi-
cation. Two Semaphore (SEM) control pins are used for
allocating shared resources. With the M/S pin, the devices can
function as a master (BUSY pins are outputs) or as a slave
(BUSY pins are inputs). The devices also have an automatic
power-down feature controlled by CE0/CE1. Each port is
provided with its own Output Enable control (OE), which allows
data to be read from the device.
Master/Slave
A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the
slave. This will allow the device to interface to a master device
with no external components. Writing to slave devices must be
delayed until after the BUSY input has settled (tBLC or tBLA),
otherwise, the slave chip may begin a write cycle during a
contention situation. When tied HIGH, the M/S pin allows the
device to be used as a master and, therefore, the BUSY line
is an output. BUSY can then be used to send the arbitration
outcome to a slave.
Functional Description
Write Operation
Semaphore Operation
Data must be set up for a duration of tSD before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CE0 and CE1 pins (see Write Cycle No. 2
waveform). Required inputs for non-contention operations are
summarized in Table 1.
The CY7C056V and CY7C057V provide eight semaphore
latches, which are separate from the dual-port memory
locations. Semaphores are used to reserve resources that are
shared between the two ports. The state of the semaphore
indicates that a resource is in use. For example, if the left port
wants to request a given resource, it sets a latch by writing a
zero to a semaphore location. The left port then verifies its
success in setting the latch by reading it. After writing to the
semaphore, SEM or OE must be deasserted for tSOP before
attempting to read the semaphore. The semaphore value will
be available tSWRD + tDOE after the rising edge of the
semaphore write. If the left port was successful (reads a 0), it
assumes control of the shared resource, otherwise (reads a 1)
it assumes the right port has control and continues to poll the
semaphore. When the right side has relinquished control of the
semaphore (by writing a 1), the left side will succeed in gaining
control of the semaphore. If the left side no longer requires the
semaphore, a one is written to cancel its request.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port tDDD after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE
and CE[3] pins. Data will be available tACE after CE or tDOE
after OE is asserted. If the user wishes to access a semaphore
flag, then the SEM pin must be asserted instead of the CE[3]
pin, and OE must also be asserted.
Interrupts
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches. For
normal semaphore access, CE[3] must remain HIGH during
SEM LOW. A CE active semaphore access is also available.
The semaphore may be accessed through the right port with
CE0R/CE1R active by asserting the Bus Match Select (BM) pin
LOW and asserting the Bus Size Select (SIZE) pin HIGH. The
semaphore may be accessed through the left port with
CE0L/CE1L active by asserting all B0–3 Byte Select pins HIGH.
A0–2 represents the semaphore address. OE and R/W are
used in the same manner as a normal memory access. When
writing or reading a semaphore, the other address pins have
no effect.
The upper two memory locations may be used for message
passing. The highest memory location (3FFF for the
CY7C056V, 7FFF for the CY7C057V) is the mailbox for the
right port and the second-highest memory location (3FFE for
the CY7C056V, 7FFE for the CY7C057V) is the mailbox for the
left port. When one port writes to the other port’s mailbox, an
interrupt is generated to the owner. The interrupt is reset when
the owner reads the contents of the mailbox. The message is
user defined.
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the busy signal (to a port)
prevents the port from setting the interrupt to the winning port.
Also, an active busy to a port prevents that port from reading
its own mailbox and, thus, resetting the interrupt to it.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a 1 will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the port showing 0
(the left port in this case). If the left port now relinquishes
control by writing a 1 to the semaphore, the semaphore will be
set to 1 for both ports. However, if the right port had requested
the semaphore (written a 0) while the left port had control, the
right port would immediately own the semaphore as soon as
the left port released it. Table 3 shows sample semaphore
operations.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy
are summarized in Table 2.
Busy
The CY7C056V and CY7C057V provide on-chip arbitration to
resolve simultaneous memory location access (contention). If
Document #: 38-06055 Rev. *B
Page 16 of 23
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CY7C056V
CY7C057V
Table 1. Non-Contending Read/Write[3]
Inputs
Outputs
I/O0–I/O35
High Z
CE
H
X
L
R/W
X
OE
X
X
X
X
L
B0, B1, B2, B3
SEM
H
Operation
X
All H
H/L
All L
H/L
All L
X
Deselected: Power-Down
Deselected: Power-Down
Write to Selected Bytes Only
Write to All Bytes
X
H
High Z
L
H
Data In and High Z
Data In
L
L
H
L
H
H
Data Out and High Z
Data Out
Read Selected Bytes Only
Read All Bytes
L
H
L
H
X
H
X
H
X
H
L
X
High Z
Outputs Disabled
H
X
L
Data Out
Read Data in Semaphore Flag
Read Data in Semaphore Flag
Write DIN0 into Semaphore Flag
H
L
All H
X
L
Data Out
X
L
Data In
X
L
X
X
All H
L
L
Data In
Write DIN0 into Semaphore Flag
Not Allowed
X
Any L
Table 2. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH)[3, 45]
Left Port
Right Port
Function
R/WL CEL
OEL
X
A0L–13L
3FFF
X
INTL R/WR CER
OER
X
A0R–13R
X
INTR
L[47]
H[46]
X
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
L
X
X
X
L
X
X
L
X
X
X
X
L
X
L
L
X
X
L
3FFF
3FFE
X
X
X
L[46]
H[47]
X
L
3FFE
X
X
X
Table 3. Semaphore Operation Example
Function I/O0–I/O8 Left I/O0–I/O8 Right
Status
No Action
1
0
0
1
1
1
Semaphore Free
Left Port Has Semaphore Token
Left Port Writes 0 to Semaphore
Right Port Writes 0 to
Semaphore
No Change. Right Side Has No Write Access to
Semaphore
Left Port Writes 1 to Semaphore
Left Port Writes 0 to Semaphore
1
1
0
0
0
1
Right Port Obtains Semaphore Token
No Change. Left Port Has No Write Access to Semaphore
Left Port Obtains Semaphore Token
Right Port Writes 1 to
Semaphore
Left Port Writes 1 to Semaphore
1
1
1
0
Semaphore Free
Right Port Writes 0 to
Semaphore
Right Port Has Semaphore Token
Right Port Writes 1 to
Semaphore
1
1
Semaphore Free
Left Port Writes 0 to Semaphore
0
1
1
1
Left Port Has Semaphore Token
Semaphore Free
Left Port Writes 1 to Semaphore
Notes:
45. A
and A
, 7FFF/7FFE for the CY7C057V.
0R–14R
0L–14L
46. If BUSY =L, then no change.
R
47. If BUSY =L, then no change.
L
Document #: 38-06055 Rev. *B
Page 17 of 23
[+] Feedback
CY7C056V
CY7C057V
Right Port Configuration[48, 49, 50]
BM
0
SIZE
Configuration
I/O Pins Used
0
1
0
1
x36 (Standard)
I/O0–35
I/O0–35
I/O0–17
I/O0–8
0
x36 (CE Active SEM Mode)
1
x18
x9
1
Right Port Operation
Configuration
WA
X
0
BA
X
X
X
0
Data Accessed[51]
DQ0–35
I/O Pins Used
I/O0–35
I/O0–17
I/O0–17
I/O0–8
x36
x18
x18
x9
DQ0–17
1
DQ18–35
DQ0–8
0
x9
0
1
DQ9–17
I/O0–8
x9
1
0
DQ18–26
DQ27–35
I/O0–8
x9
1
1
I/O0–8
Left Port Operation
Control Pin
Effect
B0
B1
B2
B3
I/O0–8 Byte Control
I/O9–17 Byte Control
I/O18–26 Byte Control
I/O27–35 Byte Control
When reading a semaphore, data lines 0 through 8 output the
semaphore value. The read value is latched in an output
register to prevent the semaphore from changing state during
a write from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore will definitely
be obtained by one side or the other, but there is no guarantee
which side will control the semaphore.
Bus Match Operation
The right port of the CY7C057V 32Kx36 dual-port SRAM can
be configured in a 36-bit long-word, 18-bit word, or 9-bit byte
format for data I/O. The data lines are divided into four lanes,
each consisting of 9 bits (byte-size data lines).
BA WA
When reading a semaphore, data lines 0 through 8 output the
semaphore value. The read value is latched in an output
register to prevent the semaphore from changing state during
a write from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore will definitely
be obtained by one side or the other, but there is no guarantee
which side will control the semaphore.
9
/
9
/
9
/
CY7C056V
CY7C057V
16K/32Kx36
Dual Port
x36
/
x9, x18, x36
/
9
/
When reading a semaphore, data lines 0 through 8 output the
semaphore value. The read value is latched in an output
register to prevent the semaphore from changing state during
a write from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore will definitely
be obtained by one side or the other, but there is no guarantee
which side will control the semaphore.
BM SIZE
The Bus Match Select (BM) pin works with Bus Size Select
(SIZE) to select bus width (long-word, word, or byte) for the
right port of the dual-port device. The data sequencing
arrangement is selected using the Word Address (WA) and
Byte Address (BA) input pins. A logic “0” applied to both the
Bus Match Select (BM) pin and to the Bus Size Select (SIZE)
Notes:
48. BM and SIZE must be configured one clock cycle before operation is guaranteed.
49. In x36 mode WA and BA pins are “Don’t Care.”
50. In x18 mode BA pin is a “Don’t Care.”
51. DQ represents data output of the chip.
Document #: 38-06055 Rev. *B
Page 18 of 23
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CY7C056V
CY7C057V
pin will select long-word (36-bit) operation. A logic “1” level
applied to the Bus Match Select (BM) pin will enable either
byte or word bus width operation on the right port I/Os
depending on the logic level applied to the SIZE pin. The level
of Bus Match Select (BM) must be static throughout device
operation.
Word (18-bit) Operation
Word (18-bit) bus sizing operation is enabled when Bus Match
Select (BM) is set to a logic “1” and the Bus SIze Select (SIZE)
pin is set to a logic “0.” In this mode, 18 bits of data are ported
through I/O0R–17R. The level applied to the Word Address
(WA) pin during word bus size operation determines whether
the most-significant or least-significant data bits are ported
through the I/O0R–17R pins in an Upper Word/Lower Word
select fashion (note that when the right port is configured for
word size operation, the Byte Address pin has no application
and its input is “Don’t Care”[52]).
Normally, the Bus Size Select (SIZE) pin would have no
standard-cycle application when BM = LOW and the device is
in long-word (36-bit) operation. A “special” mode has been
added however to disable ALL right port I/Os while the chip is
active. This I/O disable mode is implemented when SIZE is
forced to a logic “1” while BM is at a logic “0”. It allows the
bus-matched port to support a chip enable “Don’t Care”
semaphore read/write access similar to that provided on the
left port of the device when all Byte Select (B0–3) control inputs
are deselected.
Device operation is accomplished by treating the WA pin as an
additional address input and using standard cycle address and
data setup/hold times. When transferring data in word (18-bit)
bus match format, the unused I/O18R–35R pins are
three-stated.
The Bus Size Select (SIZE) pin selects either a byte or word
data arrangement on the right port when the Bus Match Select
(BM) pin is HIGH. A logic “1” on the SIZE pin when the BM pin
is HIGH selects a byte bus (9-bit) data arrangement). A logic
“0” on the SIZE pin when the BM pin is HIGH selects a word
bus (18-bit) data arrangement. The level of the Bus Size Select
(SIZE) must also be static throughout normal device operation.
Byte (9-bit) Operation
Byte (9-bit) bus sizing operation is enabled when Bus Match
Select (BM) is set to a logic “1” and the Bus Size Select (SIZE)
pin is set to a logic “1.” In this mode, data is ported through
I/O0R–8R in four groups of 9-bit bytes. A particular 9-bit byte
group is selected according to the levels applied to the Word
Address (WA) and Byte Address (BA) input pins.
Long-Word (36-bit) Operation
Bus Match Select (BM) and Bus Size Select (SIZE) set to a
logic “0” will enable standard cycle long-word (36-bit)
operation. In this mode, the right port’s I/O operates essentially
in an identical fashion as does the left port of the dual-port
SRAM. However no Byte Select control is available. All 36 bits
of the long-word are shifted into and out of the right port’s I/O
buffer stages. All read and write timing parameters may be
identical with respect to the two data ports. When the right port
is configured for a long-word size, Word Address (WA), and
Byte Address (BA) pins have no application and their inputs
are “Don’t Care”[52] for the external user.
I/Os
Rank
WA
1
BA
1
I/O27R–35R
I/O18R–26R
I/O9R–17R
I/O0R–8R
Upper-MSB
Lower-MSB
Upper-MSB
Lower-MSB
1
0
0
1
0
0
Device operation is accomplished by treating the Word
Address (WA) pin and the Byte Address (BA) pins as
additional address inputs having standard cycle address and
data set-up/hold times. When transferring data in byte (9-bit)
bus match format, the unused I/O9R–35R pins are three-stated.
Note:
52. Even though a logic level applied to a “Don’t Care” input will not change the logical operation of the dual-port, inputs that are temporarily a “Don’t Care” (along
with unused inputs) must not be allowed to float. They must be forced either HIGH or LOW.
Document #: 38-06055 Rev. *B
Page 19 of 23
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CY7C056V
CY7C057V
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
144-Pin Thin Quad Flat Pack
144-Pin Pb-Free Thin Quad Flat Pack
172-Ball Ball Grid Array (BGA)
144-Pin Thin Quad Flat Pack
144-Pin Pb-Free Thin Quad Flat Pack
172-Ball Ball Grid Array (BGA)
144-Pin Thin Quad Flat Pack
172-Ball Ball Grid Array (BGA)
12
CY7C056V-12AC
CY7C056V-12AXC
CY7C056V-12BBC
CY7C056V-15AC
CY7C056V-15AXC
CY7C056V-15BBC
CY7C056V-20AC
CY7C056V-20BBC
A144
A144
Commercial
Commercial
Commercial
BB172
A144
15
20
A144
BB172
A144
BB172
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
CY7C057V-12AC
CY7C057V-12AXC
CY7C057V-12BBC
CY7C057V-15AC
CY7C057V-15AXC
CY7C057V-15AI
Package Type
144-Pin Thin Quad Flat Pack
144-Pin Pb-Free Thin Quad Flat Pack
172-Ball Ball Grid Array (BGA)
144-Pin Thin Quad Flat Pack
144-Pin Pb-Free Thin Quad Flat Pack
144-Pin Thin Quad Flat Pack
144-Pin Pb-Free Thin Quad Flat Pack
172-Ball Ball Grid Array (BGA)
172-Ball Ball Grid Array (BGA)
144-Pin Thin Quad Flat Pack
172-Ball Ball Grid Array (BGA)
12
A144
A144
Commercial
BB172
A144
15
Commercial
Industrial
A144
A144
CY7C057V-15AXI
CY7C057V-15BBC
CY7C057V-15BBI
CY7C057V-20AC
CY7C057V-20BBC
A144
BB172
BB172
A144
Commercial
Industrial
20
Commercial
BB172
Document #: 38-06055 Rev. *B
Page 20 of 23
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CY7C056V
CY7C057V
Package Diagrams
144-Pin Plastic Thin Quad Flat Pack (TQFP) A144
144-Pin Pb-Free Plastic Thin Quad Flat Pack (TQFP) A144
51-85047-*A
Document #: 38-06055 Rev. *B
Page 21 of 23
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CY7C056V
CY7C057V
Package Diagrams (continued)
172-Ball FBGA (15 x 15 x 1.25 mm) BB172
51-85114-*B
FLEx36 is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document
may be the trademarks of their respective holders.
Document #: 38-06055 Rev. *B
Page 22 of 23
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C056V
CY7C057V
Document History Page
Document Title: CY7C056V/CY7C057V 3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static RAM
Document Number: 38-06055
Issue
Date
Orig. of
REV.
**
ECN NO.
110214
122305
393770
Change Description of Change
12/16/01
12/27/02
See ECN
SZV
RBI
YIM
Change from Spec number: 38-00742 to 38-06055
*A
Power up requirements added to Maximum Ratings Information
*B
Added Pb-Free Logo
Added Pb-Free parts to ordering information:
CY7C056V-12AXC, CY7C056V-15AXC, CY7C057V-12AXC,
CY7C057V-15AXC, CY7CO57V-15AXI
Document #: 38-06055 Rev. *B
Page 23 of 23
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