CY7C0851V-150AC [CYPRESS]
Dual-Port SRAM, 64KX36, 4ns, CMOS, PQFP176, 24 X 24 MM, 1.40 MM HEIGHT, TQFP-176;
| 型号： | CY7C0851V-150AC |
| 厂家： | 
CYPRESS |
| 描述： | Dual-Port SRAM, 64KX36, 4ns, CMOS, PQFP176, 24 X 24 MM, 1.40 MM HEIGHT, TQFP-176 时钟 静态存储器 内存集成电路 |
| 文件： | 总33页 (文件大小：698K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
3.3V 64K/128K/256K x 36 and 128K/256K x 18
Synchronous Dual-Port RAM
Functional Description (all)
Features (all)
The CY7C085XV/CY7C083XV are 2M, 4.5M, and 9M
• Truedual-portedmemorycells that allow simultaneous
access of the same memory location
• Synchronous pipelined
• Organization of 2M, 4.5M, and 9M devices
— 256K × 36 (CY7C0853V)
pipelined, synchronous, true dual-port static RAMs that are
high-speed, low-power 3.3V CMOS. Two ports are provided,
permitting independent, simultaneous access for Reads from
any location in memory. A particular port can write to a certain
location while another port is reading that location. The result
of writing to the same location by more than one port at the
same time is undefined. Registers on control, address, and
data lines allow for minimal set-up and hold time.
— 128K × 36 (CY7C0852V)
— 64K × 36 (CY7C0851V)
— 256K × 18 (CY7C0832V)
Functional Description (all except CY7C0853V)
— 128K × 18 (CY7C0831V)
During a Read operation, data is registered for decreased
cycle time. Clock to data valid tCD2 = 4.0 ns at 150 MHz. Each
port contains a burst counter on the input address register.
After externally loading the counter with the initial address, the
counter will increment the address internally (more details to
follow). The internal Write pulse width is independent of the
duration of the R/W input signal. The internal Write pulse is
self-timed to allow the shortest possible cycle times.
• Pipelined output mode allows fast 150-MHz operation
• 0.18-micron CMOS for optimum speed and power
• High-speed clock to data access: 4.0 ns (max.)
• 3.3V low operating power
— Active = 300 mA (typical)
— Standby = 10 mA (typical)
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle with chip enables asserted is required
to reactivate the outputs.
• Interrupt flags for message passing
• Global master reset
• Separate byte enables on both ports
• Commercial and industrial temperature ranges
• IEEE 1149.1-compatible JTAG boundary scan
• 172-ball BGA (1 mm pitch) (15 mm × 15 mm)
• 120-pin TQFP (14 mm × 14 mm × 1.4 mm)
• 176-pin TQFP (24 mm × 24 mm × 1.4 mm)
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and utilize the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS) and CNTEN signals are LOW. When the
port’s CNTEN is asserted and the ADS is deasserted, the
address counter will increment on each LOW to HIGH
transition of that port’s clock signal. This will Read/Write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array, and will loop back to the start. Counter reset (CNTRST)
is used to reset the unmasked portion of the burst counter to
0s. A counter-mask register is used to control the counter
wrap. The counter and mask register operations are described
in more detail in the following sections.
• FLEx36 devices are pin footprint upgradeable from
2M to 4M to 9M
Features (all except CY7C0853V)
• Counter wrap around control
— Internal maskregister controlscounter wrap-around
— Counter-interrupt flags to indicate wrap-around
— Memory block retransmit operation
• Counter readback on address lines
• Mask register readback on address lines
• Dual Chip Enables on both ports for easy depth
expansion
New features added to the CY7C08X1V/CY7C08X2V devices
include: readback of burst-counter internal address value on
address lines, counter-mask registers to control the counter
wrap-around, counter interrupt (CNTINT) flags, readback of
mask register value on address lines, retransmit functionality,
interrupt flags for message passing, JTAG for boundary scan,
and asynchronous Master Reset (MRST).
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-06059 Rev. *C
Revised April 22, 2002
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Logic Block Diagram[1]
OEL
R/WL
OER
R/WR
B0L
B1L
B2L
B3L
B0R
B1R
B2R
B3R
[2]
[2]
[2]
[2]
CE0L
CE1L
CE0R
CE1R
9
9
DQ –DQ
27L
DQ –DQ
27R
35L
26L
35R
26R
17R
9
9
9
9
9
9
DQ –DQ
18L
DQ –DQ
18R
I/O
Control
I/O
Control
DQ –DQ
9L
DQ –DQ
9R
17L
DQ –DQ
0L
DQ –DQ
0R 8R
8L
Addr.
Read
Back
Addr.
Read
Back
True
Dual-Ported
RAM Array
17
17
A0L–A16L
A0R–A16R
Mask Register
Mask Register
[2]
[2]
CNT/MSKR
CNT/MSKL
[2]
[2]
ADSR
ADSL
Counter/
Address
Register
Counter/
Address
Register
Address
Address
Decode
[2]
[2]
CNTENR
CNTENL
Decode
[2]
[2]
CNTRSTR
CNTRSTL
Mirror Reg
Mirror Reg
[2]
[2]
CLKL
CLKR[2]
[2]
CNTINTR
CNTINTL
TMS
TDI
TCK
Reset
Logic
Interrupt
Logic
Interrupt
Logic
JTAG
TDO
MRST
INTL
INTR
Notes:
1. CY7C0851V has 16 address bits instead of 17. CY7C0832V and CY7C0853V have 18 address bits instead of 17. CY7C083XV does not have B2 and B3
inputs. CY7C083XV does not have DQ18–DQ35 data bits. JTAG not implemented on CY7C083XV.
2. This feature is not available on the CY7C0853V.
Document #: 38-06059 Rev. *C
Page 2 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Pin Configurations
172-ball BGA
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DQ32L
DQ30L
CNTINTL
VSSQ
DQ13L
VDDQ
DQ11L
DQ11R
VDDQ
DQ13R
VSSQ
CNTINTR
DQ30R
DQ32R
A
B
C
D
E
F
A0L
NC
DQ33L
A1L
DQ29L
DQ31L
DQ35L
CE1L
A7L
DQ17L
DQ27L
DQ34L
B0L
DQ14L
INTL
DQ12L
DQ15L
DQ16L
VSSA
DQ9L
DQ10L
VSSQ
DQ9R
DQ10R
VSSQ
DQ12R
DQ15R
DQ16R
VDDA
DQ14R
INTR
DQ17R
DQ27R
DQ34R
B0R
DQ29R
DQ31R
DQ35R
CE1R
A7R
DQ33R
A1R
A0R
NC
A2L
A3L
DQ28L
VDDQ
VDDA
DQ28R
VDDQ
VSSA
A3R
A2R
A4L
A5L
A5R
A4R
VDD
A6L
B1L
B1R
A6R
VDD
OEL
B2L
B3L
CE0L
CE0R
B3R
B2R
OER
CY7C0851V
CY7C0852V
G
H
J
VSS
R/WL
A10L
A12L
A13L
A14L
DQ20L
DQ21L
A8L
CLKL
CLKR
A8R
R/WR
A10R
A12R
A13R
A14R
DQ20R
DQ21R
VSS
A9L
VSS
ADSL
VSSA
VDDQ
DQ25L
TDI
VDDA
VDDQ
DQ25R
TCK
ADSR
CNTRSTR
DQ26R
DQ18R
DQ6R
VSSQ
MRST
A15R
A9R
A11L
A15L
CNTRSTL
DQ26L
DQ18L
DQ6L
VDDA
DQ19L
DQ7L
DQ3L
VDDQ
VSSA
DQ19R
DQ7R
DQ3R
VDDQ
A11R
K
L
CNT/MSKL
A16L[3]
DQ24L
DQ23L
CNTENL
DQ22L
DQ8L
TDO
VSSQ
DQ2L
DQ0L
DQ1L
VSSQ
DQ2R
DQ0R
DQ1R
CNTENR
DQ22R
DQ8R
TMS
CNT/MSKR
A16R[3]
DQ24R
DQ23R
M
N
DQ5L
DQ4L
DQ5R
DQ4R
VSSQ
P
Note:
3. For CY7C0851V, pins M1 and M14 are NC.
Document #: 38-06059 Rev. *C
Page 3 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Pin Configurations (continued)
172-ball BGA
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DQ32L
DQ30L
NC
VSSQ
DQ13L
VDDQ
DQ12L
DQ15L
DQ16L
VSSA
DQ11L
DQ11R
VDDQ
DQ13R
VSSQ
NC
DQ30R DQ32R
A
B
C
D
E
F
A0L
A17L
A2L
DQ33L
A1L
DQ29L
DQ31L
DQ35L
VDD
DQ17L
DQ27L
DQ34L
B0L
DQ14L
INTL
DQ9L
DQ10L
VSSQ
DQ9R
DQ12R DQ14R DQ17R DQ29R DQ33R
A0R
A17R
A2R
DQ10R DQ15R
INTR
DQ27R DQ31R
A1R
A3R
A3L
DQ28L
VDDQ
VDDA
VSSQ
DQ16R DQ28R DQ34R DQ35R
A4L
A5L
VDDA
VDDQ
VSSA
B0R
B1R
VDD
A7R
A5R
A4R
VDD
OEL
A6L
A7L
B1L
A6R
VDD
OER
VSS
A9R
B2L
B3L
VSS
VSS
CLKR
VSS
VDD
B3R
B2R
CY7C0853V
G
H
J
VSS
R/WL
A10L
A12L
A13L
A14L
DQ20L
DQ21L
A8L
CLKL
VSS
A8R
R/WR
A10R
A12R
A13R
A14R
A9L
VSS
VSSA
VDDQ
DQ25L
TDI
VDDA
VDDQ
MRST
A15R
VSS
A11L
VDD
A16L
DQ24L
DQ23L
A15L
VSS
VDD
VDDA
DQ19L
DQ7L
DQ3L
VDDQ
VSSA
A11R
VDD
A16R
K
L
DQ26L
DQ18L
DQ6L
VSSQ
VSSQ
DQ2L
DQ0L
DQ1L
VSSQ
DQ2R
DQ0R
DQ1R
DQ19R DQ25R DQ26R
DQ22L
DQ8L
TDO
DQ7R
DQ3R
VDDQ
TCK
DQ18R DQ22R
M
N
P
DQ5L
DQ4L
DQ5R
DQ4R
DQ6R
VSSQ
DQ8R
TMS
DQ20R DQ24R
DQ21R DQ23R
Document #: 38-06059 Rev. *C
Page 4 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Pin Configurations (continued)
176-pin Thin Quad Flat Pack (TQFP)
Top View
DQ34R
DQ35R
NC
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
1
2
DQ34L
DQ35L
NC
3
A0R
4
A0L
A1R
5
A1L
A2R
6
A2L
A3R
VSS
VDD
7
A3L
VSS
VDD
8
9
A4R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
A4L
A5R
A5L
A6R
A6L
A7R
A7L
B0R
B0L
B1R
B1L
CE1R
B2R
CE1L
B2L
B3R
B3L
OER
OEL
CE0L
VDD
VDD
VSS
VSS
R/WL
CLKL
VSS
ADSL
CE0R
VDD
CY7C0851V
CY7C0852V
VDD
VSS
VSS
R/WR
CLKR
MRST
ADSR
CNTENR
CNTRSTR
CNT/MSKR
A8R
CNTENL
CNTRSTL
CNT/MSKL
A8L
A9R
A9L
A10R
A11R
A12R
VSS
A10L
98
A11L
97
A12L
96
VSS
VDD
95
VDD
A13R
A14R
A15R
A16R
DQ24R
DQ20R
94
A13L
93
A14L
92
A15L
91
A16L
90
DQ24L
DQ20L
89
Document #: 38-06059 Rev. *C
Page 5 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Pin Configurations (continued)
120-pin Thin Quad Flat Pack (TQFP)[4]
Top View
A2L
A3L
VSS
VDD
A4L
A5L
A6L
A7L
90
1
2
3
4
5
6
7
8
A2R
A3R
89
88
87
VSS
VDD
A4R
A5R
A6R
A7R
CE1R
B0R
B1R
OER
86
85
84
83
CE1L
82
81
9
B0L
10
B1L
80
79
78
11
OEL
12
CE0L
13
CE0R
VDD
VSS
VDD
14
VSS
77
76
CY7C0831V
CY7C0832V
15
R/WL
CLKL
75
74
73
16
17
18
R/WR
CLKR
MRST
ADSR
VSS
ADSL
72
71
19
20
CNTENL
CNTRSTL
CNTENR
70
69
68
67
21
22
23
24
CNTRSTR
CNT/MSKR
A8R
A9R
A10R
CNT/MSKL
A8L
A9L
A10L
66
65
25
26
A11L
A11R
A12R
VSS
A12L
64
63
62
61
27
28
29
30
VSS
VDD
VDD
A13R
A13L
Selection Guide
CY7C0853V
CY7C0851V
CY7C0852V
CY7C0853V[6]
-150
CY7C0853V
CY7C0853V
CY7C0851V
CY7C0852V
CY7C0853V
-100
CY7C0851V
CY7C0852V
CY7C0853V
-133
Unit
MHz
ns
fMAX
150
4.0
300
10
133
4.4
270
10
100
5
Max. Access Time (Clock to Data)
Typical Operating Current ICC
200
10
mA
mA
Typical Standby Current for ISB3
(Both Ports CMOS Level)[5]
Notes:
4. NC for CY7C0831V.
5. Not applicable for CY7C0853V.
6. For CY7C0853V all 150 MHz values are advance information.
Document #: 38-06059 Rev. *C
Page 6 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Pin Definitions
Left Port
Right Port
Description
[1]
[1]
A0L–A16L
A0R–A16R
Address Inputs.
ADSL
ADSR
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW
for the part using the externally supplied address on the address pins and for loading this
address into the burst address counter.
CE0L
CE0R
Active LOW Chip Enable Input.[2]
Active HIGH Chip Enable Input.[2]
CE1L
CE1R
CLKL
CLKR
Clock Signal. Maximum clock input rate is fMAX.
CNTENL
CNTENR
Counter Enable Input.[2] Asserting this signal LOW increments the burst address counter
of its respective port on each rising edge of CLK. The increment is disabled if ADS or
CNTRST are asserted LOW.
CNTRSTL
CNT/MSKL
CNTRSTR
CNT/MSKR
Counter Reset Input.[2] Asserting this signal LOW resets to zero the unmasked portion of
the burst address counter of its respective port. CNTRST is not disabled by asserting ADS
or CNTEN.
Address Counter Mask Register Enable Input.[2] Asserting this signal LOW enables
access to the mask register. When tied HIGH, the mask register is not accessible and the
address counter operations are enabled based on the status of the counter control signals.
[1]
[1]
DQ0L–DQ35L
DQ0R–DQ35R
Data Bus Input/Output.
OEL
OER
Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ
data pins during Read operations.
INTL
INTR
Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The
upper two memory locations can be used for message passing. INTL is asserted LOW when
the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a
port is deasserted HIGH when it reads the contents of its mailbox.
CNTINTL
R/WL
CNTINTR
R/WR
Counter Interrupt Output.[2] This pin is asserted LOW when the unmasked portion of the
counter is incremented to all “1s.”
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual
port memory array.
B0L–B3L
MRST
B0R–B3R
Byte Select Inputs. Asserting these signals enables Read and Write operations to the
corresponding bytes of the memory array.
Master Reset Input. MRST is an asynchronous input signal and affects both ports.
Asserting MRST LOW performs all of the reset functions as described in the text. A MRST
operation is required at power-up.
TMS
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK.
TDI
JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers.
JTAG Test Clock Input.
TCK
TDO
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally
three-stated except when captured data is shifted out of the JTAG TAP.
VSS
VDD
Ground Inputs.
Power Inputs.
Document #: 38-06059 Rev. *C
Page 7 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
order to set the INTR flag, a Write operation by the left port to
address 1FFFF will assert INTR LOW. At least one byte has to
be active for a Write to generate an interrupt. A valid Read of
the 1FFFF location by the right port will reset INTR HIGH. At
least one byte has to be active in order for a Read to reset the
interrupt. When one port Writes to the other port’s mailbox, the
INT of the port that the mailbox belongs to is asserted LOW.
The INT is reset when the owner (port) of the mailbox Reads
the contents of the mailbox. The interrupt flag is set in
a flow-thru mode (i.e., it follows the clock edge of the writing
port). Also, the flag is reset in a flow-thru mode (i.e., it follows
the clock edge of the reading port).
Master Reset
The CY7C0831V undergoes a complete reset by taking its
MRST input LOW. The MRST input can switch asynchro-
nously to the clocks. An MRST initializes the internal burst
counters to zero, and the counter mask registers to all ones
(completely unmasked). MRST also forces the Mailbox
Interrupt (INT) flags and the Counter Interrupt (CNTINT) flags
HIGH. MRST must be performed on the CY7C0831V after
power-up.
Mailbox Interrupts
Each port can read the other port’s mailbox without resetting
the interrupt. And each port can write to its own mailbox
without setting the interrupt. If an application does not require
message passing, INT pins should be left open.
The upper two memory locations may be used for message
passing and permit communications between ports. Table 2
shows the interrupt operation for both ports. The highest
memory location, 1FFFF is the mailbox for the right port and
1FFFE is the mailbox for the left port. Table 2 shows that in
Table 1. Address Counter and Counter-Mask Register Control Operation (Any Port)[2, 7, 8]
CLK MRST CNT/MSK CNTRST
ADS CNTEN
Operation
Description
X
L
X
X
X
X
Master Reset
Reset address counter to all 0s and mask
register to all 1s.
H
H
H
H
L
X
L
X
L
Counter Reset
Counter Load
Reset counter unmasked portion to all 0s.
H
Load counter with external address value
presented on address lines.
H
H
H
H
H
H
H
H
H
L
H
H
H
L
Counter
Readback
Read out counter internal value on
address lines.
Counter Increment Internally increment address counter
value.
H
Counter Hold
Constantly hold the address value for
multiple clock cycles.
H
H
L
L
L
X
L
X
L
Mask Reset
Mask Load
Reset mask register to all 1s.
H
Load mask register with value presented
on the address lines.
H
H
L
L
H
H
L
H
X
Mask Readback
Reserved
Read out mask register value on address
lines.
H
Operation undefined
Table 2. Interrupt Operation Example [1, 9, 10, 11]
Left Port
A0L–16L
Right Port
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
R/WL
CEL
L
INTL
X
R/WR
CER
X
A0R–16R
X
INTR
L
L
X
X
H
1FFFF
X
X
H
L
X
X
L
1FFFF
1FFFE
X
H
X
X
L
L
X
Reset Left INTL Flag
L
1FFFE
H
X
X
X
Notes:
7. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
8. Counter operation and mask register operation is independent of chip enables.
9. CE is internal signal. CE = LOW if CE0 = LOW and CE1 = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the
CLK and can be deasserted after that. Data will be out after the following CLK edge and will be three-stated after the next CLK edge.
10. OE is “Don’t Care” for mailbox operation.
11. At least one of B0, B1, B2, or B3 must be LOW.
Document #: 38-06059 Rev. *C
Page 8 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Mask Readback Operation
Address Counter and Mask Register
Operations [2, 12]
The internal value of the mask register can be read out on the
address lines. Readback is pipelined; the address will be valid
tCM2 after the next rising edge of the port’s clock. If mask
readback occurs while the port is enabled (CE0 LOW and CE1
HIGH), the data lines (DQs) will be three-stated. Figure 1
shows a block diagram of the operation.
Each port of the CY7C085XV/CY7C083XV has a program-
mable burst address counter. The burst counter contains three
17-bit registers: a counter register, a mask register, and a
mirror register.
The counter register contains the address used to access the
RAM array. It is changed only by the Counter Load, Increment,
Counter Reset, and by master reset (MRST) operations.
Mask Reset Operation
The mask register is reset to all “1s,” which unmasks every bit
of the counter. Master reset (MRST) also resets the mask
register to all “1s.”
The mask register value affects the Increment and Counter
Reset operations by preventing the corresponding bits of the
counter register from changing. It also affects the counter
interrupt output (CNTINT). The mask register is changed only
by the Mask Load and Mask Reset operations, and by the
MRST. The mask register defines the counting range of the
counter register. It divides the counter register into two
regions: zero or more “0s” in the most significant bits define
the masked region, one or more “1s” in the least significant bits
define the unmasked region. Bit 0 may also be “0,” masking
the least significant counter bit and causing the counter to
increment by two instead of one.
Counter Reset Operation
All unmasked bits of the counter and mirror registers are reset
to “0.” All masked bits remain unchanged. A Mask Reset
followed by a Counter Reset will reset the counter and mirror
registers to 00000, as will master reset (MRST).
Increment Operation
Once the address counter register is initially loaded with an
external address, the counter can internally increment the
address value, potentially addressing the entire memory array.
Only the unmasked bits of the counter register are incre-
mented. The corresponding bit in the mask register must be
a “1” for a counter bit to change. The counter register is incre-
mented by 1 if the least significant bit is unmasked, and by 2
if it is masked. If all unmasked bits are “1,” the next increment
will wrap the counter back to the initially loaded value. If an
Increment results in all the unmasked bits of the counter being
“1s,” a counter interrupt flag (CNTINT) is asserted. The next
Increment will return the counter register to its initial value,
which was stored in the mirror register. The counter address
can instead be forced to loop to 00000 by externally
connecting CNTINT to CNTRST.[13] An increment that results
in one or more of the unmasked bits of the counter being “0”
will de-assert the counter interrupt flag. The example in
Figure 2 shows the counter mask register loaded with a mask
value of 0003Fh unmasking the first 6 bits with bit “0” as the
LSB and bit “16” as the MSB. The maximum value the mask
register can be loaded with is 1FFFFh. Setting the mask
register to this value allows the counter to access the entire
memory space. The address counter is then loaded with an
initial value of 8h. The base address bits (in this case, the 6th
address through the 16th address) are loaded with an address
value but do not increment once the counter is configured for
increment operation. The counter address will start at address
8h. The counter will increment its internal address value till it
reaches the mask register value of 3Fh. The counter wraps
around the memory block to location 8h at the next count.
CNTINT is issued when the counter reaches its maximum
value.
The mirror register is used to reload the counter register on
increment operations (see “retransmit,” below). It always
contains the value last loaded into the counter register, and is
changed only by the Counter Load, and Counter Reset opera-
tions, and by the MRST.
Table 1 summarizes the operation of these registers and the
required input control signals. The MRST control signal is
asynchronous. All the other control signals in Table 1
(CNT/MSK, CNTRST, ADS, CNTEN) are synchronized to the
port’s CLK. All these counter and mask operations are
independent of the port’s chip enable inputs (CE0 and CE1).
Counter Load Operation
The address counter and mirror registers are both loaded with
the address value presented at the address lines. This value
ranges from 0 to 1FFFF.
Mask Load Operation
The mask register is loaded with the address value presented
at the address lines. This value ranges from 0 to 1FFFF,
although not all values permit correct increment operations.
Permitted values are of the form 2n – 1 or 2n – 2. From the
most significant bit to the least significant bit, permitted values
have zero or more “0s,” one or more “1s,” or one “0.” Thus
1FFFF, 003FE, and 00001 are permitted values, but 1F0FF,
003FC, and 00000 are not.
Counter Readback Operation
The internal value of the counter register can be read out on
the address lines. Readback is pipelined; the address will be
valid tCA2 after the next rising edge of the port’s clock. If
address readback occurs while the port is enabled (CE0 LOW
and CE1 HIGH), the data lines (DQs) will be three-stated.
Figure 1 shows a block diagram of the operation.
Hold Operation
The value of all three registers can be constantly maintained
unchanged for an unlimited number of clock cycles. Such
operation is useful in applications where wait states are
needed, or when address is available a few cycles ahead of
data in a shared bus interface.
Notes:
12. This section describes the CY7C0852V and CY7C0831V, which have 17 address bits and a maximum address value of 1FFFF. The CY7C0832V has 18 address
bits, register lengths of 18 bits, and a maximum address value of 3FFFF. The CY7C0851V has 16 address bits, register lengths of 16 bits, and a maximum
address value of FFFF.
13. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
Document #: 38-06059 Rev. *C
Page 9 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Counter Interrupt
the counter unmasked portion reaches its maximum value set
by the mask register, it wraps back to the initial value stored in
this “mirror register.” If the counter is continuously configured
in increment mode, it increments again to its maximum value
and wraps back to the value initially stored into the “mirror
register.” Thus, the repeated access of the same data is
allowed without the need for any external logic.
The counter interrupt (CNTINT) is asserted LOW when an
increment operation results in the unmasked portion of the
counter register being all “1s.” It is deasserted HIGH when an
Increment operation results in any other value. It is also
de-asserted by Counter Reset, Counter Load, Mask Reset
and Mask Load operations, and by MRST.
Counting by Two
Retransmit
When the least significant bit of the mask register is “0,” the
counter increments by two. This may be used to connect the
CY7C0851V/CY7C0852V as a 72-bit single port SRAM in
which the counter of one port counts even addresses and the
counter of the other port counts odd addresses. This even-odd
address scheme stores one half of the 72-bit data in even
memory locations, and the other half in odd memory locations.
Retransmit is a feature that allows the Read of a block of
memory more than once without the need to reload the initial
address. This eliminates the need for external logic to store
and route data. It also reduces the complexity of the system
design and saves board space. An internal “mirror register” is
used to store the initially loaded address counter value. When
Document #: 38-06059 Rev. *C
Page 10 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
CNT/MSK
CNTEN
ADS
Decode
Logic
CNTRST
MRST
Bidirectional
Address
Lines
Mask
Register
Counter/
Address
Register
Address
Decode
RAM
Array
CLK
Load/Increment
17
17
From
Address
Lines
Mirror
Counter
To Readback
and Address
Decode
1
0
1
0
From
Increment
Logic
Mask
17
Wrap
Register
17
17
17
Bit 0
From
Mask
From
+1
+2
Wrap
Detect
Counter
Wrap
To
1
0
17
1
0
Counter
Figure 1. Counter, Mask, and Mirror Logic Block Diagram[1]
Document #: 38-06059 Rev. *C
Page 11 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
CNTINT
H
Example:
Load
Counter-Mask
Register = 3F
0
0
0s
0
1
1
1
1
1
1
216 215
26 25 24 23 22 21 20
Unmasked Address
Mask
Register
bit-0
Masked Address
Load
Address
Counter = 8
H
L
X
X
Xs
Xs
Xs
X
0
0
1
0
0
0
216 215
26 25 24 23 22 21 20
Address
Counter
bit-0
Max
Address
Register
X
X
X
1
1
1
1
1
1
216 215
26 25 24 23 22 21 20
Max + 1
Address
Register
H
X
X
X
0
0
1
0
0
0
216 215
26 25 24 23 22 21 20
Figure 2. Programmable Counter-Mask Register Operation[1, 14]
IEEE 1149.1 Serial Boundary Scan (JTAG) [15]
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the MSB on any register.
The CY7C0851V/CY7C0852V/CY7C0853V incorporates an
IEEE 1149.1 serial boundary scan test access port (TAP). The
TAP controller functions in a manner that does not conflict with
the operation of other devices using 1149.1-compliant TAPs.
The TAP operates using JEDEC standard 3.3V I/O logic
levels. It is composed of three input connections and one
output connection required by the test logic defined by the
standard.
Test Data Out (TDO)
Disabling the JTAG Feature
The TDO output pin is used to serially clock data out from the
registers. The output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Diagram [FSM]). The output changes on the falling edge of
TCK. TDO is connected to the LSB of any register.
It is possible to operate the CY7C0851V/CY7C0852V/
CY7C0853V without using the JTAG feature. To disable the
TAP controller, TCK must be tied LOW (VSS) to prevent
clocking of the device. TDI and TMS are internally pulled up
and may be unconnected. They may alternatively be
connected to VDD through a pull-up resistor. TDO should be
left unconnected.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
Test Access Port–Test Clock (TCK)
CY7C0851V/CY7C0852V/CY7C0853V,
and
may
be
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
performed while the device is operating. An MRST must be
performed on the CY7C0851V/CY7C0852V/CY7C0853V
after power-up.
Test Mode Select (TMS)
Performing a Pause/Restart
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the
scan chain will output the next bit in the chain twice. For
example, if the value expected from the chain is 1010101, the
device will output a 11010101. This extra bit will cause some
testers to report an erroneous failure for the
CY7C0851/CY7C0852/CY7C0853 in a scan test. Therefore
the tester should be configured to never enter the PAUSE-DR
state.
Notes:
14. The “X” in this diagram represents the counter upper bits.
15. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance.
Document #: 38-06059 Rev. *C
Page 12 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
TAP Registers
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the
CY7C0851V/CY7C0852V/CY7C0853V test circuitry. Only one
register can be selected at a time through the instruction
registers. Data is serially loaded into the TDI pin on the rising
edge of TCK. Data is output on the TDO pin on the falling edge
of TCK.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST allows circuitry external to the CY7C0851V/
CY7C0852V/CY7C0853V package to be tested. Boundary-
scan register cells at output pins are used to apply test stimuli,
while those at input pins capture test results.
Instruction Register (IR)
Four-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in Figure 4, the JTAG/BIST
Controller Block Diagram. On power-up, the instruction
register is loaded with the IDCODE instruction. It is also loaded
with the IDCODE instruction if the controller is placed in a reset
state, as described in the previous section.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register on power-up or whenever
the TAP controller is given a test logic reset state. The
IDCODE value for the CY7C0851V is 0C001069h. The
IDCODE value for the CY7C0852V is 0C002069h. The
IDCODE value for the CY7C0853V is 0C002069h.
When the TAP controller is in the CaptureIR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Bypass Register (BYR)
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain devices. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
CY7C0851V/CY7C0852V/CY7C0853V with minimal delay.
The bypass register is set to “0” on the rising edge of TCK
following entry into the Capture-DR state, if the current
instruction causes the bypass register to be in the serial path
between TDI and TDO.
High-Z
The High-Z instruction causes the bypass register to be
connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all CY7C0851V/
CY7C0852V/CY7C0853V outputs into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions loaded into the
instruction register and the TAP controller in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
Boundary Scan Register (BSR)
The boundary scan register is connected to all the input and
output pins on the CY7C0851V/CY7C0852V/CY7C0853V,
except the MRST pin. The boundary scan register is loaded
with the contents of the CY7C0851V/CY7C0852V/
CY7C0853V input and output ring when the TAP controller is
in the Capture-DR state. It is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST and SAMPLE/PRELOAD instructions can be
used to capture the contents of the input and output ring.
The user must be aware that the TAP controller clock can only
operate at
a frequency up to 10 MHz, while the
CY7C0851V/CY7C0852V/CY7C0853V clock operates more
than an order of magnitude faster. Because there is a large
difference in the clock frequencies, it is possible that during the
Capture-DR state, an input or output will undergo a transition.
The TAP may then try to capture a signal while in transition
(metastable state). This will not harm the device, but there is
no guarantee as to the value that will be captured. Repeatable
results may not be possible.
Identification Register (IDR)
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
in the instruction register. The IDCODE is hardwired into the
CY7C0851V/CY7C0852V/CY7C0853V and can be shifted out
when the TAP controller is in the Shift-DR state. The ID
register has a vendor code and other information described in
the Identification Register Definitions table.
To guarantee that the boundary scan register will capture the
correct value of a signal, the CY7C0851V/CY7C0852V/
CY7C0853V signal must be stabilized long enough to meet the
TAP controller's capture set-up plus hold times. Once the data
is captured, it is possible to shift out the data by putting the TAP
into the Shift-DR state. This places the boundary scan register
between the TDI and TDO pins. If the TAP controller goes into
the Update-DR state, the sampled data will be updated.
TAP Instruction Set
Sixteen different instructions are possible with the four-bit
instruction register. All combinations are listed in Table 5.
Other code combinations are listed as RESERVED and should
not be used.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected on
a board.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
Document #: 38-06059 Rev. *C
Page 13 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
CLAMP
control. JTAG TAP pins (TDI, TMS, TDO, TCK), MRST, and all
power and ground pins have no scan cell. Other
CY7C0851V/CY7C0852V/CY7C0853V inputs have only the
data scan cell.
The optional CLAMP instruction allows the state of the signals
driven from CY7C0851V/CY7C0852V/CY7C0853V pins to be
determined from the boundary-scan register while the
BYPASS register is selected as the serial path between TDI
and TDO. CLAMP controls boundary cells to 1 or 0.
Active and Standby Supply Current[17]
When the instruction in the JTAG instruction register selects
the Boundary Scan Register (BSR) and the TAP controller is
in any state except TEST-LOGIC-RESET or RUN-TEST/IDLE,
then the device supply current (ICC or ISB1/2/3/4) will
increase. With the JTAG logic in this state, and both ports
inactive with CMOS input levels, it is possible for the supply
current to exceed the ISB3 value given in the Electrical
Characteristics section of this datasheet.
NBSRST
This is the Non-Boundary Scan Reset instruction. NBSRST
places the Bypass Register (BYR) between TDI and TDO
when selected. Its function is to reset every logic (similar to
MRST) except that it does not reset the JTAG logic.
Boundary Scan Cells (BSC)
Every CY7C0851V/CY7C0852V/CY7C0853V output has two
boundary scan cells; one for data, and one for three-state
TEST-LOGIC
RESET
1
0
1
1
1
SELECT
SELECT
RUN_TEST/
IDLE
0
DR-SCAN
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
1
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-IR
1
UPDATE-DR
1
0
0
Figure 3. TAP Controller State Diagram (FSM)[16]
Notes:
16. The “0”/”1” next to each state represents the value at TMS at the rising edge of CLK.
17. SB3 values only if JTAG pins are not active and mpdaster reset (MRST) not enabled.
I
Document #: 38-06059 Rev. *C
Page 14 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
0
Bypass Register (BYR)
3
2
1
0
Instruction Register (IR)
Selection
TDI
TDO
Circuitry
31 30 29
0
Identification Register (IDR)
(MUX)
n-1
0
Boundary Scan Register (BSR)
TCK
TMS
TAP
CONTROLLER
MRST
Figure 4. JTAG TAP Controller Block Diagram
Table 3. Identification Register Definitions
Instruction Field
Value
Description
Revision Number (31:28)
0h
Reserved for version number.
Cypress Device ID[18] (27:12) C002h
Defines Cypress part number for CY7C0852V.
Cypress JEDEC ID (11:1)
034h
1
Allows unique identification of CY7C0851V/CY7C0852V/
CY7C0853V vendor.
ID Register Presence (0)
Indicates the presence of an ID register.
Table 4. Scan Registers Sizes
Register Name
Instruction
Bit Size
4
1
Bypass
Identification
Boundary Scan
32
n
Note:
18. Cypress Device ID is C001h for Cypress part CY7C0851V.
Document #: 38-06059 Rev. *C
Page 15 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Table 5. Instruction Identification Codes
Instruction Code
EXTEST
Description
0000
1111
1011
0111
Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.
Places the BYR between TDI and TDO.
BYPASS
IDCODE
HIGHZ
Loads the IDR with the vendor ID code and places the register between TDI and TDO.
Places BYR between TDI and TDO. Forces all CY7C0851V/CY7C0852V/ CY7C0853V
output drivers to a High-Z state.
CLAMP
0100
Controls boundary to 1/0. Places BYR between TDI and TDO.
SAMPLE/PRELOAD 1000
Captures the input/output ring contents. Places BSR between TDI and TDO.
Resets the non-boundary scan logic. Places BYR between TDI and TDO.
NBSRST
1100
RESERVED
All other codes Other combinations are reserved. Do not use other than the above.
Document #: 38-06059 Rev. *C
Page 16 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
DC Input Voltage .............................. –0.5V to VDD + 0.5V[19]
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ..........................................> 2000V
(JEDEC JESD22-A114-2000B)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................ –65°C to + 150°C
Latch-up Current.....................................................> 200 mA
Ambient Temperature with
Power Applied............................................–55°C to + 125°C
Operating Range
Supply Voltage to Ground Potential.............. –0.5V to + 4.6V
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VDD
DC Voltage Applied to
Outputs in High-Z State .........................–0.5V to VDD + 0.5V
3.3V ± 165 mV
3.3V ± 165 mV
–40°C to +85°C
Electrical Characteristics Over the Operating Range
CY7C0851V/CY7C0852V/CY7C0853V[6]
CY7C0831V/CY7C0832V
-150
-133
-100
Parameter
VOH
VOL
Description
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
Output HIGH Voltage (VDD = Min., IOH= –4.0 mA) 2.4
2.4
2.4
V
V
Output LOW Voltage (VDD = Min., IOL= +4.0 mA)
0.4
0.8
0.4
0.4
VIH
Input HIGH Voltage
Input LOW Voltage
2.0
2.0
2.0
V
VIL
0.8
10
10
0.8
10
10
V
IOZ
Output Leakage Current
–10
10 –10
10 –10
1.0 –0.1
–10
–10
µA
µA
IIX1
Input Leakage Current Except TDI, TMS, MRST –10
IIX2
Input Leakage Current TDI, TMS, MRST
–0.1
1.0 –0.1
270 400
1.0 mA
200 310 mA
mA
ICC
Operating Current (VDD = Max.,
IOUT = 0 mA) Outputs Disabled
Com’l.
Indust.
Com’l.
Indust.
300 450
[5]
ISB1
Standby Current (Both Ports TTL
Level) CEL and CER ≥ VIH, f = fMAX
40 120
230 280
35
115
25 110 mA
mA
[5]
ISB2
Standby Current (One Port TTL Level) Com’l.
CEL | CER ≥ VIH, f = fMAX
220 250
10 75
180 230
145 190 mA
mA
Indust.
[17,5]
ISB3
Standby Current (Both Ports CMOS
Level)CEL and CER ≥ VDD – 0.2V, f = 0
Com’l.
Indust.
Com’l.
Indust.
10
75
10
75 mA
mA
[5]
ISB4
Standby Current (One Port CMOS
Level) CEL | CER ≥ VIH, f = fMAX
200 255
130 175 mA
mA
Shaded areas contain advance information.
Capacitance
Parameter
Description
Test Conditions
Max. (all) Max. (CY7C0853)
Unit
pF
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VDD = 3.3V
13
10
22
20
COUT
pF
Notes:
19. Pulse width < 20 ns.
20. (Internal I/O pad Capacitance = 10 pF) + AC Test Load.
21. External AC Test Load Capacitance = 10 pF.
22. Except JTAG signals (tr and tf < 10 ns [max.]).
Document #: 38-06059 Rev. *C
Page 17 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
AC Test Load and Waveforms
3.3V
Z = 50Ω
R = 50Ω
0
OUTPUT
R1 = 590 Ω
OUTPUT
C = 10 pF
C = 5 pF
R2 = 435 Ω
V
= 1.5V
TH
(a) Normal Load (Load 1)
(b) Three-state Delay (Load 2)
3.0V
90%
10%
90%
10%
ALL INPUT PULSES
Vss
< 2 ns
< 2 ns
Switching Characteristics Over the Operating Range
CY7C0851V/CY7C0852V/CY7C0853V[6]
CY7C0831V/CY7C0832V
-150
-133
-100
Parameter
fMAX2
tCYC2
tCH2
tCL2
tR
Description
Maximum Operating Frequency
Clock Cycle Time
Min. Max. Min. Max. Min. Max.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
150
133
100
6.7
2.7
2.7
7.5
3.0
3.0
10
4.0
4.0
Clock HIGH Time
Clock LOW Time
Clock Rise Time
2.0
2.0
2.0
2.0
3.0
3.0
tF
Clock Fall Time
tSA
Address Set-Up Time
Address Hold Time
Byte Select Set-Up Time
Byte Select Hold Time
Chip Enable Set-Up Time
Chip Enable Hold Time
R/W Set-Up Time
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.3
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
2.5
0.6
3.0
0.5
3.0
0.5
3.0
0.5
3.0
0.5
3.0
0.5
3.0
0.5
3.0
0.5
3.0
0.5
3.0
0.5
tHA
tSB
tHB
tSC
tHC
tSW
tHW
R/W Hold Time
tSD
Input Data Set-Up Time
Input Data Hold Time
ADS Set-Up Time
tHD
tSAD
tHAD
tSCN
tHCN
tSRST
tHRST
tSCM
tHCM
ADS Hold Time
CNTEN Set-Up Time
CNTEN Hold Time
CNTRST Set-Up Time
CNTRST Hold Time
CNT/MSK Set-Up Time
CNT/MSK Hold Time
Document #: 38-06059 Rev. *C
Page 18 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Switching Characteristics Over the Operating Range (continued)
CY7C0851V/CY7C0852V/CY7C0853V[6]
CY7C0831V/CY7C0832V
-150
-133
-100
Parameter
Description
Output Enable to Data Valid
Min. Max. Min. Max. Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOE
4.0
4.4
5.0
[23, 24]
tOLZ
OE to Low Z
0
0
0
0
0
0
[23, 24]
tOHZ
OE to High Z
4.0
4.0
4.0
4.0
4.4
4.4
4.4
4.4
5.0
5.0
5.0
5.0
tCD2
tCA2
tCM2
tDC
Clock to Data Valid
Clock to Counter Address Valid
Clock to Mask Register Readback Valid
Data Output Hold After Clock HIGH
Clock HIGH to Output High Z
Clock HIGH to Output Low Z
Clock to INT Set Time
1.0
0
1.0
0
1.0
0
[23, 24]
tCKHZ
4.0
4.0
6.7
6.7
5.0
5.0
4.4
4.4
7.5
7.5
5.7
5.7
5.0
5.0
10
[23, 24]
tCKLZ
1.0
0.5
0.5
0.5
0.5
1.0
0.5
0.5
0.5
0.5
1.0
0.5
0.5
0.5
0.5
tSINT
tRINT
Clock to INT Reset Time
Clock to CNTINT Set Time
Clock to CNTINT Reset time
10
tSCINT
tRCINT
7.5
7.5
Port to Port Delays
tCCS
Clock to Clock Skew
5.2
6.0
8.0
ns
Master Reset Timing
tRS
Master Reset Pulse Width
7.0
6.0
6.0
7.5
6.0
7.5
10
8.5
10
ns
ns
ns
ns
ns
tRSS
tRSR
tRSF
Master Reset Set-Up Time
Master Reset Recovery Time
Master Reset to Outputs Inactive
6.0
5.8
6.5
7.0
8.0
8.0
tRSCNTINT Master Reset to Counter Interrupt Flag Reset Time
JTAG Timing and Switching Waveforms
CY7C0852V
-150/133/100
Parameter
fJTAG
tTCYC
tTH
Description
Maximum JTAG TAP Controller Frequency
TCK Clock Cycle Time
Min.
Max.
10
Unit
MHz
ns
100
40
40
10
10
10
10
TCK Clock HIGH Time
ns
tTL
TCK Clock LOW Time
ns
tTMSS
tTMSH
tTDIS
TMS Set-Up to TCK Clock Rise
TMS Hold After TCK Clock Rise
TDI Set-Up to TCK Clock Rise
TDI Hold after TCK Clock Rise
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
ns
ns
ns
tTDIH
ns
tTDOV
30
ns
tTDOX
0
ns
Notes:
23. This parameter is guaranteed by design, but it is not production tested.
24. Test conditions used are Load 2.
Document #: 38-06059 Rev. *C
Page 19 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
tTH
tTL
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
tTDOV
Switching Waveforms
Master Reset
t
RS
MRST
t
RSF
ALL
ADDRESS/
DATA
LINES
t
RSS
t
RSR
ALL
OTHER
INPUTS
INACTIVE
ACTIVE
TMS
CNTINT
INT
TDO
Document #: 38-06059 Rev. *C
Page 20 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Switching Waveforms (continued)
Read Cycle[25, 26, 27, 28, 9]
t
CYC2
t
t
CL2
CH2
CLK
CE
t
t
t
t
HC
SC
HC
SC
t
SB
t
HB
B0–B3
R/W
t
t
t
t
SW
HW
SA
HA
ADDRESS
A
A
A
A
n+3
n
n+1
n+2
t
1 Latency
t
DC
CD2
DATA
OUT
Q
Q
Q
n+2
n
n+1
t
OHZ
t
t
CKLZ
OLZ
OE
tOE
Notes:
25. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
26. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
27. The output is disabled (high-impedance state) by CE = VIH following the next rising edge of the clock.
28. Addresses do not have to be accessed sequentially since ADS = CNTEN = VIL with CNT/MSK = VIH constantly loads the address on the rising edge of the CLK.
Numbers are for reference only.
Document #: 38-06059 Rev. *C
Page 21 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Switching Waveforms (continued)
Bank Select Read[29, 30]
t
CYC2
t
t
CL2
CH2
CLK
t
t
t
HA
SA
A
A
4
ADDRESS
A
5
A
A
A
3
(B1)
(B1)
0
1
2
t
HC
SC
CE
t
t
t
t
CKHZ
t
t
t
CD2
HC
CD2
CD2
CKHZ
SC
Q
Q
Q
3
DATA
1
0
OUT(B1)
t
t
HA
SA
t
t
t
CKLZ
DC
DC
A
A
4
A
5
ADDRESS
CE
A
0
A
A
3
(B2)
1
2
t
t
HC
SC
(B2)
t
t
t
CD2
t
CD2
CKHZ
t
SC
HC
DATA
OUT(B2)
Q
Q
4
2
t
t
CKLZ
CKLZ
Read-to-Write-to-Read (OE = LOW)[28, 31, 32, 33, 34]
t
CYC2
t
t
CL2
CH2
CLK
CE
t
t
HC
SC
t
t
HW
SW
R/W
t
t
HW
SW
A
A
A
A
A
A
n+4
n
n+1
n+2
n+2
n+3
ADDRESS
t
t
SD HD
t
t
HA
SA
D
n+2
DATA
IN
t
t
t
CD2
CD2
CKHZ
Q
Q
n
n+3
DATA
OUT
t
CKLZ
READ
NO OPERATION
WRITE
READ
Notes:
29. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C085XV device from this data sheet.
ADDRESS(B1) = ADDRESS(B2)
.
30. ADS = CNTEN= B0 – B3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
31. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
32. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
33. CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
34. CE0 = B0 – B3 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
Document #: 38-06059 Rev. *C
Page 22 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Switching Waveforms (continued)
Read-to-Write-to-Read (OE Controlled)[28, 31, 33, 34]
t
CYC2
t
t
CL2
CH2
CLK
CE
t
t
HC
SC
t
t
HW
SW
R/W
t
t
HW
SW
A
A
A
A
A
A
n+5
n
n+1
n+2
n+3
n+4
ADDRESS
t
t
HA
t
t
SA
SD HD
D
DATA
D
n+2
IN
n+3
t
t
CD2
CD2
DATA
Q
Q
n+4
OUT
n
t
OHZ
OE
READ
WRITE
READ
Read with Address Counter Advance[2, 33]
t
CYC2
t
t
CH2
CL2
CLK
t
t
HA
SA
ADDRESS
A
n
t
t
SAD
HAD
ADS
t
t
t
t
SAD
HAD
CNTEN
t
t
SCN
HCN
SCN
HCN
t
CD2
Q
Q
Q
Q
Q
n+2
DATA
Q
n+3
x–1
x
n
n+1
OUT
t
READ
DC
COUNTER HOLD
READ WITH COUNTER
READ WITH COUNTER
EXTERNAL
ADDRESS
Document #: 38-06059 Rev. *C
Page 23 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Switching Waveforms (continued)
Write with Address Counter Advance [2, 34]
t
CYC2
t
t
CH2
CL2
CLK
t
t
HA
SA
A
ADDRESS
n
INTERNAL
ADDRESS
A
A
A
A
A
n+4
n
n+1
n+2
n+3
t
t
HAD
SAD
ADS
CNTEN
t
t
HCN
SCN
D
D
D
D
D
D
n+4
DATA
n
n+1
n+1
n+2
n+3
IN
t
t
HD
SD
WRITE EXTERNAL
ADDRESS
WRITE WITH WRITE COUNTER
COUNTER HOLD
WRITE WITH COUNTER
Document #: 38-06059 Rev. *C
Page 24 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Switching Waveforms (continued)
Counter Reset [2, 35, 36]
t
CYC2
t
t
CL2
CH2
CLK
t
t
HA
SA
A
A
A
ADDRESS
p
m
n
INTERNAL
ADDRESS
A
A
A
n
1
0
A
m
p
x
t
t
HW
SW
R/W
ADS
CNTEN
CNTRST
t
t
HRST
SRST
t
t
HD
SD
DATA
D
IN
0
t
t
CD2
CD2
[48]
DATA
Q
Q
OUT
Q
1
0
n
t
CKLZ
READ
ADDRESS 1
READ
ADDRESS A
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS A
m
n
Notes:
35. CE0 = B0 – B3 = LOW; CE1 = MRST = CNT/MSK = HIGH.
36. No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.
Document #: 38-06059 Rev. *C
Page 25 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Switching Waveforms (continued)
Readback State of Address Counter or Mask Register[2, 37, 38, 39, 40]
t
CYC2
t
t
CL2
CH2
CLK
t
or t
CM2
t
t
CA2
SA
HA
EXTERNAL
ADDRESS
An*
A
n
A –A
0
16
INTERNAL
ADDRESS
An+4
An+1
An+2
An+3
An
t
t
SAD HAD
ADS
t
t
SCN
HCN
CNTEN
t
t
t
CD2
CKHZ
CKLZ
DATA
OUT
Q
n+1
Q
Q
Q
Q
Q
x-1
n+2
n+3
x-2
n
LOAD
EXTERNAL
ADDRESS
READBACK
INCREMENT
COUNTER
INTERNAL
ADDRESS
Notes:
37. CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
38. Address in output mode. Host must not be driving address bus after tCKLZ in next clock cycle.
39. Address in input mode. Host can drive address bus after tCKHZ
40. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.
.
Document #: 38-06059 Rev. *C
Page 26 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Switching Waveforms (continued)
Left_Port (L_Port) Write to Right_Port (R_Port) Read[41, 42, 43]
t
CYC2
t
t
CH2
CL2
CLK
L
t
HA
t
SA
L_PORT
ADDRESS
A
n
t
t
HW
SW
R/W
L
t
CKHZ
t
SD
t
HD
t
CKLZ
L_PORT
DATA
D
n
IN
t
CCS
t
CYC2
t
CL2
CLK
R
t
CH2
t
t
SA
HA
R_PORT
ADDRESS
A
n
R/W
R
t
CD2
R_PORT
DATA
Q
n
OUT
t
DC
Notes:
41. CE0 = OE = ADS = CNTEN = B0 – B3 = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
42. This timing is valid when one port is writing, and other port is reading the same location at the same time. If tCCS is violated, indeterminate data will be Read out.
43. If tCCS < minimum specified value, then R_Port will Read the most recent data (written by L_Port) only (2 * tCYC2 + tCD2) after the rising edge of R_Port's clock.
If tCCS > minimum specified value, then R_Port will Read the most recent data (written by L_Port) (tCYC2 + tCD2) after the rising edge of R_Port's clock.
Document #: 38-06059 Rev. *C
Page 27 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Switching Waveforms (continued)
Counter Interrupt and Retransmit[2, 44, 45, 46, 47, 48]
t
CYC2
t
t
CH2
CL2
CLK
tSCM
tHCM
CNT/MSK
ADS
CNTEN
COUNTER
INTERNAL
ADDRESS
1FFFE
1FFFC
Last_Loaded
1FFFD
1FFFF
Last_Loaded +1
t
t
RCINT
SCINT
CNTINT
Notes:
44. CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
45. CNTINT is always driven.
46. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value.
47. The mask register assumed to have the value of 1FFFFh.
48. Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.
Document #: 38-06059 Rev. *C
Page 28 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Switching Waveforms (continued)
MailBox Interrupt Timing[49, 50, 51, 52, 53]
tCYC2
tCH2
tCL2
CLKL
t
t
HA
SA
L_PORT
ADDRESS
A
1FFFF
A
A
A
n+3
n+1
n
n+2
t
SINT
t
INT
RINT
R
t
CYC2
t
t
CH2
CL2
CLK
R
t
t
HA
SA
R_PORT
ADDRESS
A
A
m+1
1FFFF
A
A
m+4
m
m+3
Table 6. Read/Write and Enable Operation (Any Port)[1, 7, 54, 55, 56]
Inputs
Outputs
DQ0 – DQ35
High-Z
OE
CLK
CE0
CE1
R/W
Operation
X
H
X
X
Deselected
Deselected
Write
X
X
L
X
L
L
L
L
X
L
High-Z
DIN
H
H
H
H
X
DOUT
High-Z
Read
H
X
Outputs Disabled
Notes:
49. CE0 = OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
50. Address “1FFFF” is the mailbox location for R_Port.
51. L_Port is configured for Write operation, and R_Port is configured for Read operation.
52. At least one byte enable (B0 – B3) is required to be active during interrupt operations.
53. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
54. OE is an asynchronous input signal.
55. When CE changes state, deselection and Read happen after one cycle of latency.
56. CE0 = OE = LOW; CE1 = R/W = HIGH.
Document #: 38-06059 Rev. *C
Page 29 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Ordering Information
256K × 36 (9M) 3.3V Synchronous CY7C0853V Dual-Port SRAM
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
150
133
100
CY7C0853V-150BBC
CY7C0853V-133BBC
CY7C0853V-100BBC
CY7C0853V-100BBI
BB172
BB172
BB172
BB172
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Industrial
256K
×
18 (4M) 3.3V Synchronous CY7C0832V Dual-Port SRAM
Package
Speed
(MHz)
Operating
Range
Ordering Code
CY7C0832V-150AC
CY7C0832V-133AC
CY7C0832V-100AC
CY7C0832V-100AI
Name
A120
A120
A120
A120
Package Type
150
133
100
120-pin Flat Pack 14 mm × 14 mm (TQFP)
120-pin Flat Pack 14 mm × 14 mm (TQFP)
120-pin Flat Pack 14 mm × 14 mm (TQFP)
120-pin Flat Pack 14 mm × 14 mm (TQFP)
Commercial
Commercial
Commercial
Industrial
128K
× 36 (4M) 3.3V Synchronous CY7C0852V Dual-Port SRAM
150
CY7C0852V-150BBC
CY7C0852V-150AC
CY7C0852V-133BBC
CY7C0852V-133BBI
CY7C0852V-133AC
CY7C0852V-100BBC
CY7C0852V-100AC
CY7C0852V-100BBI
CY7C0852V-100AI
BB172
A176
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial
176-pin Flat Pack 24 mm × 24 mm (TQFP) Commercial
133
100
BB172
BB172
A176
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Industrial
176-pin Flat Pack 24 mm × 24 mm (TQFP)
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial
176-pin Flat Pack 24 mm × 24 mm (TQFP) Commercial
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Industrial
176-pin Flat Pack 24 mm × 24 mm (TQFP) Industrial
Commercial
BB172
A176
BB172
A176
128K
×
18 (2M) 3.3V Synchronous CY7C0831V Dual-Port SRAM
Package
Speed
(MHz)
Operating
Ordering Code
CY7C0831V-150AC
CY7C0831V-133AC
CY7C0831V-100AC
Name
A120
A120
A120
Package Type
Range
Commercial
Commercial
Commercial
150
133
100
120-pin Flat Pack 14 mm × 14 mm (TQFP)
120-pin Flat Pack 14 mm × 14 mm (TQFP)
120-pin Flat Pack 14 mm × 14 mm (TQFP)
64K
× 36 (2M) 3.3V Synchronous CY7C0851V Dual-Port SRAM
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
CY7C0851V-150BBC
CY7C0851V-150AC
CY7C0851V-133BBC
CY7C0851V-133AC
CY7C0851V-133BBI
CY7C0851V-100BBC
CY7C0851V-100AC
Package Type
150
BB172
A176
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial
176-pin Flat Pack 24 mm × 24 mm (TQFP) Commercial
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial
176-pin Flat Pack 24 mm × 24 mm (TQFP) Commercial
133
BB172
A176
BB172
BB172
A176
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Industrial
172-ball Grid Array 15 mm × 15 mm with 1.0 mm pitch (BGA) Commercial
100
176-pin Flat Pack 24 mm × 24 mm (TQFP)
Commercial
Shaded areas contain advance information.
Document #: 38-06059 Rev. *C
Page 30 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Package Diagrams
120-pin thin Quad Flatpack (14 × 14 × 1.4 mm) A120
51-85100
176-lead Thin Quad Flat Pack (24 × 24 × 1.4 mm) A176
51-85132
Document #: 38-06059 Rev. *C
Page 31 of 33
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Package Diagrams (continued)
172-ball BGA BB172
51-85114-*A
FLEx36 is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trade-
marks of their respective holders.
Document #: 38-06059 Rev. *C
Page 32 of 33
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C0851V/CY7C0852V/CY7C0853V
PRELIMINARY
CY7C0831V/CY7C0832V
Document Title: CY7C0851V/CY7C0852V/CY7C0853V/CY7C0831V/CY7C0832V 3.3V 64K/128K/256K x 36 and
128K/256K x 18 Synchronous Dual-Port RAM
Document Number: 38-06059
Issue
Date
Orig. of
REV.
**
ECN NO.
111473
Change Description of Change
11/27/01
12/21/01
DSG
JFU
Change from Spec number: 38-01056 to 38-06059
*A
111942
Updated capacitance values
Updated switching parameters and ISB3
Updated “Read-to-Write-to-Read (OE Controlled)” waveform
Revised static discharge voltage
Revised footnote regarding ISB3
*B
*C
113741
114704
04/02/02
04/24/02
KRE
KRE
Updated Isb values
Updated ESD voltage
Corrected 0853 pins L3 and L12
Added discussion of Pause/Restart for JTAG boundary scan
Document #: 38-06059 Rev. *C
Page 33 of 33
相关型号：
CY7C0852AV-133AXC
FLEx36⢠3.3 V 32 K / 64 K / 128 K / 256 K à 36 Synchronous Dual-Port RAM
CYPRESS
CY7C0852AV-133AXI
FLEx36⢠3.3 V 32 K / 64 K / 128 K / 256 K à 36 Synchronous Dual-Port RAM
CYPRESS
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