CY7C0852V25 [CYPRESS]
SRAM;
CYPRESS 
851V25
52V25
CY7C0851V25
CY7C0852V25
ADVANCE INFORMATION
2.5V 64K/128K x 36
Sync Dual-Port Static RAM
Features
Functional Description
• True Dual-Ported memory cellsthatallow simultaneous
access of the same memory location
• Sync. Pipelined 4.5 Megabit devices
—64K x 36 organization (CY7C0851V25)
The CY7C0851V25/CY7C0852V25 is a 4.5-Megabit pipelined
synchronous true dual-port Static RAM. This is a high-speed,
low-power 2.5V CMOS dual-port static RAM. Two ports are
provided, permitting independent, simultaneous access for
reads from any location in memory. A particular port can write
to a certain location while the other port is reading that location
simultaneously. The result of writing to the same location by
more than one port at the same time is undefined. Registers
on control, address, and data lines allow for minimal set-up
and hold time.
—128K x 36 organization (CY7C0852V25)
• Pipelined output mode allows fast 100-MHz operation
• 0.18-micron CMOS for optimum speed/power
• High-speed clock to data access: 5 ns (max.)
• 2.5V Low operating power
During a read operation, data is registered for decreased cycle
—Active = 150 mA (typical)
time. Clock to data valid t
= 5 ns. Each port contains a burst
CD2
—Standby = 10 mA (typical)
counter on the input address register. After externally loading
the counter with the initial address the counter will self-incre-
ment the address internally (more details to follow). The inter-
nal write pulse width is independent of the duration of the R/W
input signal. The internal write pulse is self-timed to allow the
shortest possible cycle times.
• HSTL class 1 I/O (0.75 Vref)
• Counter wraparound control
—Internal mask register controls counter wraparound
—Counter-Interrupt flags to indicate wraparound
—Memory Block Retransmit Operation
• Counter readback on address lines
• Mask register readback on address lines
• Interrupt flags for message passing
• Global Master reset
• Width and Depth expansion capabilities
• Dual Chip Enables on both ports for easy depth expan-
sion
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power consump-
tion. One cycle is required with chip enables asserted to reac-
tivate the outputs.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded when the port’s address strobe
(ADS) and (CNTEN) signals are LOW. When the port’s counter
enable (CNTEN) is asserted and the ADS is deasserted, the
address counter will increment on each LOW to HIGH transi-
tion of that port’s clock signal. This will read/write one word
from/into each successive address location until CNTEN is
deasserted. The counter can address the entire memory array
and will loop back to the start. Counter reset (CNTRST) is used
to reset the unmasked portion of the burst counter to 0s. A
counter-mask register is used to control the counter wrap. The
counter and mask register operations are described in more
detail in the following sections.
• Separate byte enables on both ports
• Commercial and Industrial temperature ranges
• IEEE 1149.1 JTAG boundary scan
• 172-ball BGA (1-mm pitch) (15 mm x 15 mm x 0.51 mm)
New features added to the CY7C0851V25/CY7C0852V25 in-
clude: readback of burst-counter internal address value on ad-
dress lines, counter-mask registers to control the counter
wrap-around and counter interrupt (CNTINT) flags, readback
of mask register value on address lines, retransmit functional-
ity, interrupt flags for message passing, JTAG for boundary
scan, and asynchronous Master Reset.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
October 17, 2000
CY7C0851V25
CY7C0852V25
ADVANCE INFORMATION
Logic Block Diagram
OE
R/W
OE
R/W
L
R
R
L
B0
B1
B2
B3
B0
B1
B2
B3
L
L
L
L
R
R
R
R
CE
CE
CE
CE
0L
0R
1R
1L
9
9
9
9
DQ27L–DQ35L
DQ18L–DQ26L
DQ9L–DQ17L
DQ0L–DQ8L
DQ27R–DQ35R
DQ18R–DQ26R
DQ9R–DQ17R
DQ0R–DQ8R
I/O
Control
I/O
Control
9
9
9
9
Addr.
Read
Back
Addr.
Read
Back
True
Dual-Ported
RAM Array
17
17
A
–A
16L
A
–A
16R
0L
0R
Mask Register
Mask Register
CNT/MSK
ADS
CNT/MSK
R
R
R
L
ADS
Counter/
Address
Register
Counter/
Address
Register
L
Address
Address
CNTEN
CNTRST
CLK
CNTEN
L
Decode
Decode
CNTRST
R
R
L
Mirror Reg
Mirror Reg
CLK
L
CNTINT
CNTINT
R
L
TMS
TDI
TCK
Reset
Logic
Interrupt
Interrupt
Logic
JTAG
TDO
MRST
INT
INT
R
L
Logic
2
CY7C0851V25
CY7C0852V25
ADVANCE INFORMATION
Pin Configuration
172-Ball Grid Array (BGA)
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DQ32L
DQ30L
VSSQ
DQ13L
VDDQ
DQ11L
DQ11R
VDDQ
DQ13R
VSSQ
DQ30R
DQ32R
CNTINTL
CNTINTR
A
B
C
D
E
F
A0L
VREFL
A2L
DQ33L
A1L
DQ29
DQ31L
DQ35L
CE1L
A7L
DQ17L
DQ27L
DQ34L
B0L
DQ14L
INTL
DQ12L
DQ15L
DQ16L
VSSA
DQ9L
DQ10L
VSSQ
DQ9R
DQ10R
VSSQ
DQ12R
DQ15R
DQ16R
VDDA
DQ14R
INTR
DQ17R
DQ27R
DQ34R
B0R
DQ29R
DQ31R
DQ35R
CE1R
A7R
DQ33R
A1R
A0R
VREFR
A2R
A3L
DQ28L
VDDQ
VDDA
DQ28R
VDDQ
VSSA
A3R
A4L
A5L
A5R
A4R
VDD
OEL
VSS
A9L
A6L
B1L
A6R
VDD
OER
VSS
B1R
B2L
B3L
CE0L
CE0R
B3R
B2R
G
H
J
R/WL
A10L
A12L
A13L
A8L
CLKL
CLKR
A8R
R/WR
A10R
A12R
A13R
VSS
ADSL
ADSR
A9R
VSSA
VDDQ
DQ25L
VDDA
VDDQ
DQ25R
MRST
A15R
A11L
CNTRSTL
DQ26L
CNTRSTR
A11R
A15L
CNTENL
VDDA
VSSA
K
DQ19L
VSSQ
VSSQ
DQ19R
DQ26R CNTENR
CNT/
MSKR
CNT/MSKL
L
M
N
P
A14L
DQ20L
DQ21L
DQ22L
DQ8L
TDO
DQ18L
DQ6L
VSSQ
DQ7L
DQ3L
VDDQ
DQ2L
DQ0L
DQ1L
DQ2R
DQ0R
DQ1R
DQ7R
DQ3R
VDDQ
DQ18R
DQ6R
VSSQ
DQ22R
DQ8R
TMS
A14R
A16L
DQO24L
DQ23L
TDI
TCK
DQ5R
DQ4R
A16R
DQ5L
DQ4L
DQ20R
DQ21R
DQ24R
DQ23R
3
CY7C0851V25
CY7C0852V25
ADVANCE INFORMATION
Selection Guide
CY7C0851V25/CY7C0852V25
-100
f
(MHz)
100
5
MAX
Max. Access Time (ns) (Clock to Data)
Typical Operating Current I (mA)
150
CC
Typical Standby Current for I
Typical Standby Current for I
(mA) (Both Ports TTL Level)
(mA) (Both Ports CMOS Level)
SB1
SB3
10
4
CY7C0851V25
CY7C0852V25
ADVANCE INFORMATION
Pin Definitions
Left Port
–A
Right Port
–A
Description
A
A
Address Inputs.
0L
16L
0R
16R
ADS
ADS
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
assert the part using the externally supplied address on Address Pins and to load this address
into the Burst Address Counter.
L
R
CE0
CE1
CLK
CE0
CE1
CLK
Active Low Chip Enable Input.
Active High Chip Enable Input.
L
L
L
R
R
R
Clock Signal. Maximum clock input rate is f
.
MAX
CNTEN
CNTEN
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. Increment is disabled if ADS or CNTRST are
asserted LOW.
L
R
CNTRST
CNTRST
Counter Reset Input. Asserting this signal LOW resets to zero the unmasked portion of the
burst address counter of its respective port. CNTRST is not disabled by asserting ADS or
CNTEN.
L
R
CNT/MSK
CNT/MSK
Address Counter Mask Register Enable Input. Asserting this signal LOW enables the access
to the mask register. When tied HIGH the mask register is not accessible and the address
counter operations are enabled based on the status of the counter control signals.
L
R
DQ –DQ
DQ –DQ
35R
Data Bus Input/Output.
0L
35L
0R
OE
OE
Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ data
pins during read operations.
L
R
INT
INT
Mailbox Interrupt Flag Output. Mailbox permits communications between ports. The upper two
L
R
memory locations can be used for message passing. INT is asserted LOW when right port
L
writes to the mailbox location of left port and vice versa. Interrupt to a port is deasserted HIGH
when it reads the contents of its mailbox.
CNTINT
CNTINT
Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of the counter
L
R
is incremented to all “1s.”
R/W
R/W
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to read from the dual-port
memory array.
L
R
B
–B
B
–B
3L
Byte Select Inputs. Asserting these signals enables read and write operations to the corre-
sponding bytes of the memory array.
0L
3L
0L
MRST
TMS
Master Reset Input. MRST is an asynchronous input and affects both ports. Asserting MRST
LOW performs all of the reset functions as described in the text. A MRST operation is required
at power-up.
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State ma-
chine transitions occur on the rising edge of TCK.
TDI
JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers.
JTAG Test Clock Input.
TCK
TDO
JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally
three-stated except when captured data is shifted out of the JTAG TAP.
V
V
, V
, V
Ground Inputs (A: for address lines, Q: for data lines).
Power Inputs (A: for address lines, Q: for data lines).
SS SSA
SSQ
, V
, V
DDQ
DD DDA
5
CY7C0851V25
CY7C0852V25
ADVANCE INFORMATION
Ordering Information
64K x 36 (2 Meg) 2.5V Synchronous CY7C0851V25 Dual Port SRAM
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
Package Type
100
CY7C0851V25-100BBC
BB172
172-Ball Grid Array (BGA)
Commercial
128K x 36 (4 Meg) 2.5V Synchronous CY7C0852V25 Dual Port SRAM
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
CY7C0852V25-100BBC
CY7C0852V25-100BBI
100
BB172
BB172
172-Ball Grid Array (BGA)
172-Ball Grid Array (BGA)
Commercial
Industrial
Shaded areas contain advanced information
Document #: 38-01056-**
Package Diagram
172-Ball FBGA BB172
51-85114
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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