CY7C09349V-9AC [CYPRESS]
Dual-Port SRAM, 4KX18, 9ns, CMOS, PQFP100, PLASTIC, TQFP-100;
| 型号： | CY7C09349V-9AC |
| 厂家： | 
CYPRESS |
| 描述： | Dual-Port SRAM, 4KX18, 9ns, CMOS, PQFP100, PLASTIC, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总17页 (文件大小：348K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1
CY7C09349V
CY7C09359V
PRELIMINARY
3.3V 4K/8K x 18
Synchronous Dual-Port Static RAM
[1, 2]
• High-speed clock to data access 7.5
• 3.3V Low operating power
/9/12 ns (max.)
Features
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
— Active = 135 mA (typical)
— Standby = 10 µA (typical)
• Two Flow-Through/Pipelined devices
— 4K x 18 organization (CY7C09349V)
— 8K x 18 organization (CY7C09359V)
• Three Modes
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
— Shorten cycle times
— Minimize bus noise
— Flow-Through
— Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Upper and lower byte controls for bus matching
• Automatic power-down
— Pipelined
— Burst
• Pipelinedoutputmodeonboth portsallowsfast83-MHz
operation
• Commercial and Industrial temperature ranges
• 0.35-micron CMOS for optimum speed/power
Available in 100-pin TQFP
•
v
Logic Block Diagram
R/W
R/W
UB
L
R
R
UB
L
CE
CE
CE
CE
0L
1L
0R
1R
1
1
0
0
0/1
0/1
LB
LB
L
R
OE
OE
L
R
1b 0b 1a 0a
0a 1a 0b 1b
a b 0/1
0/1
b
a
FT/Pipe
FT/Pipe
L
R
9
9
9
9
I/O –I/O
I/O –I/O
9R 17R
9L
17L
8L
I/O
Control
I/O
Control
I/O –I/O
I/O –I/O
0L
0R
8R
12/13
12/13
[3]
A
–A[3]
A
–A
0L
11/12L
0R 11/12R
Counter/
Address
Register
Decode
Counter/
Address
Register
Decode
CLK
CLK
ADS
L
R
R
R
R
True Dual-Ported
RAM Array
ADS
L
CNTEN
CNTEN
L
CNTRST
CNTRST
L
Notes:
1. Call for availability
2. See Page 6 for Load Conditions.
3. A0–A11 for 4K; A0–A12 for 8K devices.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
October 14, 1999
CY7C09349V
CY7C09359V
PRELIMINARY
A HIGH on CE or LOW on CE for one clock cycle will power
Functional Description
0
1
down the internal circuitry to reduce the static power consump-
tion. The use of multiple Chip Enables allows easier banking
of multiple chips for depth expansion configurations. In the
The CY7C09349V and CY7C09359V are high-speed 3.3V
synchronous CMOS 4K and 8K x 18 dual-port static RAMs.
Two ports are provided, permitting independent, simultaneous
pipelined mode, one cycle is required with CE LOW and CE
0
1
[4]
access for reads and writes to any location in memory. Reg-
HIGH to reactivate the outputs.
isters on control, address, and data lines allow for minimal set-
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW-to-HIGH
transition of that port’s clock signal. This will read/write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array and will loop back to the start. Counter Reset (CNTRST)
is used to reset the burst counter.
up and hold times. In pipelined output mode, data is registered
[1]
for decreased cycle time. Clock to data valid t
= 7.5 ns
CD2
(pipelined). Flow-through mode can also be used to bypass
the pipelined output register to eliminate access latency. In
flow-through mode data will be available t
= 18 ns after the
CD1
address is clocked into the device. Pipelined output or flow-
through mode is selected via the FT/Pipe pin.
Each port contains a burst counter on the input address regis-
ter. The internal write pulse width is independent of the LOW-
to-HIGH transition of the clock signal. The internal write pulse
is self-timed to allow the shortest possible cycle times.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Note:
4. When simultaneously writing to the same location, final value cannot be guaranteed.
2
CY7C09349V
CY7C09359V
PRELIMINARY
Pin Configuration
100-Pin TQFP (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
A10L
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
A8R
2
A9R
A11L
3
A10R
A11R
[Note 5] A12L
NC
4
5
A12R
NC
[Note 5]
NC
6
NC
7
NC
LBL
8
NC
UBL
9
LBR
UBR
CE0R
CE1R
CE0L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CE1L
CY7C09359V (8K x 18)
CY7C09349V (4K x 18)
CNTRSTL
R/WL
CNTRSTR
R/WR
OEL
VCC
GND
FT/PIPEL
I/O17L
I/O16L
GND
60
59
58
57
56
55
OER
FT/PIPER
I/O17R
GND
I/O15L
I/O14L
I/O13L
1/012L
I/O16R
I/O15R
54
53
I/O14R
I/O13R
I/O11L
I/O10L
24
25
52
51
I/O12R
I/O11R
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Selection Guide
CY7C09349V
CY7C09359V
CY7C09349V
CY7C09359V
-9
CY7C09349V
CY7C09359V
-12
[1, 2]
-7
f
(MHz) (Pipelined)
83
7.5
67
9
50
12
MAX2
Max Access Time (ns) (Clock to Data, Pipelined)
Typical Operating Current I (mA)
155
25
135
20
115
20
CC
Typical Standby Current for I
(mA) (Both Ports TTL Level)
SB1
Typical Standby Current for I
(µA) (Both Ports CMOS Level)
10 µA
10 µA
10 µA
SB3
Shaded areas contain advance information.
Note:
5. This pin is NC for CY7C09349V.
3
CY7C09349V
CY7C09359V
PRELIMINARY
Pin Definitions
Left Port
–A
Right Port
A –A
0R
Description
Address Inputs (A –A for 4K, A –A for 8K devices).
A
0L
12L
12R
0
11
0
12
ADS
ADS
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW during
normal read or write transactions. Asserting this signal LOW also loads the burst address
counter with data present on the I/O pins.
L
R
CE ,CE
CE ,CE
Chip Enable Input. To select either the left or right port, both CE AND CE must be asserted
0 1
0L
1L
0R
1R
to their active states (CE ≤ V and CE ≥ V ).
0
IL
1
IH
CLK
CLK
Clock Signal. This input can be free running or strobed. Maximum clock input rate is f
.
L
R
MAX
CNTEN
CNTEN
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
L
R
CNTRST
CNTRST
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respec-
tive port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
L
R
I/O –I/O
I/O –I/O
Data Bus Input/Output (I/O –I/O for x16 devices).
0 15
0L
17L
0R
17R
LB
LB
Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the
lower byte (I/O –I/O for x18, I/O –I/O for x16) of the memory array. For read operations both
L
R
0
8
0
7
the LB and OE signals must be asserted to drive output data on the lower byte of the data pins.
UB
UB
R
Upper Byte Select Input. Same function as LB, but to the upper byte (I/O –I/O ).
L
8/9L
15/17L
OE
OE
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
L
R
R/W
R/W
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.
For read operations, assert this pin HIGH.
L
R
FT/PIPE
FT/PIPE
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
For pipelined mode operation, assert this pin HIGH.
L
R
GND
NC
Ground Input.
No Connect.
Power Input.
V
CC
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........................................... >2001V
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature ................................. –65°C to +150°C
Operating Range
Ambient Temperature with
Ambient
Power Applied.............................................–55°C to +125°C
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
V
CC
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
3.3V ± 300 mV
3.3V ± 300 mV
DC Voltage Applied to
Outputs in High Z State ...........................–0.5V to V +0.5V
CC
Shaded areas contain advance information.
DC Input Voltage......................................–0.5V to V +0.5V
CC
4
CY7C09349V
CY7C09359V
PRELIMINARY
Electrical Characteristics Over the Operating Range
CY7C09349V
CY7C09359V
[1, 2]
-7
-9
-12
Parameter
Description
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
V
V
V
V
Output HIGH Voltage (V = Min., I = –4.0 mA) 2.4
2.4
2.0
–10
2.4
2.0
–10
V
V
OH
OL
IH
CC
OH
Output LOW Voltage (V = Min., I = +4.0 mA)
0.4
0.4
0.4
CC
OH
Input HIGH Voltage
Input LOW Voltage
2.0
V
0.8
10
0.8
10
0.8
10
V
IL
I
I
Output Leakage Current
Operating Current (V = Max.,
–10
µA
OZ
Com’l.
Indust.
Com’l.
Indust.
Com’l.
Indust.
Com’l.
Indust.
Com’l.
Indust.
155 275
135 230
185 300
115 180 mA
155 250 mA
CC
CC
I
= 0 mA) Outputs Disabled
OUT
I
I
I
I
Standby Current (Both Ports TTL
25
85
20
35
75
85
20
30
70 mA
80 mA
SB1
SB2
SB3
SB4
[6]
Level) CE & CE ≥ V , f =f
L
R
IH
MAX
[6]
Standby Current (One Port TTL Level)
CE | CE ≥ V , f =f
105 165
95 155
106 165
10 250
10 250
85 115
95 125
85 140 mA
95 150 mA
10 250 µA
10 250 µA
75 100 mA
85 110 mA
L
R
IH
MAX
Standby Current (Both Ports CMOS
10
95
250
125
[6]
Level) CE & CE ≥ V – 0.2V, f = 0
L
R
CC
Standby Current (One Port CMOS
[6]
Level) CE | CE ≥ V , f = f
L
R
IH
MAX
Shaded areas contain advance information.
Capacitance
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
pF
C
C
Input Capacitance
Output Capacitance
10
10
IN
A
V
= 3.3V
CC
pF
OUT
Note:
6. CEL and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH).
5
CY7C09349V
CY7C09359V
PRELIMINARY
AC Test Loads
3.3V
3.3V
R
TH
= 250
Ω
R1 = 590
Ω
Ω
OUTPUT
C = 30 pF
OUTPUT
R1 = 590
Ω
OUTPUT
C = 5 pF
C = 30 pF
R2 = 435
R2 = 435
Ω
V
TH
= 1.4V
(a) Normal Load (Load 1)
(c)Three-State Delay(Load 2)
(Used for t , t , & t
(b) Thévenin Equivalent (Load 1)
CKLZ OLZ
OHZ
including scope and jig)
AC Test Loads (Applicable to -7 only)[7]
ALL INPUTPULSES
Z = 50
Ω
R = 50
Ω
0
OUTPUT
3.0V
GND
90%
10%
90%
C
10%
3 ns
3 ns
≤
V
TH
= 1.4V
≤
(a) Load 1 (-7 only)
1 .00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.1 0
0.00
1 0
1 5
20
25
30
35
Capacitance (pF)
(b) Load Derating Curve
Note:
7. Test Conditions: C = 10 pF.
6
CY7C09349V
CY7C09359V
PRELIMINARY
Switching Characteristics Over the Operating Range
CY7C09349V
CY7C09359V
[1, 2]
-7
Min.
-9
-12
Parameter
Description
Flow-Through
Max.
Min.
Max.
40
Min.
Max.
33
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
f
f
f
45
83
MAX1
MAX2
CYC1
CYC2
CH1
CL1
CH2
CL2
R
Max
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Pipelined
67
50
Max
Clock Cycle Time - Flow-Through
Clock Cycle Time - Pipelined
Clock HIGH Time - Flow-Through
Clock LOW Time - Flow-Through
Clock HIGH Time - Pipelined
Clock LOW Time - Pipelined
Clock Rise Time
22
12
7.5
7.5
5
25
15
12
12
6
30
20
12
12
8
5
6
8
3
3
3
3
3
3
Clock Fall Time
F
Address Set-up Time
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
1
SA
Address Hold Time
HA
Chip Enable Set-up Time
Chip Enable Hold Time
R/W Set-up Time
SC
HC
SW
R/W Hold Time
HW
Input Data Set-up Time
Input Data Hold Time
SD
HD
ADS Set-up Time
SAD
HAD
SCN
HCN
SRST
HRST
OE
ADS Hold Time
CNTEN Set-up Time
CNTEN Hold Time
CNTRST Set-up Time
CNTRST Hold Time
Output Enable to Data Valid
OE to Low Z
9
10
12
2
1
2
1
2
1
OLZ
OHZ
CD1
CD2
DC
OE to High Z
7
7
20
9
7
Clock to Data Valid - Flow-Through
Clock to Data Valid - Pipelined
Data Output Hold After Clock HIGH
Clock HIGH to Output High Z
Clock HIGH to Output Low Z
18
7.5
25
12
2
2
2
2
2
2
2
2
2
9
9
9
CKHZ
CKLZ
Port to Port Delays
t
t
Write Port Clock HIGH to Read Data Delay
Clock to Clock Set-up Time
35
10
40
15
40
15
ns
ns
CWDD
CCS
Shaded areas contain advance information.
7
CY7C09349V
CY7C09359V
PRELIMINARY
Switching Waveforms
Read Cycle for Flow-Through Output (FT/PIPE = V )
[8, 9, 10, 11]
IL
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
tSC
tHC
CE1
R/W
tSW
tSA
tHW
tHA
An
An+1
An+2
An+3
ADDRESS
DATAOUT
tCKHZ
Qn+2
tDC
tDC
Qn
tCD1
Qn+1
tCKLZ
tOHZ
tOLZ
OE
tOE
[8, 9, 10, 11]
Read Cycle for Pipelined Operation (FT/PIPE = V )
IH
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
tSC
tHC
CE1
R/W
tSW
tSA
tHW
tHA
ADDRESS
DATAOUT
An
An+1
An+2
An+3
tDC
1 Latency
tCD2
Qn
Qn+1
tOHZ
Qn+2
tCKLZ
tOLZ
OE
tOE
Notes:
8. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
9. ADS = VIL, CNTEN and CNTRST = VIH
10. The output is disabled (high-impedance state) by CE0=VIH or CE1 = VIL following the next rising edge of the clock.
.
11. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
8
CY7C09349V
CY7C09359V
PRELIMINARY
Switching Waveforms (continued)
[12, 13]
Bank Select Pipelined Read
tCYC2
tCH2
tCL2
CLKL
tHA
tSA
A3
ADDRESS(B1)
A4
A5
A0
A1
A2
tHC
tSC
CE0(B1)
tCD2
tCD2
tCD2
tCKHZ
tHC
tCKHZ
tSC
D0
D3
D1
DATAOUT(B1)
ADDRESS(B2)
tHA
tSA
tDC
A2
tDC
A3
tCKLZ
A4
A5
A0
A1
tHC
tSC
CE0(B2)
tCD2
tCKHZ
tCD2
tSC
tHC
DATAOUT(B2)
D4
D2
tCKLZ
tCKLZ
[14, 15, 16, 17]
Left Port Write to Flow-Through Right Port Read
CLKL
tHW
tSW
R/WL
tHA
tSA
NO
MATCH
ADDRESSL
MATCH
tHD
tSD
VALID
tCCS
DATAINL
CLKR
R/WR
tCD1
tSW tHW
tSA tHA
NO
MATCH
MATCH
ADDRESSR
tCWDD
tCD1
DATAOUTR
VALID
VALID
tDC
tDC
Notes:
12. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2. Each Bank consists of one Cypress dual-port device from this data sheet.
ADDRESS(B1) = ADDRESS(B2)
.
13. UB, LB, OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH
.
14. The same waveforms apply for a right port write to flow-through left port read.
15. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH
.
16. OE = VIL for the right port, which is being read from. OE = VIH for the left port, which is being written to.
17. It tCCS ≤ maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid
until tCCS + tCD1. tCWDD does not apply in this case.
9
CY7C09349V
CY7C09359V
PRELIMINARY
Switching Waveforms (continued)
Pipelined Read-to-Write-to-Read (OE = V )
[11, 18, 19, 20]
IL
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
R/W
tSW
tHW
tSW
tHW
An
An+1
An+2
An+2
An+3
An+4
ADDRESS
DATAIN
tSD tHD
tSA
tHA
Dn+2
tCD2
tCD2
tCKHZ
tCKLZ
Qn
Qn+3
DATAOUT
READ
NO OPERATION
[11, 18, 19, 20]
WRITE
READ
Pipelined Read-to-Write-to-Read (OE Controlled)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
R/W
tHW
tSW
tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
DATAOUT
tSA
tHA
tSD tHD
Dn+2
Dn+3
tCD2
tCKLZ
tCD2
DATAIN
OE
Qn
Qn+4
tOHZ
READ
WRITE
READ
Notes:
18. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
19. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH
.
20. During “No operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
10
CY7C09349V
CY7C09359V
PRELIMINARY
Switching Waveforms (continued)
Flow-Through Read-to-Write-to-Read (OE = V )
[9, 11, 19, 20]
IL
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
R/W
tSW
tHW
tSW
tHW
An
An+1
An+2
An+2
An+3
An+4
ADDRESS
DATAIN
tSD
tHD
tSA
tHA
Dn+2
tCD1
tCD1
tCD1
tCD1
DATAOUT
Qn
tDC
Qn+1
tCKHZ
Qn+3
tCKLZ
tDC
NO
OPERATION
READ
WRITE
READ
[9, 11, 18, 19, 20]
Flow-Through Read-to-Write-to-Read (OE Controlled)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
R/W
tSW
tHW
tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
DATAIN
tSD
tHD
tSA
tHA
Dn+2
Dn+3
tOE
tCD1
tDC
tCD1
tCD1
Qn
Qn+4
tDC
DATAOUT
OE
tOHZ
tCKLZ
READ
WRITE
READ
11
CY7C09349V
CY7C09359V
PRELIMINARY
Switching Waveforms (continued)
Pipelined Read with Address Counter Advance
[21]
tCYC2
tCH2
tCL2
CLK
tSA
tHA
ADDRESS
An
tSAD
tHAD
ADS
tSAD
tHAD
CNTEN
tSCN
tHCN
tSCN
tHCN
tCD2
DATAOUT
Qx-1
Qx
tDC
Qn
Qn+1
Qn+2
Qn+3
READ
COUNTER HOLD
READ WITH COUNTER
[21]
READ WITH COUNTER
EXTERNAL
ADDRESS
Flow-Through Read with Address Counter Advance
tCYC1
tCH1
tCL1
CLK
tSA
tHA
An
ADDRESS
tSAD
tHAD
ADS
tSAD
tHAD
CNTEN
tSCN
tHCN
tSCN
tHCN
tCD1
Qn+3
Qn+2
Qx
tDC
Qn
Qn+1
DATAOUT
READ
WITH
READ
COUNTER HOLD
READ WITH COUNTER
EXTERNAL
ADDRESS
COUNTER
Note:
21. CE0 and OE = VIL; CE1, R/W and CNTRST = VIH
.
12
CY7C09349V
CY7C09359V
PRELIMINARY
Switching Waveforms (continued)
Write with Address Counter Advance (Flow-Through or Pipelined Outputs)
[22, 23]
tCYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
An
An+1
An+2
An+3
An+4
tSAD
tHAD
ADS
CNTEN
DATAIN
tSCN
tHCN
Dn
Dn+1
Dn+1
Dn+2
Dn+3
Dn+4
tSD
tHD
WRITE EXTERNAL
ADDRESS
WRITE WITH WRITE COUNTER
COUNTER HOLD
WRITE WITH COUNTER
Notes:
22. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH
.
23. The “Internal Address” is equal to the “External Address” when ADS = VIL and equals the counter output when ADS = VIH
.
13
CY7C09349V
CY7C09359V
PRELIMINARY
Switching Waveforms (continued)
[11, 18, 24, 25]
Counter Reset (Pipelined Outputs)
tCYC2
tCH2
tCL2
CLK
tSA
tHA
An
An+1
ADDRESS
INTERNAL
ADDRESS
AX
0
1
An
An+1
tSW tHW
R/W
ADS
tSAD
tHAD
tSCN
tHCN
CNTEN
tSRST
tHRST
CNTRST
DATAIN
tSD tHD
D0
DATAOUT
Q0
Q1
Qn
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS n
Notes:
24. CE0, UB, and LB = VIL; CE1 = VIH
.
25. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
14
CY7C09349V
CY7C09359V
PRELIMINARY
Read/Write and Enable Operation[26, 27, 28]
Inputs
Outputs
OE
CLK
CE
CE
R/W
I/O –I/O
Operation
0
1
0
17
[29]
X
H
X
X
High-Z
Deselected
Deselected
Write
[29]
X
X
L
X
L
L
L
L
H
H
H
X
L
High-Z
D
IN
[29]
H
X
D
Read
OUT
H
X
High-Z
Outputs Disabled
Address Counter Control Operation[26, 30, 31, 32]
Previous
Address Address CLK ADS CNTEN CNTRST
I/O
Mode
Operation
X
X
X
X
X
H
L
H
H
D
D
D
Reset
Counter Reset to Address 0
out(0)
A
X
L
Load
Hold
Address Load into Counter
n
out(n)
out(n)
X
X
A
H
External Address Blocked—Counter
Disabled
n
n
A
H
L
H
D
Increment Counter Enabled—Internal Address
out(n+1)
Generation
Notes:
26. “X” = “don’t care,” “H” = VIH, “L” = VIL
.
27. ADS, CNTEN, CNTRST = “don’t care.”
28. OE is an asynchronous input signal.
29. When CE changes state In the pipelined mode, deselection and read happen in the following clock cycle.
30. CE0 and OE = VIL; CE1 and R/W = VIH
.
31. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle.
32. Counter operation is independent of CE0 and CE1.
15
CY7C09349V
CY7C09359V
PRELIMINARY
Ordering Information
4K x18 3.3V Synchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C09349V–7AC
CY7C09349V–9AC
CY7C09349V–9AI
CY7C09349V–12AC
CY7C09349V–12AI
Package Type
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
[1, 2]
7.5
A100
A100
A100
A100
A100
Commercial
Commercial
Industrial
9
12
Commercial
Industrial
8K x18 3.3V Synchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C09359V–7AC
CY7C09359V–9AC
CY7C09359V–9AI
CY7C09359V–12AC
CY7C09359V–12AI
Package Type
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
[1, 2]
7.5
A100
A100
A100
A100
A100
Commercial
Commercial
Industrial
9
12
Commercial
Industrial
Shaded areas contain advance information.
Document #: 38–00676–C
Package Diagram
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-A
16
CY7C09349V
CY7C09359V
PRELIMINARY
without the loss of any power. Contact your local Cypress FAE
for assistance as needed.
CY7C036 Dual Port Design Consideration –
Data Sheet Addendum
Troubleshooting—If a problem occurs with the part, power
down the device to ground and then power up again at slower
ramp rate (greater than 100 ns) in order to confirm that the
problem might be due to the POR circuit. If the dual-port func-
tions properly once the ramp rate is slowed to 100 ns or great-
er, then the POR circuit is at fault.
This design consideration applies to the Internal Power-On-
Reset (POR) circuit used on the CY7C036 and its derivatives
listed below.
Power supply ramp—The devices will function properly and
meet all data sheet specifications if the power supply ramp rate
is greater than 100 ns. If ramp is less than 100 ns, you may
see a non-destructive failure in which the device will not re-
spond to changes in address or clock, but the I/Os will respond
to the output enable.
Applicable devices—All speed/package/temperature combi-
nations of the following:
• CY7C09349V
• CY7C09359V
Applications consideration—If the power supply ramps in less
than 100 ns, a small resistor (20–50Ω), a large capacitor, or an
RC network can be connected at the output of the power sup-
ply to ground. The addition of a resistor will help clean up the
power lines, while the capacitor will slow down the ramp rate
Cypress design change—Cypress design team has identified
the root cause. A permanent circuit change and die revision
will be available beginning in October and will be identified by
the letter “A” in the part number.
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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