CY7C09579V-83BBI [CYPRESS]
3.3V 16K/32K x 36 FLE x 36-TM Synchronous Dual-Port Static RAM; 3.3V 16K / 32K ×36 FLE ×36 -TM同步双端口静态RAM
| 型号： | CY7C09579V-83BBI |
| 厂家： | 
CYPRESS |
| 描述： | 3.3V 16K/32K x 36 FLE x 36-TM Synchronous Dual-Port Static RAM |
| 文件： | 总30页 (文件大小：1118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C09569V CY7C09579V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 16K/32K
FLEx36™ Synchronous Dual-Port Static RAM
x 36
CY7C09569V
CY7C09579V
3.3V 16K/32K x 36
FLEx36™ Synchronous Dual-Port Static RAM
• 3.3V Low operating power
Features
— Active = 250 mA (typical)
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
— Standby = 10 μA (typical)
• Fully synchronous interface for ease of use
• Burst counters increment addresses internally
— Shorten cycle times
• Two Flow-Through/Pipelined devices
— 16K x 36 organization (CY7C09569V)
— 32K x 36 organization (CY7C09579V)
• 0.25-micron CMOS for optimum speed/power
• Three modes
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
• Counter Address Read Back via I/O lines
• Single Chip Enable
— Flow-Through
— Pipelined
• Automatic power-down
— Burst
• Commercial and Industrial Temperature Ranges
• Compact package
• Bus-Matching Capabilities on Right Port
(x36 to x18 or x9)
• Byte-Select Capabilities on Left Port
• 100-MHz Pipelined Operation
— 144-Pin TQFP (20 x 20 x 1.4 mm)
— 144-Pin Pb-Free TQFP (20 x 20 x 1.4 mm)
— 172-Ball BGA (1.0-mm pitch) (15 x 15 x 0.51 mm)
• High-speed clock to data access 5/6/8 ns
Logic Block Diagram
R/WL
R/WR
OEL
Left
Right
Port
Control
Logic
OER
CER
Port
Control
Logic
B0–B3
CEL
FT/PipeR
FT/PipeL
BE
9
9
9
9
9
9
9
9
I/O0L–I/O8L
9/18/36
I/O9L–I/O17L
I/O18L–I/O26L
I/O27L–I/O35L
Bus
Match
I/O
Control
I/O
Control
I/OR
BM
SIZE
14/15
14/15
[1]
[1]
A0–A13/14L
A0–A13/14R
CLKR
Counter/
Address
Register
Decode
Counter/
CLKL
True Dual-Ported
Address
Register
Decode
ADSL
ADSR
RAM Array
CNTENL
CNTRSTL
CNTENR
CNTRSTR
Note:
1. A –A for 16K; A –A for 32K devices.
0
13
0
14
Cypress Semiconductor Corporation
Document #: 38-06054 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised April 18, 2005
CY7C09569V
CY7C09579V
A HIGH on CE for one clock cycle will power down the internal
circuitry to reduce the static power consumption. In the
pipelined mode, one cycle is required with CE LOW to
reactivate the outputs.
Functional Description
The CY7C09569V and CY7C09579V are high-speed 3.3V
synchronous CMOS 16K and 32K x 36 dual-port static RAMs.
Two ports are provided, permitting independent, simultaneous
access for reads and writes to any location in memory.
Registers on control, address, and data lines allow for minimal
set-up and hold times. In pipelined output mode, data is regis-
tered for decreased cycle time. Clock to data valid tCD2 = 5 ns
(pipelined). Flow-through mode can also be used to bypass
the pipelined output register to eliminate access latency. In
flow-through mode data will be available tCD1 = 12.5 ns after
the address is clocked into the device. Pipelined output or
flow-through mode is selected via the FT/Pipe pin.
Counter Enable Inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW-to-HIGH
transition of that port’s clock signal. This will read/write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array and will loop back to the start. Counter Reset (CNTRST)
is used to reset the burst counter.
Each port contains a burst counter on the input address
register. The internal write pulse width is independent of the
external R/W LOW duration. The internal write pulse is self-
timed to allow the shortest possible cycle times.
All parts are available in 144-Pin Thin Quad Plastic Flatpack
(TQFP), 144-Pin Pb-Free Thin Quad Plastic Flatpack (TQFP)
and 172-Ball Ball Grid Array (BGA) packages.
Document #: 38-06054 Rev. *B
Page 2 of 30
CY7C09569V
CY7C09579V
Pin Configurations
144-Pin Thin Quad Flatpack (TQFP)
Top View
I/O33L
I/O34L
1
2
108
I/O33R
I/O34R
107
106
I/O35L
A0L
I/O35R
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
3
4
105
104
103
102
A1L
5
6
7
A2L
A3L
A4L
A5L
8
101
100
9
10
99
98
97
A6L
A7L
11
12
13
BM
SIZE
B0
B1
96
95
94
BE
B2
B3
14
15
vss
OER
R/WR
VDD
VSS
VSS
CER
CLKR
ADSR
16
17
18
19
93
92
91
90
OEL
R/WL
VDD
VSS
CY7C09569V (16K x 36)
CY7C09579V (32K x 36)
VSS
20
21
89
88
CEL
CLKL
22
23
24
87
86
85
84
83
82
ADSL
CNTRSTL
CNTRSTR
CNTENR
FT/PIPER
CNTENL
FT/PIPEL
A8L
25
26
27
A8R
A9R
A10R
28
29
30
31
A9L
81
80
A10L
79
78
77
A11R
A12R
A13R
A11L
A12L
A13L
32
33
NC
NC[2
76
75
[3
I/O26L
34
35
36
I/O26R
I/O25L
I/O24L
74
73
I/O25R
I/O24R
Notes:
2. This pin is A14L for CY7C09579V.
3. This pin is A14R for CY7C09579V.
Document #: 38-06054 Rev. *B
Page 3 of 30
CY7C09569V
CY7C09579V
Pin Configurations (continued)
172-Ball Ball Grid Array (BGA)
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
I/O32L I/O30L NC
VSS I/O13L VDD I/O11L I/O11R VDD I/O13R VSS
NC I/O30R I/O32R
A
B
C
D
E
F
A0L I/O33L I/O29 I/O17L I/O14L I/O12L I/O9L I/O9R I/O12R I/O14R I/O17R I/O29R I/O33R A0R
NC
A2L
A4L
VDD
OEL
A1L I/O31L I/O27L NC I/O15L I/O10L I/O10R I/O15R NC I/O27R I/O31R A1R
A3L I/O35L I/O34L I/O28L I/O16L VSS VSS I/O16R I/O28R I/O34R I/O35R A3R
NC
A2R
A4R
VDD
OER
A5L
A6L
B2L
NC
A7L
B3L
B0L
B1L
CEL
NC
NC
NC
NC
NC
NC
BM
SIZE A7R
CER VSS
NC
A5R
A6R
BE
G
H
J
VSS R/WL A8L CLKL
CLKR A8R R/WR VSS
A9L
A10L VSS ADSL
NC
NC
NC ADSR VSS A10R
A9R
CNTRSTL
CNTRSTR
A11L A12L
NC
NC
NC
NC
NC
A12R A11R
K
L
FT/PIPEL
CNTENL
CNTENR
FT/PIPER
A13L
I/O26L I/O25L I/O19L VSS
I/O7L I/O2L I/O2R I/O7R
I/O24L I/O20L I/O8L I/O6L I/O5L I/O3L I/O0L I/O0R I/3R I/O5R I/O6R I/O8R I/O20R I/O24R
I/O23L I/O21L NC VSS I/O4L VDD I/O1L I/O1R VDD I/O4R VSS NC I/O21R I/O23R
VSS I/O19R I/O25R I/O26R
A13R
NC
NC[2] I/O22L I/O18L NC
NC I/O18R I/O22R NC[3]
NC
M
N
P
Document #: 38-06054 Rev. *B
Page 4 of 30
CY7C09569V
CY7C09579V
Selection Guide
CY7C09569V CY7C09569V CY7C09569V
CY7C09579V CY7C09579V CY7C09579V
-100
100
5
-83
83
6
-67
67
8
Unit
MHz
ns
fMAX2 (Pipelined)
Max. Access Time (Clock to Data, Pipelined)
Typical Operating Current ICC
250
30
240
25
10
230
25
10
mA
mA
μA
Typical Standby Current for ISB1 (Both Ports TTL Level)
Typical Standby Current for ISB3 (Both Ports CMOS Level)
10
Pin Definitions
Left Port
A0L–A13/14L
ADSL
Right Port
A0R–A13/14R
ADSR
Description
Address Inputs (A0–A13 for 16K, A0–A14 for 32K devices).
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
assert the part using the externally supplied address on Address Pins. To load this address into
the Burst Address Counter both ADS and CNTEN have to be LOW. ADS is disabled if CNTRST
is asserted LOW
CEL
CER
Chip Enable Input.
CLKL
CLKR
Clock Signal. This input can be free-running or strobed. Maximum clock input rate is fMAX.
CNTENL
CNTENR
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if CNTRST is asserted LOW.
CNTRSTL
CNTRSTR
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its
respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
I/O0L–I/O35L
OEL
I/O0R–I/O35R Data Bus Input/Output.
OER
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
R/WL
R/WR
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.
For read operations, assert this pin HIGH.
FT/PIPEL
B0L–B3L
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
For pipelined mode operation, assert this pin HIGH.
FT/PIPE
R
Byte Select Inputs. Asserting these signals enable read and write operations to the corre-
sponding bytes of the memory array.
Select Pins for Bus Matching. See Bus Matching for details.
Big Endian Pin. See Bus Matching for details.
BM, SIZE
BE
VSS
VDD
Ground Input.
Power Input.
Document #: 38-06054 Rev. *B
Page 5 of 30
CY7C09569V
CY7C09579V
Maximum Ratings [4]
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................>2001V
Latch-Up Current.....................................................>200 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Operating Range
Ambient
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential............... –0.5V to +4.6V
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VDD
3.3V ± 165 mV
3.3V ± 165 mV
DC Voltage Applied to
Outputs in High Z State............................–0.5V to VDD+0.5V
DC Input Voltage.................................. –0.5V to VDD+0.5V[5]
Electrical Characteristics Over the Operating Range
CY7C09569V
CY7C09579V
-100
-83
-67
Parameter
Description
Output HIGH Voltage
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
VOH
2.4
2.4
2.4
V
(VDD = Min., IOH = –4.0 mA)
VOL
Output LOW Voltage
(VDD = Min., IOL= +4.0 mA)
0.4
0.4
0.4
V
VIH
VIL
IOZ
ICC
Input HIGH Voltage
2.0
2.0
2.0
V
V
Input LOW Voltage
0.8
0.8
0.8
10
Output Leakage Current
–10
10 –10
250 385
10 –10
240 360
270 385
μA
Operating Current (VDD = Max., Commercial
230 340 mA
mA
I
OUT = 0 mA) Outputs Disabled
Industrial
ISB1
ISB2
ISB3
Standby Current (Both Ports TTL Commercial
30
170 220
0.01
75
25
35
70
85
25
65
mA
mA
Level) CEL & CER ≥ VIH, f = fMAX
Industrial
Standby Current (One Port TTL Commercial
160 210
170 235
150 200 mA
mA
Level) CEL | CER ≥ VIH, f = fMAX
Industrial
Standby Current (Both Ports
CMOS Level)
CEL & CER ≥ VDD – 0.2V, f = 0
Commercial
Industrial
1
0.01
0.01
1
1
0.01
1
mA
mA
ISB4
StandbyCurrent(OnePortCMOS Commercial
150 200
140 190
150 200
130 180 mA
mA
Level)
Industrial
CEL | CER ≥ VIH, f = fMAX
Capacitance
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
Unit
pF
CIN
COUT
Note:
TA = 25°C, f = 1 MHz,
VDD = 3.3V
10
10
pF
4. The voltage on any input or I/O pin can not exceed the power pin during power-up.
5. Pulse width < 20 ns.
Document #: 38-06054 Rev. *B
Page 6 of 30
CY7C09569V
CY7C09579V
AC Test Load and Waveforms
3.3V
Z0 = 50Ω
R = 50Ω
OUTPUT
R1 = 590Ω
[6]
C
OUTPUT
V
TH
= 1.5V
C = 5 pF
R2 = 435Ω
(b) Three-State Delay (Load 2)
(a) Normal Load (Load 1)
3.0V
VSS
90%
10%
90%
10%
3 ns
ALL INPUT PULSES
3 ns
≤
≤
7
6
5
4
3
2
1
20[7]
30 60 80 100
200
Capacitance (pF)
(b) Load Derating Curve
Notes:
6. External AC Test Load Capacitance = 10 pF.
7. (Internal I/O pad Capacitance = 10 pF) + AC Test Load.
Document #: 38-06054 Rev. *B
Page 7 of 30
CY7C09569V
CY7C09579V
Switching Characteristics Over the Operating Range
CY7C09569V
CY7C09579V
-100
-83
-67
Parameter
fMAX1
fMAX2
tCYC1
tCYC2
tCH1
tCL1
tCH2
tCL2
tR
Description
fMax Flow-Through
Min.
Max.
67
Min.
Max.
45
Min.
Max.
40
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
fMax Pipelined
100
83
67
Clock Cycle Time - Flow-Through
Clock Cycle Time - Pipelined
Clock HIGH Time - Flow-Through
Clock LOW Time - Flow-Through
Clock HIGH Time - Pipelined
Clock LOW Time - Pipelined
Clock Rise Time
15
10
6.5
6.5
4
22
12
7.5
7.5
5
25
15
8.5
8.5
6.5
6.5
4
5
3
3
3
3
3
3
tF
Clock Fall Time
tSA
Address Set-Up Time
Address Hold Time
3.5
0.5
3.5
0.5
3.5
0.5
3.5
0.5
3.5
0.5
3.5
0.5
3.5
0.5
3.5
0.5
4
0.5
4
4
0.5
4
tHA
tSB
Byte Select Set-Up Time
Byte Select Hold Time
Chip Enable Set-Up Time
Chip Enable Hold Time
R/W Set-Up Time
tHB
0.5
4
0.5
4
tSC
tHC
0.5
4
0.5
4
tSW
tHW
R/W Hold Time
0.5
4
0.5
4
tSD
Input Data Set-Up Time
Input Data Hold Time
ADS Set-Up Time
tHD
0.5
4
0.5
4
tSAD
tHAD
tSCN
tHCN
tSRST
tHRST
tOE
ADS Hold Time
0.5
4
0.5
4
CNTEN Set-Up Time
CNTEN Hold Time
0.5
4
0.5
4
CNTRST Set-Up Time
CNTRST Hold Time
0.5
0.5
Output Enable to Data Valid
OE to Low Z
8
9
10
[8, 9]
tOLZ
2
1
2
1
2
1
[8, 9]
tOHZ
OE to High Z
7
7
18
6
7
20
8
tCD1
tCD2
tCA1
Clock to Data Valid - Flow-Through
Clock to Data Valid - Pipelined
12.5
5
Clock to Counter Address Valid -
Flow-Through
12.5
18
20
tCA2
tDC
Clock to Counter Address Valid - Pipelined
Data Output Hold After Clock HIGH
Clock HIGH to Output High Z
9
6
10
7
11
8
ns
ns
ns
ns
2
2
2
2
2
2
2
2
2
[8, 9]
tCKHZ
[8, 9]
tCKLZ
Clock HIGH to Output Low Z
Notes:
8. This parameter is guaranteed by design, but it is not production tested.
9. Test conditions used are Load 2.
Document #: 38-06054 Rev. *B
Page 8 of 30
CY7C09569V
CY7C09579V
Switching Characteristics Over the Operating Range (continued)
CY7C09569V
CY7C09579V
-100
-83
-67
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Port to Port Delays
tCWDD
tCCS
Write Port Clock HIGH to Read Data Delay
Clock to Clock Set-Up Time
30
9
35
10
35
12
ns
ns
Document #: 38-06054 Rev. *B
Page 9 of 30
CY7C09569V
CY7C09579V
Switching Waveforms
Read Cycle for Flow-Through Output (FT/PIPE = VIL)[10, 11, 12, 13]
tCYC1
tCH1
tCL1
CLK
CE
tSC
tHC
tSC
tHC
tSB
tHB
B0-3
R/W
tSW
tSA
tHW
tHA
An
An+1
An+2
An+3
ADDRESS
DATAOUT
tCKHZ
tDC
Qn
tCD1
Qn+1
Qn+2
tDC
tCKLZ
tOHZ
tOLZ
OE
tOE
Read Cycle for Pipelined Operation (FT/PIPE = VIH)[10, 11, 12, 13]
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tSC
tHC
tSB
tHB
B0-3
R/W
tSW
tSA
tHW
tHA
ADDRESS
DATAOUT
An
An+1
An+2
An+3
tDC
1 Latency
tCD2
Qn
Qn+1
tOHZ
Qn+2
tCKLZ
tOLZ
OE
t
OE
Notes:
10. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
11. ADS = V , CNTEN = V and CNTRST = V
.
IH
IL
IL
12. The output is disabled (high-impedance state) by CE=V following the next rising edge of the clock.
IH
13. Addresses do not have to be accessed sequentially since ADS = V constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
IL
Document #: 38-06054 Rev. *B
Page 10 of 30
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Bus Match Read Cycle for Flow-Through Output (FT/PIPE = VIL)[10, 12, 14, 15, 16]
tCYC1
tCH1
tCL1
CLK
CE
tSC
tHC
ADS
R/W
tSW
tSA
tHW
tHA
An
An
An+1
An+1
ADDRESS
DATAOUT
tDC
Qn
tCD1
Qn
Qn+1
1st
Cycle
Qn+1
2nd
Cycle
1st
Cycle
2nd
Cycle
tCKLZ
tDC
LOW
OE
Bus Match Read Cycle for Pipelined Operation (FT/PIPE = VIH)[10, 12, 14, 15, 16]
tCYC2
tCL2
tCH2
CLK
CE
tHC
tSC
R/W
tSW tHW
ADS
ADDRESS
An+1
An
An
An+1
tSA tHA
t
tCD2
tCD2
CD2
tCLKZ
DATAOUT
Qn
Qn
Qn+1
1 Latency
tDC
tDC
2nd Cycle
tDC
1st Cycle
1st Cycle
OE
LOW
Notes:
14. Timing shown is for x18 bus matching; x9 bus matching is similar with 4 cycles between address inputs.
15. See table “Right Port Operation“ for data output on first and subsequent cycles.
16. CNTEN = V . In x9 and x18 Bus Matching Burst Mode operations (Write or Read), ADS can toggle on the rising edge of every clock cycle or it can be at V level
IL
IH
all the time except when loading the initial external address (i.e. ADS = V only required when reading or writing the first Byte or Word).
IL
Document #: 38-06054 Rev. *B
Page 11 of 30
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Bank Select Pipelined Read[17, 18]
tCYC2
tCH2
tCL2
CLKL
tHA
tSA
A3
A4
ADDRESS(B1)
A5
A0
A1
A2
tHC
tSC
CE(B1)
tCD2
tCD2
tCD2
tCKHZ
tHC
tCKHZ
tSC
Q0
Q3
Q1
DATAOUT(B1)
ADDRESS(B2)
tHA
tSA
tDC
A2
tDC
A3
tCKLZ
A4
A5
A0
A1
tHC
tSC
CE(B2)
tCD2
tCKHZ
tCD2
tSC
tHC
DATAOUT(B2)
Q4
Q2
tCKLZ
tCKLZ
Left Port Write to Flow-Through Right Port Read[18, 19, 20, 21, 22]
CLKL
tHW
tSW
R/WL
tHA
tSA
NO
MATCH
ADDRESSL
MATCH
tHD
tSD
VALID
tCCS
DATAINL
CLKR
R/WR
tCD1
tSW tHW
tSA tHA
NO
MATCH
MATCH
ADDRESSR
tCWDD
tCD1
DATAOUTR
VALID
VALID
tDC
tDC
Notes:
17. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this data sheet.
ADDRESS = ADDRESS
.
(B2)
(B1)
18. B0 = B1 = B2 = B3 = BM = SIZE = ADS = CNTEN = V , CNTRST = V
.
IL
IH
19. The same waveforms apply for a right port write to flow-through left port read.
20. CE = B0 = B1 = B2 = B3 = ADS = CNTEN=V ; CNTRST= V
.
IH
IL
21. OE = V for the right port, which is being read from. OE = V for the left port, which is being written to.
IL
IH
22. If t
≤ maximum specified, then data from right port READ is not valid until the maximum specified for t
. If t >maximum specified, then data is not valid
CCS
CCS
CWDD
until t
+ t
(t
does not apply in this case).
CCS
CD1 CWDD
Document #: 38-06054 Rev. *B
Page 12 of 30
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Pipelined Read-to-Write-to-Read (OE = VIL)[13, 23, 24, 25]
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tSW
tHW
R/W
tSW
tHW
An
An+1
An+2
An+2
An+3
An+4
ADDRESS
DATAIN
tSD tHD
tSA
tHA
Dn+2
tCD2
tCD2
tCKHZ
tCKLZ
Qn
Qn+3
DATAOUT
READ
NO OPERATION
WRITE
READ
Notes:
23. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
24. CE = ADS = CNTEN = V ; CNTRST = V
.
IH
IL
25. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
Document #: 38-06054 Rev. *B
Page 13 of 30
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Pipelined Read-to-Write-to-Read (OE Controlled)[11, 23, 24, 25]
tCYC2
tCH2
tCL2
CLK
CE
tSC
tHC
tHW
tSW
R/W
tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
DATAIN
tSA
tHA
tSD tHD
Dn+2
Dn+3
tCD2
tCKLZ
tCD2
DATAOUT
Qn
Qn+4
tOHZ
OE
READ
WRITE
READ
Document #: 38-06054 Rev. *B
Page 14 of 30
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Bus Match Pipelined Read-to-Write-to-Read (OE = VIL)[11, 14, 15, 16, 24, 25, 26]
tCYC2
CLK
tCL2
tCH2
CE
tSC
tHC
R/W
tSW
tHW
ADDRESS
An+3
An+2
An+4
An+1
An+2
An+4
An
An+3
An
An+1
tSA
tHA
ADS
tCKLZ
2nd Word
Qn+3
2nd Word
Qn
1st Word
Qn+3
1st Word
Qn
DATAOUT
DATAIN
tCKHZ
tCD2
tCD2
tCD2
2nd Word
Dn+2
1st Word
Dn+2
tDC
tHD
tSD
No
Operation 1st Cycle
READ
1st Cycle
READ
1st Cycle
WRITE
2nd Cycle
READ
READ
2nd Cycle
READ
READ
2nd Cycle
WRITE
Note:
26. BM, SIZE, and BE must be reconfigured 1 cycle before operation is guaranteed. BM, SIZE, and BE should remain static for any particular port configuration.
Document #: 38-06054 Rev. *B
Page 15 of 30
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Flow-Through Read-to-Write-to-Read (OE = VIL)[11, 13, 14, 15, 24, 25]
tCYC1
tCH1
tCL1
CLK
CE
tSW
tHW
R/W
tSW
tHW
An
An+1
An+2
An+2
An+3
An+4
ADDRESS
DATAIN
tSD
tHD
tSA
tHA
Dn+2
tCD1
tCD1
tCD1
tCD1
DATAOUT
Qn
tDC
Qn+1
tCKHZ
Qn+3
tDC
tCKLZ
NO
OPERATION
READ
WRITE
READ
Flow-Through Read-to-Write-to-Read (OE Controlled)[11, 13, 23,24, 25]
tCYC1
tCH1
tCL1
CLK
CE
tSW
tHW
R/W
tSW
tHW
An
An+1
An+2
An+3
An+4
An+5
ADDRESS
DATAIN
tSD
tHD
tSA
tHA
Dn+2
Dn+3
tOE
tCD1
tDC
tCD1
tCD1
Qn
Qn+4
tDC
DATAOUT
OE
tOHZ
tCKLZ
READ
WRITE
READ
Document #: 38-06054 Rev. *B
Page 16 of 30
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Bus Match Flow-Through Read-to-Write-to-Read (OE = VIL)[11, 14, 15, 16, 24, 25, 26]
tCYC1
tCH1 tCL1
CLK
tSC tHC
CE
tSW tHW
tSW tHW
R/W
tSA tHA
An+1
ADDRESS
ADS
An
An+1
An+1
An+2
An+1
An+1
An
tSD tHD
Dn+1
Dn+1
DATAIN
tCD1
tDC
2nd Word
1st Word
tCKHZ
tCD1
tCD1
tCD1
Qn
1st Word
Qn+1
Qn+1
Qn
DATAOUT
2nd Word
tDC
tCKLZ
READ
1st Cycle
READ
2nd Cycle
No
Operation
WRITE
1st Cycle
WRITE
2nd Cycle
READ
1st Cycle
READ
2nd Cycle
Document #: 38-06054 Rev. *B
Page 17 of 30
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Pipelined Read with Address Counter Advance[27]
tCYC2
tCH2
tCL2
CLK
tSA
tHA
ADDRESS
An
tSAD
tHAD
ADS
tSAD
tHAD
CNTEN
tSCN
tHCN
tSCN
tHCN
tCD2
DATAOUT
Qx–1
Qx
tDC
Qn
Qn+1
COUNTER HOLD
Qn+2
Qn+3
READ
READ WITH COUNTER
READ WITH COUNTER
EXTERNAL
ADDRESS
Flow-Through Read with Address Counter Advance[27]
tCYC1
tCH1
tCL1
CLK
tSA
tHA
An
ADDRESS
tSAD
tHAD
ADS
tSAD
tHAD
CNTEN
tSCN
tHCN
tCD1
tSCN
Qn+2
tHCN
Qx
tDC
Qn
Qn+1
DATAOUT
Qn+3
Qn+4
COUNTER HOLD
READ
tDC
tDC
READ
WITH
EXTERNAL
ADDRESS
READ WITH COUNTER
tCD1
tCD1
COUNTER
Note:
27. CE = OE = V ; R/W = CNTRST = V
.
IL
IH
Document #: 38-06054 Rev. *B
Page 18 of 30
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Write with Address Counter Advance (Flow-Through or Pipelined Outputs)[28, 29]
tCYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
An
An+1
An+2
An+3
An+4
tSAD
tHAD
ADS
CNTEN
DATAIN
tSCN
tHCN
Dn
Dn+1
Dn+1
Dn+2
Dn+3
Dn+4
tSD
tHD
WRITE EXTERNAL
ADDRESS
WRITE WITH WRITE COUNTER
COUNTER HOLD
WRITE WITH COUNTER
Notes:
28. CE= B0 = B1 = B2 = B3 = R/W = V ; CNTRST = V
.
IH
IL
29. The “Internal Address” is equal to the “External Address” when ADS = CNTEN = V and CNTRST=V
.
IL
IH
Document #: 38-06054 Rev. *B
Page 19 of 30
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Counter Reset (Pipelined Outputs)[11, 23, 30, 31, 32]
tCYC2
tCH2 tCL2
CLK
tHA
Am
tSA
Ap
An
ADDRESS
INTERNAL
Ap
Ax
An
1
0
Am
ADDRESS
tHW
tSW
R/W
ADS
CNTEN
CNTRST
tHRST
tSRST
tHD
tSD
DATAIN
D0
tCD2
tCD2
DATA
[32
OUT
Q0
Qn
Q1
tCKLZ
READ
ADDRESS 1
READ
ADDRESS An
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS Am
Notes:
30. CE = B0 = B1 = B2 = B3 = V .
IL
31. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
32. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. Ideally, DATA
should be in the High-Impedance state during
OUT
a valid WRITE cycle.
Document #: 38-06054 Rev. *B
Page 20 of 30
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Counter Reset (Flow-Through Outputs)[23, 25, 30, 31, 32]
tCYC2
tCH2
tCL2
CLK
tSA tHA
An
An+1
ADDRESS
INTERNAL
ADDRESS
AX
0
An
An+1
1
tSW tHW
R/W
ADS
CNTEN
tHRST
tSRST
CNTRST
DATAIN
tHD
tSD
D0
tCD1
DATAOUT
Q0
Qn
Q1
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS n
Document #: 38-06054 Rev. *B
Page 21 of 30
CY7C09569V
CY7C09579V
Switching Waveforms (continued)
Pipelined Read of State of Address Counter [33, 34, 35]
tCYC2
tCH2 tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
An
An+2
An+1
tSAD
tHAD
ADS
CNTEN
tSAD
tHAD
tSCN
tHCN
tSCN
tHCN
tSCN
tHCN
tCA2
DATAOUT
Qx-1
Qx-2
Qn
An
Qn+1
Qn+2
READ WITH
COUNTER
LOAD
EXTERNAL
ADDRESS
tDC
READ COUNTER ADDRESS
COUNTER
HOLD
READ WITH COUNTER
Flow-Through Read of State of Address Counter [33, 34, 36]
tCYC1
tCH1 tCL1
CLK
tSA
tHA
An
ADDRESS
INTERNAL
ADDRESS
An
An+1
An+3
An+2
tSAD
tHAD
ADS
CNTEN
tSAD
tHAD
tSCN
tHCN
tSCN
tHCN
tCA1
tHCN
tSCN
DATAOUT
Qn
Qx
An
Qn+2
Qn+1
READ WITH
Qn+3
tDC
READ COUNTER ADDRESS
COUNTER
LOAD
EXTERNAL
ADDRESS
COUNTER
HOLD
READ WITH COUNTER
Notes:
33. CE = OE = V ; R/W = CNTRST = V
.
IH
IL
34. When reading ADDRESS
in x9 Bus Match mode, readout of A is extended by 1 cycle.
OUT
N
35. For Pipelined address counter read, signals from address counter operation table from must be valid for 2 consecutive cycles for x36 and x18 mode and for 3
consecutive cycles for x9 mode.
36. For flow-through address counter read, signals from address counter operation table must be valid for consecutive cycles for x36.
Document #: 38-06054 Rev. *B
Page 22 of 30
CY7C09569V
CY7C09579V
Read/Write and Enable Operation[37, 38, 39]
Inputs
Outputs
I/O0–I/O35
High-Z
OE
CLK
CE
R/W
Operation
X
H
X
Deselected[40]
X
L
L
L
L
L
H
X
DIN
Write
DOUT
High-Z
Read[40]
H
X
Outputs Disabled
Address Counter Control Operation[37, 41]
Previous
Address Address CLK
OE
R/W
ADS
CNTEN CNTRST
Mode
Operation
X
X
X
X
X
X
L
H
H
Reset
Counter Reset
An
An
X
X
L
X
H
L
L
L
Load
Address Load into Counter
An
H
Hold + External Address Blocked -
Read
Counter Address Readout
X
X
An
An
X
X
X
X
H
H
H
L
H
H
Hold
External Address Blocked -
Counter Disabled
Increment Counter Increment
Notes:
37. “X” = “Don’t Care,” “H” = V , “L” = V .
IH
IL
38. ADS, CNTEN, CNTRST = “Don’t Care.”
39. OE is an asynchronous input signal.
40. When CE changes state In the pipelined mode, deselection and read happen in the following clock cycle.
41. Counter operation is independent of CE.
Document #: 38-06054 Rev. *B
Page 23 of 30
CY7C09569V
CY7C09579V
Right Port Configuration[26, 42]
BM
0
SIZE
Configuration
I/O Pins used
0
0
1
x36
x18
x9
I/O0R–35R
I/O0R–17R
I/O0R–8R
1
1
Right Port Operation[43]
Configuration
BE
0
Data on 1st Cycle
DQ0R–17R
Data on 2nd Cycle
DQ18R–35R
Data on 3rd Cycle
Data on 4th Cycle
x18
x18
x9
-
-
1
DQ18R–35R
DQ0R–8R
DQ0R–17R
-
-
0
DQ9R–17R
DQ18R–26R
DQ9R–17R
DQ27R–35R
DQ0R–8R
x9
1
DQ27R–35R
DQ18R–26R
Readout of Internal Address Counter[44]
Address on 2nd
Cycle
I/O Pins used on 2nd
Cycle
Configuration
Left Port x36
Right Port x36
Right Port x18
Right Port x9
Address on 1st Cycle
A0L–14L
I/O Pins used on 1st Cycle
I/O3L–17L
-
-
A0R–14R
I/O3R–17R
-
-
WA, A0R–14R
A6R–14R
I/O2R–17R
-
-
I/O0R–8R
BA, WA, A0R–5R
I/O1R–8R
Left Port Operation
Control Pin
Effect
B0
B1
B2
B3
I/O0–8 Byte Control
I/O9–17 Byte Control
I/O18–26 Byte Control
I/O27–35 Byte Control
Notes:
42. In x36 mode, BE input is a “Don’t Care.”
43. DQ represents data output of the chip.
44. x18 and x9 configuration apply to right port only.
Document #: 38-06054 Rev. *B
Page 24 of 30
CY7C09569V
CY7C09579V
word, or 9-bit byte format for data I/O. The data lines are
divided into four lanes, each consisting of 9 bits (byte-size data
lines).
Counter Operation
The CY7C09569V/09579V Dual-Port RAM (DPRAM) contains
on-chip address counters (one for each port) for the
synchronous members of the product family. Besides the main
x36 format, the right port allows bus matching (x18 or x9, user-
selectable). An internal sub-counter provides the extra
addresses required to sequence out the 36-bit word in 18-bit
or 9-bit increments. The sub-counter counts up in the “Little
Endian” mode, and counts down if the user has chosen the
“Big Endian” mode. The address counter is required to be in
increment mode in order for the sub-counter to sequence out
the second word (in x18 mode) or the remaining three bytes
(in x9 mode).
BE
9
/
9
/
9
CY7C09569V
CY7C09579V
16K/32Kx36
Dual Port
x36
/
x9, x18, x36
/
/
9
/
For a x36 format (the only active format on the left port), each
address counter in the CY7C09579V uses addresses (A0–14).
BM SIZE
For the right port (allowing for the bus-matching feature), a
maximum of two address bits (out of a 2-bit sub-counter) are
added.
Figure 2. Bus Match Operation Diagram
The Bus Match Select (BM) pin works with Bus Size Select
(SIZE) and Big Endian Select (BE) to select the bus width
(long-word, word, or byte) and data sequencing arrangement
for the right port of the dual-port device. A logic “0” applied to
both the Bus Match Select (BM) pin and to the Bus Size Select
(SIZE) pin will select long-word (36-bit) operation. A logic “1”
level applied to the Bus Match Select (BM) pin will enable
whether byte or word bus width operation on the right port I/Os
depending on the logic level applied to the SIZE pin. The level
of Bus Match Select (BM) must be static throughout normal
device operation.
1. ADSL/R (pin #23/86) is a port's address strobe, allowing the
loading of that port's burst counters if the corresponding
CNTENL/R pin is active as well.
2. CNTENL/R (pin #25/84) is a port's count enable, provided
to stall the operation of the address input and utilize the
internal address generated by the internal counter for fast
interleaved memory applications; when asserted, the
address counter will increment on each positive transition
of that port's clock signal.
3. CNTRSTL/R (pin #24/85) is a port's burst counter reset.
The Bus Size Select (SIZE) pin selects either a byte or word
data arrangement on the right port when the Bus Match Select
(BM) pin is HIGH. A logic “1” on the SIZE pin when the BM pin
is HIGH selects a byte bus (9-bit) data arrangement. A logic
“0” on the SIZE pin when the BM pin is HIGH selects a word
bus (18-bit) data arrangement. The level of the Bus Size Select
(SIZE) must also be static throughout normal device operation.
A new read-back (Hold+Read Mode) feature has been added,
which is different between the left and right port due to the bus
matching feature provided only for the right port. In read-back
mode the internal address of the counter will be read from the
data I/Os as shown in Figure 1.
The Big Endian Select (BE) pin is a multiple-function pin during
word or byte bus selection (BM = 1). BE is used in Big Endian
Select mode to determine the order by which bytes (or words)
of data are transferred through the right data port. A logic “0”
on the BE pin will select Little Endian data sequencing
arrangement and a logic “1” on the BE pin will select a Big
Endian data sequencing arrangement. Under these circum-
stances, the level on the BE pin should be static throughout
dual-port operation.
Address
CY7C09569V
CY7C09579V
RAM
ARRAY
_______
Long-Word (36-bit) Operation
ADS
______________
Bus Match Select (BM) and Bus Size Select (SIZE) set to a
logic “0” will enable standard cycle long-word (36-bit)
operation. In this mode, the right port’s I/O operates essentially
in an identical fashion to the left port of the dual-port SRAM.
However no Byte Select control is available. All 36 bits of the
long-word are shifted into and out of the right port’s I/O buffer
stages. All read and write timing parameters may be identical
with respect to the two data ports. When the right port is
configured for a long-word size, Big- Endian Select (BE) pin
has no application and their inputs are “Don’t Care”[45] for the
external user.
CNTRST
____________
CNTEN
I/O’s
Figure 1. Counter Operation Diagram
Bus Match Operation
The right port of the CY7C09569V/09579V 16K/32Kx36 dual-
port SRAM can be configured in a 36-bit long-word, 18-bit
Note:
45. Even though a logic level applied to a “Don’t Care” input will not change the logical operation of the dual-port, inputs that are temporarily a “Don’t Care” (along
with unused inputs) must not be allowed to float. They must be forced either HIGH or LOW.
Document #: 38-06054 Rev. *B
Page 25 of 30
CY7C09569V
CY7C09579V
Word (18-bit) Operation
Byte (9-bit) Operation
Word (18-bit) bus sizing operation is enabled when Bus Match
Select (BM) is set to a logic “1” and the Bus Size Select (SIZE)
pin is set to a logic “0.” In this mode, 18 bits of data are ported
through I/O0R–17R. The level applied to the Big Endian (BE) pin
determines the right port data I/O sequencing order (Big
Endian or Little Endian).
Byte (9-bit) bus sizing operation is enabled when Bus Match
Select (BM) is set to a logic “1” and the Bus Size Select (SIZE)
pin is set to a logic “1.” In this mode, 9 bits of data are ported
through I/O0R–8R
.
Big Endian and Little Endian data sequencing is available for
dual-port operation. The level applied to the Big Endian pin
(BE) under these circumstances will determine the right port
data I/O sequencing order (Big or Little Endian). A logic LOW
applied to the BE pin during byte (9-bit) bus size operation will
select Little Endian operation. In this case, the least significant
data byte is read from the right port first or written to the right
port first. A logic “1” on the BE pin during byte (9-bit) bus size
operation will select Big Endian operation resulting in the most
significant data word to be transferred through the right port
first. Internally, the data will be stored in the appropriate 36-bit
LSB or MSB I/O memory location. Device operation requires
a minimum of four clock cycles to read or write during byte (9-
bit) bus size operation. An internal sub-counter automatically
increments the right port multiplexer control when Little or Big
Endian operation is in effect. When transferring data in byte (9-
bit) bus match format, the unused I/O pins (I/O9RQ–35R) are
three-stated.
During word (18-bit) bus size operation, a logic LOW applied
to the BE pin will select Little Endian operation. In this case,
the least significant data word is read from the right port first
or written to the right port first. A logic “1” on the BE pin during
word (18-bit) bus size operation will select Big Endian
operation resulting in the most significant data word being
transferred through the right port first. Internally, the data will
be stored in the appropriate 36-bit LSB or MSB I/O memory
location. Device operation requires a minimum of two clock
cycles to read or write during word (18-bit) bus size operation.
An internal sub-counter automatically increments the right port
multiplexer control when Little or Big Endian operation is in
effect.
Document #: 38-06054 Rev. *B
Page 26 of 30
CY7C09569V
CY7C09579V
Ordering Information
16K x36 3.3V Synchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(MHz)
Ordering Code
CY7C09569V-100AC
CY7C09569V-100AXC
CY7C09569V-100BBC
CY7C09569V-83AC
CY7C09569V-83AXC
CY7C09569V-83BBC
CY7C09569V-67AC
CY7C09569V-67BBC
Package Type
144-Pin Thin Quad Flat Pack
144-Pin Pb-Free Thin Quad Flat Pack
172-Ball Ball Grid Array (BGA)
144-Pin Thin Quad Flat Pack
144-Pin Pb-Free Thin Quad Flat Pack
172-Ball Ball Grid Array (BGA)
144-Pin Thin Quad Flat Pack
172-Ball Ball Grid Array (BGA)
100
A144
A144
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
BB172
A144
83
67
A144
BB172
A144
BB172
32K x36 3.3V Synchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(MHz)
Ordering Code
CY7C09579V-100AC
CY7C09579V-100AXC
CY7C09579V-100BBC
CY7C09579V-83AC
CY7C09579V-83AXC
CY7C09579V-83AI
Package Type
144-Pin Thin Quad Flat Pack
144-Pin Pb-Free Thin Quad Flat Pack
172-Ball Ball Grid Array (BGA)
144-Pin Thin Quad Flat Pack
144-Pin Pb-Free Thin Quad Flat Pack
144-Pin Thin Quad Flat Pack
144-Pin Pb-Free Thin Quad Flat Pack
172-Ball Ball Grid Array (BGA)
172-Ball Ball Grid Array (BGA)
144-Pin Thin Quad Flat Pack
172-Ball Ball Grid Array (BGA)
100
A144
A144
Commercial
Commercial
Commercial
Commercial
Commercial
Industrial
BB172
A144
83
67
A144
A144
CY7C09579V-83AXI
CY7C09579V-83BBC
CY7C09579V-83BBI
CY7C09579V-67AC
CY7C09579V-67BBC
A144
Industrial
BB172
BB172
A144
Commercial
Industrial
Commercial
Commercial
BB172
Document #: 38-06054 Rev. *B
Page 27 of 30
CY7C09569V
CY7C09579V
Package Diagrams
144-Pin Plastic Thin Quad Flat Pack (TQFP) A144
144-Pin Pb-Free Plastic Thin Quad Flat Pack (TQFP) A144
51-85047-*A
Document #: 38-06054 Rev. *B
Page 28 of 30
CY7C09569V
CY7C09579V
Package Diagrams (continued)
172-Ball FBGA (15 x 15 x 1.25 mm) BB172
51-85114-*B
FLeX36 is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document
may be the trademarks of their respective holders.
Document #: 38-06054 Rev. *B
Page 29 of 30
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C09569V
CY7C09579V
Document History Page
Document Title: CY7C09569V/CY7C09579V 3.3 16K/ 32K x 36 FLEx36™ Synchronous Dual-Port Static RAM
Document Number: 38-06054
Issue
Date
Orig. of
REV.
**
ECN NO.
110213
122304
349775
Change Description of Change
12/16/01
12/27/02
See ECN
SZV
RBI
Change from Spec number: 38-00743 to 38-06054
*A
Power up requirements added to Maximum Ratings Information
Added Pb-Free Information
*B
RUY
Document #: 38-06054 Rev. *B
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