CY7C1006L-12VC [CYPRESS]
Standard SRAM, 256KX4, 12ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28;
| 型号： | CY7C1006L-12VC |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 256KX4, 12ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28 静态存储器 光电二极管 |
| 文件： | 总9页 (文件大小：251K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
006
CY7C106
CY7C1006
256K x 4 Static RAM
an active LOW output enable (OE), and three-state drivers.
These devices have an automatic power-down feature that re-
duces power consumption by more than 65% when the devic-
es are deselected.
Features
• High speed
— tAA = 12 ns
• CMOS for optimum speed/power
• Low active power
Writing to the devices is accomplished by taking chip enable
(CE) and write enable (WE) inputs LOW. Data on the four I/O
pins (I/O0 through I/O3) is then written into the location speci-
fied on the address pins (A0 through A17).
— 910 mW
• Low standby power
— 275 mW
Reading from the devices is accomplished by taking chip en-
able (CE) and output enable (OE) LOW while forcing write en-
able (WE) HIGH. Under these conditions, the contents of the
memory location specified by the address pins will appear on
the four I/O pins.
• 2.0V data retention (optional)
— 100 µW
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
The four input/output pins (I/O0 through I/O3) are placed in a
high-impedance state when the devices are deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE and WE LOW).
Functional Description
The CY7C106 and CY7C1006 are high-performance CMOS
static RAMs organized as 262,144 words by 4 bits. Easy mem-
ory expansion is provided by an active LOW chip enable (CE),
The CY7C106 is available in a standard 400-mil-wide SOJ; the
CY7C1006 is available in a standard 300-mil-wide SOJ.
Logic Block Diagram
Pin Configuration
SOJ
Top View
28
27
26
1
2
3
4
5
6
A
V
CC
0
A
A
17
A
16
A
15
1
A
2
3
A
25
24
A
A
14
A
13
A
12
4
23
22
A
5
A
7
8
9
10
11
12
13
6
A
21
20
19
18
17
A
7
11
INPUTBUFFER
A
NC
I/O
8
A
9
3
2
1
A
1
A
10
I/O
I/O
I/O
A
A
3
I/O
I/O
I/O
I/O
CE
OE
GND
2
3
2
1
0
16
15
0
14
WE
A
4
A
5
512 x 512 x 4
ARRAY
C106–2
A
6
A
7
A
8
A
9
POWER
DOWN
COLUMN
DECODER
CE
WE
OE
C106–1
Selection Guide
7C106-12
7C1006-12
7C106-15
7C1006-15
7C106-20
7C1006-20
7C106-25
7C1006-25
7C106-35
35
Maximum Access Time (ns)
12
15
20
25
Maximum Operating
Current (mA)
165
155
145
130
125
Maximum Standby
Current (mA)
50
30
30
30
25
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05033 Rev. **
Revised July 9, 1998
CY7C106
CY7C1006
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-Up Current..................................................... >200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC Relative to GND[1] .... –0.5V to +7.0V
Operating Range
Ambient
Range
Temperature[2]
VCC
DC Voltage Applied to Outputs
in High Z State[1]....................................–0.5V to VCC + 0.5V
Commercial
0°C to +70°C
5V ± 10%
DC Input Voltage[1] ................................–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range
7C106-12
7C1006-12
7C106-15
7C1006-15
7C106-20
7C1006-20
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
Min. Max. Min. Max. Min. Max. Unit
2.4
2.4
2.4
V
V
V
VOL
0.4
0.4
0.4
VIH
2.2
VCC
2.2
VCC
2.2
VCC
+0.3
+0.3
+0.3
VIL
IIX
Input LOW Voltage[1]
Input Load Current
–0.3
–1
0.8
+1
+5
–0.3
–1
0.8
+1
+5
–0.3
–1
0.8
+1
+5
V
GND < VI < VCC
µA
µA
IOZ
Output Leakage Current GND < VI < VCC
,
–5
–5
–5
Output Disabled
IOS
ICC
Output Short
VCC = Max., VOUT = GND
–300
–300
–300 mA
Circuit Current[3]
VCC Operating
Supply Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
165
155
140
30
mA
mA
mA
ISB1
Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > VIH,
VIN > VIH or VIN < VIL,
f = fMAX
50
30
ISB2
Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC
,
Com’l
10
2
10
2
10
2
CE > VCC – 0.3V,
VIN > VCC – 0.3V
or VIN < 0.3V, f=0
L
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. A is the “instant on” case temperature.
T
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Document #: 38-05033 Rev. **
Page 2 of 9
CY7C106
CY7C1006
Electrical Characteristics Over the Operating Range (continued)
7C106-25
7C1006-25
7C106-35
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[1]
Input Load Current
Test Conditions
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
Min.
Max.
Min.
Max.
Unit
V
VOH
VOL
VIH
VIL
2.4
2.4
0.4
VCC + 0.3
0.8
0.4
VCC + 0.3
0.8
V
2.2
–0.3
–1
2.2
–0.3
–1
V
V
IIX
GND < VI < VCC
+1
+1
µA
µA
IOZ
Output Leakage Current
GND < VI < VCC
,
–5
+5
–5
+5
Output Disabled
IOS
ICC
Output Short
VCC = Max., VOUT = GND
–300
–300
mA
mA
Circuit Current[3]
VCC Operating
Supply Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
130
125
ISB1
Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > VIH,
VIN > VIH or VIN < VIL,
f = fMAX
30
25
mA
mA
ISB2
Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC
,
Com’l
10
2
10
2
CE > VCC – 0.3V,
VIN > VCC – 0.3V
or VIN < 0.3V, f=0
L
Capacitance[4]
Parameter
CIN: Addresses
CIN: Controls
Description
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
Input Capacitance
7
pF
pF
pF
10
10
COUT
Output Capacitance
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R1 480Ω
R1 480Ω
ALL INPUT PULSES
90%
5V
5V
3.0V
GND
90%
10%
OUTPUT
OUTPUT
10%
R2
255Ω
R2
255Ω
30 pF
5 pF
< 3 ns
< 3 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
C106–3
C106–4
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
167Ω
1.73V
OUTPUT
Document #: 38-05033 Rev. **
Page 3 of 9
CY7C106
CY7C1006
[5]
Switching Characteristics Over the Operating Range
7C106-12
7C106-15
7C106-20
7C106-25
7C1006-12 7C1006-15 7C1006-20 7C1006-25
7C106-35
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
12
3
15
3
20
3
25
3
35
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[6,7]
CE LOW to Low Z[7]
CE HIGH to High Z[6,7]
CE LOW to Power-Up
CE HIGH to Power-Down
12
15
20
25
35
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
12
6
15
7
20
8
25
10
35
10
0
3
0
0
3
0
0
3
0
0
3
0
0
3
0
6
6
7
7
8
8
10
10
25
10
10
35
tPD
12
15
20
WRITE CYCLE[8,9]
tWC
tSCE
tAW
tHA
Write Cycle Time
12
10
10
0
15
12
12
0
20
15
15
0
25
20
20
0
35
25
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tSA
0
0
0
0
0
tPWE
tSD
10
7
12
8
15
10
0
20
15
0
25
20
0
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[7]
tHD
0
0
tLZWE
2
3
3
3
3
tHZWE
WE LOW to High Z[6,7]
6
7
8
10
10
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
OL/IOH and 30–pF load capacitance.
I
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
Document #: 38-05033 Rev. **
Page 4 of 9
CY7C106
CY7C1006
Data Retention Characteristics Over the Operating Range (L Version Only)
Parameter
VDR
ICCDR
Description
VCC for Data Retention
Conditions[10]
Min.
Max.
Unit
V
2.0
Data Retention Current
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V
50
µA
ns
[4]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
[4]
tR
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
> 2V
4.5V
4.5V
V
V
CC
DR
t
t
R
CDR
CE
C106–5
Switching Waveforms
Read Cycle No.1[11, 12]
1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
C106–6
Read Cycle No. 2 (OE Controlled)[12, 13]
ADDRESS
t
RC
CE
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PD
V
CC
ICC
ISB
t
PU
SUPPLY
CURRENT
50%
50%
C106–7
Notes:
10. No input may exceed VCC +0.5V.
11. Device is continuously selected, OE and CE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05033 Rev. **
Page 5 of 9
CY7C106
CY7C1006
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[14, 15]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
C106A–8
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
DATA I/O
DATA VALID
t
HZOE
C106–9
Notes:
14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
15. Data I/O is high impedance if OE = VIH
.
Document #: 38-05033 Rev. **
Page 6 of 9
CY7C106
CY7C1006
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[9, 15]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
t
PWE
SA
WE
t
t
HD
SD
DATA I/O
DATA VALID
t
t
LZWE
HZWE
C106–10
Truth Table
CE
H
L
OE
X
WE
X
Input/Output
High Z
Mode
Power
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
Power-Down
Read
)
L
H
Data Out
Data In
High Z
)
L
X
L
Write
)
L
H
H
Selected, Outputs Disabled
)
Ordering Information
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
Package Type
12
CY7C106–12VC
CY7C1006–12VC
CY7C106–15VC
CY7C1006–15VC
CY7C106–20VC
CY7C1006–20VC
CY7C106–25VC
CY7C1006–25VC
CY7C106–35VC
V28
V21
V28
V21
V28
V21
V28
V21
V28
28-Lead (400-Mil) Molded SOJ
28-Lead (300-Mil) Molded SOJ
28-Lead (400-Mil) Molded SOJ
28-Lead (300-Mil) Molded SOJ
28-Lead (400-Mil) Molded SOJ
28-Lead (300-Mil) Molded SOJ
28-Lead (400-Mil) Molded SOJ
28-Lead (300-Mil) Molded SOJ
28-Lead (400-Mil) Molded SOJ
Commercial
Commercial
Commercial
Commercial
Commercial
15
20
25
35
Contact factory for “L” version availability.
Document #: 38-05033 Rev. **
Page 7 of 9
CY7C106
CY7C1006
Package Diagrams
28-Lead (300-Mil) Molded SOJ V21
51-85031-B
28-Lead (400-Mil) Molded SOJ V28
51-85032-A
Document #: 38-05033 Rev. **
Page 8 of 9
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C106
CY7C1006
Document Title: CY7C106, CY7C1006 256K x 4 Static RAM
Document Number: 38-05033
REV.
ECN NO.
Issue Date
Orig. of Change
Description of Change
Change from Spec #: 38-00230 to 38-05033
**
106827
06/12/01
SZV
Document #: 38-05033 Rev. **
Page 9 of 9
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