CY7C1007-15VI [CYPRESS]
1M x 1 Static RAM; 1M ×1静态RAM
| 型号： | CY7C1007-15VI |
| 厂家： | 
CYPRESS |
| 描述： | 1M x 1 Static RAM |
| 文件： | 总8页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C107
CY7C1007
1M x 1 Static RAM
memory expansion is provided by an active LOW Chip Enable
(CE) and three-state drivers. These devices have an automatic
power-down feature that reduces power consumption by more
than 65% when deselected.
Features
• High speed
— t = 12 ns
AA
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the input pin
• CMOS for optimum speed/power
• Low active power
— 825 mW
(D ) is written into the memory location specified on the ad-
IN
dress pins (A through A ).
0
19
• Low standby power
— 275 mW
Reading from the devices is accomplished by taking Chip En-
able (CE) LOW while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location speci-
• 2.0V data retention (optional)
fied by the address pins will appear on the data output (D
pin.
)
OUT
100
W
µ
—
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
The output pin (D
) is placed in a high-impedance state
OUT
when the device is deselected (CE HIGH) or during a write
operation (CE and WE LOW).
Functional Description
The CY7C107 and CY7C1007 are high-performance CMOS
static RAMs organized as 1,048,576 words by 1 bit. Easy
The CY7C107 is available in a standard 400-mil-wide SOJ; the
CY7C1007 is available in a standard 300-mil-wide SOJ.
Logic Block Diagram
Pin Configuration
SOJ
Top View
D
IN
28
27
26
1
2
3
4
5
6
A
A
A
A
A
A
V
CC
10
11
12
13
14
15
A
9
A
8
25
24
A
7
INPUT BUFFER
A
6
A
A0
23
22
5
A1
A2
A3
A4
A5
A6
A7
A8
7
8
9
10
11
12
13
NC
A
4
21
20
19
18
17
A
17
NC
16
A
A
3
A
19
A
2
18
512x2048
ARRAY
A
A
1
D
OUT
A
0
D
OUT
WE
GND
16
15
D
IN
14
CE
107-2
POWER
DOWN
COLUMN
DECODER
CE
WE
107-1
Selection Guide
7C107-12
7C107-15
7C107-20
7C107-25
7C1007-12
7C1007-15
7C1007-20
7C1007-25
7C107-35
35
Maximum Access Time (ns)
12
15
20
25
Maximum Operating
Current (mA)
150
135
125
120
110
Maximum Standby
Current (mA)
50
40
30
30
25
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
December 1992 – Revised September 3, 1999
CY7C107
CY7C1007
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ..................................... −65°C to +150°C
Latch-Up Current..................................................... >200 mA
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Operating Range
[1]
Supply Voltage on V Relative to GND .....−0.5V to +7.0V
Ambient
CC
[2]
Range
Commercial
Industrial
Temperature
0°C to +70°C
−40°C to +85°C
V
CC
DC Voltage Applied to Outputs
[1]
5V ± 10%
5V ± 10%
in High Z State ....................................... −0.5V to V + 0.5V
CC
[1]
DC Input Voltage .................................... −0.5V to V + 0.5V
CC
Electrical Characteristics Over the Operating Range
7C107-12
7C1007-12
7C107-15
7C1007-15
7C107-20
7C1007-20
Parameter
Description
Output HIGH
Voltage
Test Conditions
Min.
Max.
Min.
Max.
Min.
Max.
Unit
V
V
V
= Min., I = −4.0 mA 2.4
2.4
2.4
V
OH
OL
IH
CC
CC
OH
V
V
V
Output LOW
Voltage
= Min., I = 8.0 mA
0.4
0.4
0.4
V
V
V
OL
Input HIGH
Voltage
2.2
V
+
2.2
V
+
2.2
V
+
CC
CC
CC
0.3
0.3
0.3
Input LOW
−0.3
0.8
−0.3
0.8
−0.3
0.8
IL
[1]
Voltage
I
I
Input Load Current
GND < V < V
CC
−1
–5
+1
+5
−1
–5
+1
+5
−1
–5
+1
+5
µA
µA
IX
I
Output Leakage
Current
GND < V < V
,
OZ
OS
CC
I
CC
Output Disabled
I
I
Output Short
Circuit Current
V
= Max., V
= GND
−300
−300
−300
mA
mA
CC
OUT
[3]
V
Operating
V
I
OUT
= Max.,
= 0 mA,
150
135
125
CC
CC
Supply Current
f = f
= 1/t
MAX
RC
I
I
Automatic CE
Power-Down
Current— TTL Inputs f = f
Max. V , CE > V ,
50
2
40
2
30
2
mA
mA
SB1
SB2
CC
IH
V
>V or V < V ,
IN
IH
IN
IL
MAX
Automatic CE
Power-Down
Current—
Max. V
,
CC
CE > V – 0.3V,
CC
V
> V – 0.3V or
IN
CC
CMOS Inputs
V
< 0.3V, f = 0
IN
Notes:
1. IL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the “instant on” case temperature.
V
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
2
CY7C107
CY7C1007
Electrical Characteristics Over the Operating Range (continued)
7C107-25
7C1007-25
7C107-35
Parameter
Description
Output HIGH
Test Conditions
= Min., I = −4.0 mA
Min.
Max.
Min.
Max.
Unit
V
V
V
2.4
2.4
V
OH
CC
CC
OH
Voltage
V
V
V
Output LOW Voltage
Input HIGH Voltage
= Min., I = 8.0 mA
0.4
0.4
V
V
OL
IH
IL
OL
2.2
−0.3
−1
V
+ 0.3
2.2
−0.3
−1
V
+ 0.3
CC
CC
[1]
Input LOW Voltage
0.8
0.8
V
I
I
Input Load Current
GND < V < V
CC
+1
+5
+1
+5
µA
µA
IX
I
Output Leakage
Current
GND < V < V ,
CC
−5
−5
OZ
OS
CC
I
Output Disabled
I
I
Output Short
Circuit Current
V
= Max., V
= GND
−300
−300
mA
mA
CC
OUT
[3]
V
Operating
V
I
OUT
= Max.,
= 0 mA,
120
110
CC
CC
Supply Current
f = f
= 1/t
MAX
RC
I
I
Automatic CE
Power-Down
Current—TTL Inputs
Max. V , CE > V ,
30
2
25
2
mA
mA
SB1
SB2
CC
IH
V
>V or V < V ,
IN
IH
IN
IL
f = f
MAX
Automatic CE
Max. V
,
CC
Power-Down
CE > V – 0.3V,
CC
Current—CMOS Inputs
V > V – 0.3V or
IN CC
V
< 0.3V, f = 0
IN
Capacitance[4]
Parameter
Description
Test Conditions
Max.
7
Unit
pF
C : Addresses
Input Capacitance
T = 25°C, f = 1 MHz,
A
IN
V
= 5.0V
CC
C : Controls
10
pF
IN
C
Output Capacitance
10
pF
OUT
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
3
CY7C107
CY7C1007
AC Test Loads and Waveforms
R1 480
R1 480
Ω
Ω
5V
5V
ALL INPUT PULSES
3.0V
GND
OUTPUT
OUTPUT
90%
10%
90%
10%
ns
R2
255
R2
255
30 pF
5 pF
Ω
Ω
3 ns
≤
3
≤
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
107-4
(a)
(b)
107-3
Equivalentto:
THÉVENIN EQUIVALENT
167
Ω
OUTPUT
1.73V
Switching Characteristics[5] Over the Operating Range
7C107-12
7C1007-12
7C107-15
7C1007-15
7C107-20
7C1007-20
7C107-25
7C1007-25
7C107-35
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Unit
READ CYCLE
t
t
t
Read Cycle Time
12
3
15
3
20
3
25
3
35
3
ns
ns
ns
RC
Address to Data Valid
12
15
20
25
35
AA
Data Hold from Address
Change
OHA
t
t
t
t
t
CE LOW to Data Valid
12
6
15
7
20
8
25
10
25
35
10
35
ns
ns
ns
ns
ns
ACE
LZCE
HZCE
PU
[6]
CE LOW to Low Z
3
0
3
0
3
0
3
0
3
0
[6, 7]
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
12
15
20
PD
[8]
WRITE CYCLE
t
t
t
Write Cycle Time
12
10
10
15
12
12
20
15
15
25
20
20
35
25
25
ns
ns
ns
WC
SCE
AW
CE LOW to Write End
Address Set-Up to Write
End
t
Address Hold from Write
End
0
0
0
0
0
0
0
0
0
0
ns
ns
HA
SA
t
Address Set-Up to Write
Start
t
t
t
t
t
WE Pulse Width
10
7
12
8
15
10
0
20
15
0
25
20
0
ns
ns
ns
ns
ns
PWE
Data Set-Up to Write End
Data Hold from Write End
SD
0
0
HD
[6]
WE HIGH to Low Z
3
3
3
3
3
LZWE
[6, 7]
WE LOW to High Z
6
7
8
10
10
HZWE
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
OL/IOH and 30-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device.
7. HZCE and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
I
t
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WEmust be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
4
CY7C107
CY7C1007
Data Retention Characteristics Over the Operating Range (L Version Only)
[9]
Parameter
Description
for Data Retention
CC
Conditions
Min.
Max.
Unit
V
V
V
2.0
DR
I
t
t
Data Retention Current
V
= V = 2.0V,
50
µA
ns
CCDR
CC
DR
CE > V – 0.3V,
[4]
CC
Chip Deselect to Data Retention Time
Operation Recovery Time
0
CDR
V
> V – 0.3 or
IN
CC
[4]
R
V
< 0.3V
t
ns
IN
RC
Data Retention Waveform
DATA RETENTION MODE
> 2V
V
CC
4.5V
4.5V
V
DR
t
t
R
CDR
CE
107-5
Switching Waveforms
[10, 11]
Read Cycle No. 1
t
RC
ADDRESS
t
AA
t
OHA
PREVIOUS DATA VALID
DATA VALID
DATA OUT
107-6
[11, 12]
Read Cycle No. 2
ADDRESS
CE
t
RC
t
ACE
t
t
HZCE
LZCE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
PD
t
PU
V
CC
ICC
ISB
SUPPLY
CURRENT
50%
50%
107-7
Notes:
9. No input may exceed VCC + 0.5V.
10. Device is continuously selected, CE = VIL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
5
CY7C107
CY7C1007
Switching Waveforms (continued)
[13]
Write Cycle No. 1 (CE Controlled)
t
WC
ADDRESS
t
SA
t
SCE
CE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
107-8
[13]
Write Cycle No. 2 (WE Controlled)
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
DATA IN
DATA VALID
t
t
LZWE
HZWE
HIGH IMPEDANCE
DATA OUT
DATA UNDEFINED
107-9
Note:
13. If CEgoes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
6
CY7C107
CY7C1007
Truth Table
CE
H
WE
D
Mode
Power-Down
Power
OUT
X
H
L
High Z
Standby (I
)
SB
L
Data Out
High Z
Read
Write
Active (I )
CC
L
Active (I
)
CC
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C107-12VC
Package Type
12
V28
V21
V28
V21
V28
V21
V28
V21
V28
V21
28-Lead (400-Mil) Molded SOJ
28-Lead (300-Mil) Molded SOJ
28-Lead (400-Mil) Molded SOJ
28-Lead (300-Mil) Molded SOJ
28-Lead (400-Mil) Molded SOJ
28-Lead (300-Mil) Molded SOJ
28-Lead (400-Mil) Molded SOJ
28-Lead (300-Mil) Molded SOJ
28-Lead (400-Mil) Molded SOJ
28-Lead (300-Mil) Molded SOJ
Commercial
CY7C1007-12VC
CY7C107-15VC
CY7C1007-15VC
CY7C107-15VI
CY7C1007-15VI
CY7C107-20VC
CY7C1007-20VC
CY7C107-25VC
CY7C1007-25VC
15
15
20
25
Commercial
Industrial
Commercial
Commercial
Contact factory for “L” version availability.
Document #: 38-00232-C
Package Diagrams
28-Lead (300-Mil) Molded SOJ V21
51-85031-B
7
CY7C107
CY7C1007
Package Diagrams (continued)
28-Lead (400-Mil) Molded SOJ V28
51-85032-A
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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