CY7C1011CV33-12ZXCT [CYPRESS]
Standard SRAM, 128KX16, 12ns, CMOS, PDSO44, LEAD FREE, TSOP2-44;
| 型号： | CY7C1011CV33-12ZXCT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 128KX16, 12ns, CMOS, PDSO44, LEAD FREE, TSOP2-44 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总11页 (文件大小：352K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1011CV33
2-Mbit (128K x 16) Static RAM
Features
Functional Description
• Pin equivalent to CY7C1011BV33
• High speed
The CY7C1011CV33 is a high-performance CMOS Static
RAM organized as 131,072 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
— tAA = 10 ns
• Low active power
— 360 mW (max.)
• Data Retention at 2.0
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Easy memory expansion with CE and OE features
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
• Available in Pb-free and non Pb-free 44-pin TSOP II,
44-pin TQFP and non Pb-free 48-ball VFBGA packages
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1011CV33 is available in a standard 44-pin TSOP
II package with center power and ground pinout, a 44-pin Thin
Plastic Quad Flatpack (TQFP), as well as a 48-ball fine-pitch
ball grid array (VFBGA) package.
Logic Block Diagram
Pin Configuration
TSOP II
Top View
INPUT BUFFER
44
1
A
4
A
5
A
0
43
42
41
40
39
38
A
A
2
3
4
5
6
3
6
A
1
A
A
2
7
A
2
OE
A
1
I/O0–I/O7
128K x 16
ARRAY
A
3
BHE
BLE
I/O
I/O
I/O
A
0
A
4
CE
A
I/O8–I/O15
5
I/O
7
0
15
A
6
37
36
35
34
33
I/O
I/O
8
1
2
14
13
12
A
7
9
A
8
10
11
12
13
I/O
V
SS
I/O
3
CC
V
SS
V
V
CC
COLUMN
DECODER
32
I/O
I/O
I/O
4
5
6
7
11
10
31
30
29
28
I/O
I/O
I/O
14
15
16
I/O
I/O
9
8
WE 17
NC
A
18
19
20
21
22
27
26
25
16
15
A
BHE
8
A
A
A
WE
CE
OE
9
A
11
14
10
A
A
12
24
23
13
BLE
A
NC
Cypress Semiconductor Corporation
Document #: 38-05232 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 6, 2006
CY7C1011CV33
Selection Guide
–10
10
–12
12
–15
15
Unit
ns
Maximum Access Time
Maximum Operating Current
Com’l
Ind’l
90
85
95
10
80
90
10
mA
100
10
Maximum CMOS Standby Current Com’l/Ind’l
mA
Pin Configurations
44-pin TQFP
(Top View)
1
33
32
31
30
29
28
27
26
25
24
23
I/O
15
1
2
3
4
5
6
7
8
9
CE
I/O
I/O
14
0
I/O
I/O
13
1
I/O
12
I/O
2
V
SS
I/O
3
V
CC
V
CC
I/O
11
V
SS
I/O
10
I/O
4
I/O
9
I/O
5
I/O
8
I/O
10
11
6
NC
I/O
7
48-ball VFBGA
(Top View)
1
2
4
3
5
6
A
A
2
A
NC
OE
BLE
0
1
A
B
C
A
A
4
I/O BHE
CE
I/O
I/O
0
3
8
A
A
6
I/O I/O
I/O
5
9
10
1
2
NC
V
V
A
7
I/O
I/O
3
CC
D
E
F
SS
11
A
V
CC
NC
V
I/O
I/O
SS
16
12
4
A
A
15
I/O
I/O
I/O
I/O
14
13
5
14
6
A
A
G
H
I/O
NC
WE
I/O
13
12
15
7
A
A
A10
A
NC
NC
11
9
8
Document #: 38-05232 Rev. *E
Page 2 of 11
CY7C1011CV33
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current......................................................>200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V
Ambient
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VCC
DC Voltage Applied to Outputs
in High-Z State[1] ....................................–0.5V to VCC + 0.5V
3.3V ± 0.3V
DC Input Voltage[1].................................–0.5V to VCC + 0.5V
DC Electrical Characteristics Over the Operating Range
–10
–12
–15
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
Min. Max. Min. Max. Min. Max. Unit
2.4
2.4
2.4
V
V
V
VOL
0.4
0.4
0.4
VIH
2.0
VCC
2.0
VCC
2.0
VCC
+ 0.3
+ 0.3
+ 0.3
VIL
IIX
Input LOW Voltage[1]
–0.3
–1
0.8
+1
+1
–0.3
–1
0.8
+1
+1
–0.3
–1
0.8
+1
+1
V
Input Leakage Current GND < VI < VCC
µA
µA
IOZ
Output Leakage Current GND < VOUT < VCC
,
–1
–1
–1
Output Disabled
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
Com’l
Ind’l
90
100
40
85
95
40
80
90
40
mA
mA
mA
ISB1
Automatic CE
Power-down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
V
IN < VIL, f = fMAX
Max. VCC
CE > VCC – 0.3V,
IN > VCC – 0.3V,
or VIN < 0.3V, f = 0
ISB2
Automatic CE
Power-down Current
—CMOS Inputs
,
Com’l/
Ind’l
10
10
10
mA
V
Capacitance[2]
Parameter
Description
Input Capacitance
I/O Capacitance
Test Conditions
Max.
Unit
pF
CIN
TA = 25°C, f = 1 MHz, VCC = 3.3V
8
8
COUT
pF
Thermal Resistance[2]
Parameter
Description
Test Conditions
TSOP II TQFP VFBGA Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
44.56
42.66
46.98 °C/W
ΘJC
Thermal Resistance
(Junction to Case)
10.75
14.64
9.63 °C/W
Notes:
1. V (min.) = –2.0V for pulse durations of less than 20 ns.
IL
2. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05232 Rev. *E
Page 3 of 11
CY7C1011CV33
AC Test Loads and Waveforms[3]
12-, 15-ns devices:
3.3V
10-ns devices:
R 317Ω
Z = 50Ω
OUTPUT
OUTPUT
30 pF
50Ω
1.5V
30 pF*
R2
351Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
(b)
(a)
High-Z characteristics:
R 317Ω
3.3V
OUTPUT
5 pF
ALL INPUT PULSES
3.0V
90%
10%
90%
10%
R2
351Ω
GND
(c)
Fall Time: 1 V/ns
Rise Time: 1 V/ns
(d)
AC Switching Characteristics Over the Operating Range[4]
–10
–12
–15
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle
[5]
tpower
VCC(typical) to the first access
Read Cycle Time
1
1
1
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
10
12
15
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z[6, 7]
CE LOW to Low-Z[7]
CE HIGH to High-Z[6, 7]
CE LOW to Power-up
CE HIGH to Power-down
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
10
12
15
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
3
3
3
10
5
12
6
15
7
0
3
0
0
3
0
0
3
0
5
5
6
6
7
7
tPD
10
5
12
6
15
7
tDBE
tLZBE
0
0
0
tHZBE
6
6
7
Notes:
3. AC characteristics (except High-Z) for all 10-ns parts are tested using the load conditions shown in (a). All other speeds are tested using the Thevenin load shown
in (b). High-Z characteristics are tested for all speeds using the test load shown in (d).
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
5. t
6. t
gives the minimum amount of time that the power supply should be at typical V values until the first memory access is performed.
POWER
CC
, t
, and t
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
HZOE HZCE
HZWE
7. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
Document #: 38-05232 Rev. *E
Page 4 of 11
CY7C1011CV33
AC Switching Characteristics Over the Operating Range[4] (continued)
–10
–12
–15
Parameter
Write Cycle[8, 9]
tWC
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
10
7
12
8
15
10
ns
ns
Write Cycle Time
tSCE
CE LOW to Write End
tAW
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
7
0
0
7
5
0
3
8
0
0
8
6
0
3
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHA
tSA
0
tPWE
tSD
10
7
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z[7]
tHD
0
tLZWE
tHZWE
tBW
3
WE LOW to High-Z[6, 7]
5
6
7
Byte Enable to End of Write
7
8
10
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
V
V
CC
DR
t
t
R
CDR
CE
Switching Waveforms
Read Cycle No. 1[10, 11]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes:
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
and t
.
SD
HZWE
10. Device is continuously selected. OE, CE, BHE and/or BHE = V
11. WE is HIGH for read cycle.
.
IL
Document #: 38-05232 Rev. *E
Page 5 of 11
CY7C1011CV33
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)[11, 12]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
BHE, BLE
t
LZOE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
t
LZCE
t
PD
I
CC
t
PU
50%
50%
I
SB
Write Cycle No. 1 (CE Controlled)[13, 14]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATAI/O
Notes:
12. Address valid prior to or coincident with CE transition LOW.
13. Data I/O is high-impedance if OE or BHE and/or BLE = V
.
IH
14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05232 Rev. *E
Page 6 of 11
CY7C1011CV33
Switching Waveforms (continued)
Write Cycle No. 2 (BLE or BHE Controlled)
t
WC
ADDRESS
t
SA
t
BW
BHE, BLE
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
HD
SD
DATAI/O
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
t
SCE
CE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
DATA I/O
t
LZWE
Document #: 38-05232 Rev. *E
Page 7 of 11
CY7C1011CV33
Truth Table
CE
H
L
OE WE BLE
BHE
X
I/O0–I/O7
High-Z
I/O8–I/O15
High-Z
Mode
Power
X
L
X
H
H
H
L
X
L
Power-down
Read All Bits
Standby (ISB)
L
Data Out
Data Out
High-Z
Data Out
High-Z
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
)
)
L
L
L
H
L
Read Lower Bits Only
Read Upper Bits Only
Write All Bits
L
L
H
L
Data Out
Data In
High-Z
L
X
X
X
H
L
Data In
Data In
High-Z
L
L
L
H
L
Write Lower Bits Only
Write Upper Bits Only
Selected, Outputs Disabled
L
L
H
X
Data In
High-Z
L
H
X
High-Z
Ordering Information
Speed
Package
Operating
Range
(ns)
Ordering Code
CY7C1011CV33-10ZC
CY7C1011CV33-10ZXC
CY7C1011CV33-10ZXI
CY7C1011CV33-10BVI
CY7C1011CV33-12ZC
CY7C1011CV33-12ZXC
CY7C1011CV33-12ZI
CY7C1011CV33-12ZXI
CY7C1011CV33-12AXI
CY7C1011CV33-12BVI
CY7C1011CV33-15ZXC
CY7C1011CV33-15AI
Name
Package Type
10
51-85087
44-pin TSOP II
Commercial
44-pin TSOP II (Pb-Free)
44-pin TSOP II (Pb-Free)
48-ball (6 x 8 x 1 mm) VFBGA
44-pin TSOP II
Industrial
51-85150
51-85087
12
15
Commercial
Industrial
44-pin TSOP II (Pb-Free)
44-pin TSOP II
44-pin TSOP II (Pb-Free)
44-pin TQFP (Pb-Free)
48-ball (6 x 8 x 1 mm) VFBGA
44-pin TSOP II (Pb-Free)
44-pin TQFP
51-85064
51-85150
51-85087
51-85064
Commercial
Industrial
Document #: 38-05232 Rev. *E
Page 8 of 11
CY7C1011CV33
Package Diagrams
44-Pin TSOP II (51-85087)
51-85087-*A
44-pin Thin Plastic Quad Flat Pack (51-85064)
12.00 0.2ꢀ SQ
10.00 0.10 SQ
44
34
0° MIN.
1
33
0.37 0.0ꢀ
R. 0.08 MIN.
0.20 MAX.
STAND-OFF
0.0ꢀ MIN.
0.1ꢀ MAX.
0.2ꢀ
GAUGE PLANE
R. 0.08 MIN.
0.20 MIN.
0-7°
0.20 MIN.
1.00 REF.
0.60 0.1ꢀ
0.80
B.S.C.
11
23
DETAIL
A
12
22
NOTE:
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.2ꢀ mm) PER SIDE
12° 1°
(8X)
SEATING PLANE
1.60 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
1.40 0.0ꢀ
0.10
0.20 MAX.
51-85064-*C
SEE DETAIL
A
Document #: 38-05232 Rev. *E
Page 9 of 11
CY7C1011CV33
Package Diagrams (continued)
48-ball VFBGA (6 x 8 x 1 mm) (51-85150)
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.0ꢀ M C
Ø0.2ꢀ M C A B
A1 CORNER
Ø0.30 0.0ꢀ(48X)
1
2
3
4
ꢀ
6
6
ꢀ
4
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.87ꢀ
A
A
0.7ꢀ
B
6.00 0.10
3.7ꢀ
B
6.00 0.10
0.1ꢀ(4X)
51-85150-*D
SEATING PLANE
C
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05232 Rev. *E
Page 10 of 11
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1011CV33
Document History Page
Document Title: CY7C1011CV33, 2-Mbit (128K x 16) Static RAM
Document Number: 38-05232
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
117132
118057
119702
Description of Change
07/31/02
08/19/02
10/11/02
HGK
HGK
DFP
New Data Sheet
*A
Pin configuration for 48-ball FBGA correction
*B
Updated FBGA to VFBGA; updated package code on page 8 to BV48A.
Updated address pinouts on page 1 to A0 to A16. Updated CMOS standby
current on page 1 from 8 to 10 mA
*C
*D
386106
498501
See ECN
See ECN
PCI
Added lead-free parts in Ordering Information Table
NXR
Corrected typo in the Logic Block Diagram on page# 1
Incuded the Maximum Ratings for Static Discharge Voltage and Latch up
Current on page# 3
Changed the description of IIX from Input Load Current to
Input Leakage Current in DC Electrical Characteristics table
Updated the Ordering Information Table
*E
522620
See ECN
VKN
Added Thermal Resistance Table
Document #: 38-05232 Rev. *E
Page 11 of 11
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