CY7C1012AV33-8BGCT [CYPRESS]
Standard SRAM, 512KX24, 8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119;
| 型号： | CY7C1012AV33-8BGCT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 512KX24, 8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119 静态存储器 内存集成电路 |
| 文件： | 总14页 (文件大小：384K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1012AV33
512 K × 24 Static RAM
512
K × 24 Static RAM
Features
Functional Description
■ High speed
❐ tAA = 8 ns
The CY7C1012AV33 is a high-performance CMOS static RAM
organized as 512 K words by 24 bits. Each data byte is
separately controlled by the individual chip selects (CE0, CE1,
CE2). CE0 controls the data on the I/O0–I/O7, while CE1 controls
the data on I/O8–I/O15, and CE2 controls the data on the data
pins I/O16–I/O23. This device has an automatic power-down
feature that significantly reduces power consumption when
deselected.
■ Low active power
❐ 1080 mW (max)
■ Operating voltages of 3.3 ± 0.3 V
■ 2.0 V data retention
Writing the data bytes into the SRAM is accomplished when the
chip select controlling that byte is LOW and the write enable input
(WE) input is LOW. Data on the respective input/output (I/O) pins
is then written into the location specified on the address pins
(A0–A18). Asserting all of the chip selects LOW and write enable
LOW will write all 24 bits of data into the SRAM. Output enable
(OE) is ignored while in WRITE mode.
■ Automatic power-down when deselected
■ TTL-compatible inputs and outputs
■ Easy memory expansion with CE0, CE1 and CE2 features
■ Available in non Pb-free 119 ball PBGA.
Data bytes can also be individually read from the device.
Reading a byte is accomplished when the chip select controlling
that byte is LOW and write enable (WE) HIGH while output
enable (OE) remains LOW. Under these conditions, the contents
of the memory location specified on the address pins will appear
on the specified data input/output (I/O) pins. Asserting all the chip
selects LOW will read all 24 bits of data from the SRAM.
The 24 I/O pins (I/O0–I/O23) are placed in a high-impedance
state when all the chip selects are HIGH or when the output
enable (OE) is HIGH during a READ mode. For further details,
refer to the truth table of this data sheet.
The CY7C1012AV33 is available in a standard 119-ball PBGA.
For a complete list of related documentation, click here.
Functional Block Diagram
INPUT BUFFER
A
0
A
1
A
2
I/O –I/O
0
7
A
3
512K x 24
ARRAY
A
4
I/O –I/O
8
15
A
5
A
6
I/O –I/O
16
23
A
7
A
8
A
9
CE , CE , CE
2
0
1
COLUMN
DECODER
WE
OE
CONTROL LOGIC
Cypress Semiconductor Corporation
Document Number: 38-05254 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 18, 2014
CY7C1012AV33
Contents
Selection Guide ................................................................3
Pin Configurations ...........................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
DC Electrical Characteristics ..........................................4
Capacitance ......................................................................5
AC Test Loads and Waveforms .......................................5
AC Switching Characteristics .........................................6
Switching Waveforms ......................................................7
Truth Table ........................................................................9
Ordering Information ......................................................10
Ordering Code Definitions .........................................10
Package Diagram ............................................................11
Acronyms ........................................................................12
Document Conventions .................................................12
Units of Measure .......................................................12
Document History Page .................................................13
Sales, Solutions, and Legal Information ......................14
Worldwide Sales and Design Support .......................14
Products ....................................................................14
PSoC® Solutions ......................................................14
Cypress Developer Community .................................14
Technical Support .....................................................14
Document Number: 38-05254 Rev. *J
Page 2 of 14
CY7C1012AV33
Selection Guide
Description
-8
8
Unit
ns
Maximum Access Time
Maximum Operating Current
Commercial
300
300
50
mA
Industrial
Maximum CMOS Standby Current
Commercial / Industrial
mA
Pin Configurations
[1, 2]
Figure 1. 119-ball PBGA pinout (Top View)
1
2
3
4
5
6
7
A
B
NC
NC
A
A
A
A
A
NC
A
A
CE0
NC
A
A
NC
C
D
E
F
I/O12
I/O13
I/O14
I/O15
I/O16
I/O17
NC
NC
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
A
CE1
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
NC
A
CE2
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
NC
A
NC
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
A
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
DNU
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
G
H
J
K
L
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
NC
M
N
P
R
T
A
WE
OE
A
U
NC
A
A
A
A
NC
Notes
1. NC pins are not connected on the die.
2. DNU pins have to be left floating or tied to VSS to ensure proper application.
Document Number: 38-05254 Rev. *J
Page 3 of 14
CY7C1012AV33
DC Voltage Applied to Outputs
Maximum Ratings
in high Z State [3] ................................ –0.5 V to VCC + 0.5 V
DC Input Voltage [3] ............................ –0.5 V to VCC + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with
Power Applied ......................................... –55 C to +125 C
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0 C to +70 C
VCC
Supply Voltage on
V
CC to Relative GND[3] ................................–0.5 V to +4.6 V
3.3 V 0.3 V
–40 C to +85 C
DC Electrical Characteristics
Over the Operating Range
-8
Parameter
VOH
Description
Test Conditions [4]
Unit
Min
2.4
–
Max
–
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
VCC = Min, IOH = –4.0 mA
V
V
VOL
VIH
VCC = Min, IOL = 8.0 mA
0.4
2.0
–0.3
–1
VCC + 0.3
0.8
V
[3]
VIL
IIX
Input LOW Voltage
V
Input Leakage Current
Output Leakage Current
VCC Operating Supply Current
GND < VI < VCC
+1
A
A
mA
mA
mA
IOZ
ICC
GND < VOUT < VCC, Output Disabled
–1
+1
VCC = Max,
Commercial
Industrial
–
–
–
300
300
100
f = fMAX = 1/tRC
ISB1
ISB2
Automatic CE Power-down
Current – TTL Inputs
Max VCC, CE > VIH,
VIN > VIH or VIN < VIL, f = fMAX
Automatic CE Power-down
Current – CMOS Inputs
Max VCC
CE > VCC – 0.3 V,
IN > VCC – 0.3 V,
or VIN < 0.3 V, f = 0
,
Commercial /
Industrial
–
50
mA
V
Notes
3.
V
(min) = –2.0 V for pulse durations of less than 20 ns.
IL
4. CE refers to a combination of CE , CE , and CE . CE is active LOW when all three of these signals are active LOW at the same time.
0
1
2
Document Number: 38-05254 Rev. *J
Page 4 of 14
CY7C1012AV33
Capacitance
Parameter [5]
Description
Input Capacitance
I/O Capacitance
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 3.3 V
Max
8
Unit
pF
CIN
COUT
10
pF
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [6]
R1 317
50
3.3 V
= 1.5 V
VTH
OUTPUT
OUTPUT
Z = 50
30 pF*
0
R2
351
* Capacitive Load consists of all
5 pF
components of the test environment.
(a)
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
(b)
3.3 V
90%
10%
90%
10%
GND
Rise time > 1 V/ns
Fall time: > 1 V/ns
(c)
Notes
5. Tested initially and after any design or process changes that may affect these parameters.
6. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V (3.0 V). As soon as 1 ms (T
) after reaching the minimum
power
DD
operating V , normal SRAM operation can begin including reduction in V to the data retention (V , 2.0 V) voltage.
CCDR
DD
DD
Document Number: 38-05254 Rev. *J
Page 5 of 14
CY7C1012AV33
AC Switching Characteristics
Over the Operating Range
-8
Parameter [7]
Description
Unit
Min
Max
Read Cycle
[8]
tpower
tRC
VCC(typical) to the first access
Read Cycle Time
1
8
–
3
–
–
1
–
3
–
0
–
–
1
–
–
–
8
–
8
5
–
5
–
5
–
8
5
–
5
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data Hold from Address Change
CE1, CE2, and CE3 LOW to Data Valid
OE LOW to Data Valid
OE LOW to low Z[9]
OE HIGH to high Z[9]
CE1, CE2, and CE3 LOW to low Z[9]
CE1, CE2, or CE3 HIGH to high Z[9]
CE1, CE2, and CE3 LOW to power-up[10]
CE1, CE2, or CE3 HIGH to power-down[10]
Byte Enable to Data Valid
tPD
tDBE
tLZBE
tHZBE
Byte Enable to low Z[9]
Byte Disable to high Z[9]
Write Cycle[11, 12]
tWC
tSCE
tAW
Write Cycle Time
8
6
6
0
0
6
5
0
3
–
6
–
–
–
–
–
–
–
–
–
5
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE1, CE2, and CE3 LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tHA
tSA
tPWE
tSD
Data Set-up to Write End
Data Hold from Write End
WE HIGH to low Z[13]
tHD
tLZWE
tHZWE
tBW
WE LOW to high Z[13]
Byte Enable to End of Write
Notes
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified I /I
OL OH
and transmission line loads. Test conditions for the read cycle use output loading as shown in part (a) of the Figure 2, unless specified otherwise.
8. This part has a voltage regulator which steps down the voltage from 3 V to 2 V internally. t time has to be provided initially before a read/write operation is started.
power
9.
t
, t
, t
, t
, and t
, t
, t
, t
are specified with a load capacitance of 5 pF as in part (b) of Figure 2. Transition is measured 200 mV
HZOE HZCE HZWE HZBE
LZOE LZCE LZWE LZBE
from steady-state voltage.
10. These parameters are guaranteed by design and are not tested.
11. The internal write time of the memory is defined by the overlap of CE , CE , and CE LOW and WE LOW. The chip enables must be active and WE must be LOW
1
2
3
to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge
of the signal that terminates the write.
12. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
13. t
, t
, t
, t
, and t
, t , t , t are specified with a load capacitance of 5 pF as in part (b) of Figure 2 on page 5. Transition is measured
HZOE HZCE HZWE HZBE
LZOE LZCE LZWE LZBE
200 mV from steady-state voltage.
Document Number: 38-05254 Rev. *J
Page 6 of 14
CY7C1012AV33
Switching Waveforms
Figure 3. Read Cycle No. 1 [14, 15]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 4. Read Cycle No. 2 (OE Controlled) [15, 16, 17]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
t
PU
V
CC
50%
50%
SUPPLY
CURRENT
ISB
Figure 5. Write Cycle No. 1 (CE Controlled) [17, 18, 19]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Notes
14. Device is continuously selected. OE, CE = V .
IL
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE transition LOW.
17. CE refers to a combination of CE , CE , and CE . CE is active LOW when all three of these signals are active LOW at the same time.
0
1
2
18. Data I/O is high impedance if OE = V
.
IH
19. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document Number: 38-05254 Rev. *J
Page 7 of 14
CY7C1012AV33
Switching Waveforms (continued)
Figure 6. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [20, 21]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
t
PWE
SA
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 22
t
HZOE
Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [21, 23]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 22
DATA I/O
DATA VALID
t
t
LZWE
HZWE
Notes
20. Data I/O is high impedance if OE = V
.
IH
21. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
22. During this period the I/Os are in the output state and input signals should not be applied.
23. CE refers to a combination of CE , CE , and CE . CE is active LOW when all three of these signals are active LOW at the same time.
0
1
2
Document Number: 38-05254 Rev. *J
Page 8 of 14
CY7C1012AV33
Truth Table
CE0
H
L
CE1
H
H
L
CE2
H
H
H
L
OE
X
L
WE
X
I/O0–I/O23
Mode
Power
High Z
Power-down
Read
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
H
H
H
H
L
I/O0–I/O7 Data Out
I/O8–I/O15 Data Out
I/O16–I/O23 Data Out
Full Data Out
)
H
H
L
L
Read
)
H
L
L
Read
)
L
L
Read
)
L
H
L
H
H
L
X
X
X
X
H
I/O0–I/O7 Data In
I/O8–I/O15 Data In
I/O16–I/O23 Data In
Full Data In
Write
)
H
H
L
L
Write
)
H
L
L
Write
)
L
L
Write
)
L
L
L
H
High Z
Selected, Outputs Disabled
)
Document Number: 38-05254 Rev. *J
Page 9 of 14
CY7C1012AV33
Ordering Information
Speed
Package
Diagram
Operating
Range
Ordering Code
(ns)
Package Type
8
CY7C1012AV33-8BGC
51-85115 119-ball (14 × 22 × 2.4 mm) PBGA
Commercial
Ordering Code Definitions
CY 7 C 1012 V33
C
A
BG
- 8
Temperature range: C = Commercial
BG = 119-ball PBGA
Speed Grade: 8 ns
V33 = 3.3 V
Process Technology: A 90 nm
Part Identifier
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05254 Rev. *J
Page 10 of 14
CY7C1012AV33
Package Diagram
Figure 8. 119-ball PBGA (14 × 22 × 2.4 mm) BG119 Package Outline, 51-85115
51-85115 *D
Document Number: 38-05254 Rev. *J
Page 11 of 14
CY7C1012AV33
Acronyms
Document Conventions
Units of Measure
Acronym
Description
CMOS
CE
Complementary Metal Oxide Semiconductor
Chip Enable
Symbol
°C
Unit of Measure
degree Celsius
megahertz
microampere
milliampere
millimeter
millisecond
millivolt
MHz
µA
mA
mm
ms
mV
mW
ns
I/O
Input/Output
OE
Output Enable
PBGA
SRAM
TTL
Plastic Ball Grid Array
Static Random Access Memory
Transistor-Transistor Logic
Write Enable
WE
milliwatt
nanosecond
percent
%
pF
picofarad
volt
V
W
watt
Document Number: 38-05254 Rev. *J
Page 12 of 14
CY7C1012AV33
Document History Page
Document Title: CY7C1012AV33, 512 K × 24 Static RAM
Document Number: 38-05254
Orig. of
Change
Rev.
ECN No.
Issue Date
Description of Change
**
113711
117057
117988
118992
03/11/02
07/31/02
09/03/02
09/19/02
NSL
New data sheet.
Removed 15-ns bin
Added 8-ns bin
*A
*B
*C
DFP
DFP
DFP
Change Cin (input capacitance) from 6 pF to 8 pF
Change Cout (output capacitance) from 8 pF to 10 pF
*D
*E
120382
492137
11/15/02
See ECN
DFP
NXR
Final data sheet. Added note 4 to “AC Test Loads and Waveforms”
Removed 12 ns speed bin from product offering
Included note #1 and 2 on page #2
Changed the description of IIX from Input Load Current to Input Leakage Cur-
rent in DC Electrical Characteristics table
Updated Ordering Information Table
*F
*G
*H
2896044
3097955
3086499
03/19/2010
11/30/2010
06/07/2011
AJU
PRAS
AJU
Updated Ordering Information Table
Updated Package Diagram
Added Sales, Solutions, and Legal Information
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Minor edits.
Updated Selection Guide (Removed -10 column).
Updated DC Electrical Characteristics (Removed -10 column).
Updated AC Switching Characteristics (Removed -10 column).
Updated in new template.
*I
4212876
4573215
12/06/2013
11/18/2014
VINI
VINI
Updated Package Diagram:
spec 51-85115 – Changed revision from *C to *D.
Updated in new template.
Completing Sunset Review.
*J
Added related documentation hyperlink in page 1.
Document Number: 38-05254 Rev. *J
Page 13 of 14
CY7C1012AV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
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psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Clocks & Buffers
Interface
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Community | Forums | Blogs | Video | Training
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© Cypress Semiconductor Corporation, 2002-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05254 Rev. *J
Revised November 18, 2014
Page 14 of 14
All products and company names mentioned in this document may be the trademarks of their respective holders.
相关型号：
CY7C1012AV33-8BGIT
Standard SRAM, 512KX24, 8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CYPRESS
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