CY7C1019DV33-10BVXI [CYPRESS]
1-Mbit (128K x 8) Static RAM; 1兆位（ 128K ×8）静态RAM
| 型号： | CY7C1019DV33-10BVXI |
| 厂家： | 
CYPRESS |
| 描述： | 1-Mbit (128K x 8) Static RAM |
| 文件： | 总11页 (文件大小：387K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1019DV33
1-Mbit (128K x 8) Static RAM
Features
Functional Description[1]
• Pin- and function-compatible with CY7C1019CV33
• High speed
The CY7C1019DV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
— tAA = 10 ns
• Low Active Power
— ICC = 60 mA @ 10 ns
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A16).
• Low CMOS Standby Power
— ISB2 = 3 mA
• 2.0V Data retention
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Center power/ground pinout
• Easy memory expansion with CE and OE options
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
• Available in Pb-free 32-pin 400-Mil wide Molded SOJ,
32-pin TSOP II and 48-ball VFBGA packages
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1019DV33 is available in Pb-free 32-pin 400-Mil
wide Molded SOJ, 32-pin TSOP II and 48-ball VFBGA
packages.
Logic Block Diagram
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
INPUTBUFFER
A
0
A
1
A
2
A
3
128K × 8
ARRAY
A
3
4
5
4
A
5
A
6
A
7
A
8
CE
WE
POWER
DOWN
6
7
COLUMN
DECODER
I/O
OE
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com
Cypress Semiconductor Corporation
Document #: 38-05481 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 8, 2006
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CY7C1019DV33
Selection Guide
–10 (Industrial)
Unit
ns
Maximum Access Time
10
60
3
Maximum Operating Current
Maximum Standby Current
mA
mA
Pin Configurations[2]
48-ball VFBGA
(Top View)
SOJ/TSOPII
Top View
1
2
4
3
5
6
A
A
7
A
NC
A
A
1
A
A
OE
32
NC
1
2
6
A
B
C
0
16
31
30
2
3
4
5
6
15
A
A
A
5
A
14
A
13
I/O NC
2
CE
NC
NC
NC
I/O
I/O
7
1
0
A
3
29
28
CE
A
A
A
I/O
NC
NC
I/O
OE
I/O
I/O
0
4
3
1
6
27
26
I/O
0
1
7
I/O
V
7
8
9
10
11
12
13
6
NC
NC
V
CC
V
SS
D
E
F
25
24
23
22
21
V
CC
SS
V
V
CC
I/O
SS
NC
V
CC
V
SS
NC
NC
I/O
I/O
2
3
5
4
I/O
A
A
A
11
I/O
I/O
5
14
4
2
WE
A
4
12
A
11
20
19
A
A
G
H
I/O
A
5
A
10
NC
A
WE
A8
12
15
3
14
15
16
A
6
A
9
A
8
18
17
A
A
A13
A
7
NC
NC
9
16
10
Note
2. NC pins are not connected on the die.
Document #: 38-05481 Rev. *D
Page 2 of 11
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CY7C1019DV33
DC Input Voltage[3] ................................ –0.3V to VCC + 0.3V
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current.....................................................> 200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[3] ... –0.3V to + 4.6V
Operating Range
Ambient
Range
VCC
Speed
DC Voltage Applied to Outputs
Temperature
in High-Z State[3] ....................................–0.3V to VCC + 0.3V
Industrial
–40°C to +85°C
3.3V ± 0.3V
10 ns
Electrical Characteristics Over the Operating Range
–10 (Industrial)
Parameter
Description
Test Conditions
Unit
Min.
Max.
VOH
VOL
VIH
VIL
IIX
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[3]
Input Leakage Current
Output Leakage Current
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
2.4
V
V
0.4
VCC + 0.3
0.8
2.0
–0.3
–1
V
V
GND < VI < VCC
+1
µA
µA
mA
mA
mA
mA
mA
IOZ
ICC
GND < VI < VCC, Output Disabled
–1
+1
VCC Operating Supply Current VCC = Max.,
IOUT = 0 mA,
100MHz
60
83MHz
66MHz
40MHz
55
f = fMAX = 1/tRC
45
30
ISB1
ISB2
Automatic CE Power-down
Current—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or VIN < VIL, f = fMAX
10
Automatic CE Power-down
Current—CMOS Inputs
Max. VCC, CE > VCC – 0.3V,
3
mA
VIN > VCC – 0.3V or VIN < 0.3V, f = 0
Note
3.
V (min.) = –2.0V and V (max) = V + 1V for pulse durations of less than 5 ns.
IL IH CC
Document #: 38-05481 Rev. *D
Page 3 of 11
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CY7C1019DV33
Capacitance[4]
Parameter
Description
Test Conditions
Max.
Unit
pF
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz, VCC = 3.3V
8
8
COUT
pF
Thermal Resistance[4]
Parameter
Description
Test Conditions
SOJ TSOP II VFBGA Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
56.29
62.22
36
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
38.14
21.43
9
°C/W
AC Test Loads and Waveforms[5]
ALL INPUT PULSES
3.0V
GND
Z = 50Ω
90%
10%
90%
OUTPUT
10%
50Ω
1.5V
30 pF*
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
Fall Time: 1 V/ns
Rise Time: 1 V/ns
(b)
(a)
High-Z characteristics:
R1 317Ω
3.3V
OUTPUT
5 pF
R2
351Ω
(c)
Notes
4. Tested initially and after any design or process changes that may affect these parameters.
5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
Document #: 38-05481 Rev. *D
Page 4 of 11
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CY7C1019DV33
Switching Characteristics Over the Operating Range [6]
–10 (Industrial)
Parameter
Description
Unit
Min.
Max.
Read Cycle
[7]
tpower
VCC(typical) to the first access
100
10
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read Cycle Time
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[8, 9]
CE LOW to Low Z[9]
CE HIGH to High Z[8, 9]
CE LOW to Power-Up
CE HIGH to Power-Down
10
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
3
10
5
0
3
0
5
5
[10]
tPU
[10]
tPD
10
Write Cycle[11, 12]
tWC
tSCE
tAW
Write Cycle Time
10
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
8
tHA
0
tSA
0
tPWE
tSD
7
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[9]
5
tHD
0
tLZWE
tHZWE
3
WE LOW to High Z[8, 9]
5
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
7.
8.
t
t
gives the minimum amount of time that the power supply should be at typical V values until the first memory access can be performed
P
O
W
E
R
C
C
, t
, and t
are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state.
HZOE HZCE
HZWE
9. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
10. This parameter is guaranteed by design and is not tested.
11. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
12. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
Document #: 38-05481 Rev. *D
Page 5 of 11
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CY7C1019DV33
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
Description
VCC for Data Retention
Data Retention Current
Conditions
Min.
Max.
Unit
V
2.0
VCC = VDR = 2.0V, CE > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
3
mA
[4]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
ns
[13]
tR
tRC
Data Retention Waveform
DATA RETENTION MODE
3.0V
3.0V
VDR > 2V
V
CC
t
t
R
CDR
CE
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[14, 15]
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[15, 16]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
V
CC
ICC
t
PU
SUPPLY
CURRENT
50%
50%
ISB
Notes
13. Full device operation requires linear V ramp from V to V
> 50 µs or stable at V > 50 µs.
CC(min.)
CC
DR
CC(min.)
14. Device is continuously selected. OE, CE = V .
IL
15. WE is HIGH for Read cycle.
16. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05481 Rev. *D
Page 6 of 11
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CY7C1019DV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[17, 18]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[17, 18]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
DATA VALID
IN
DATA I/O
NOTE 19
t
HZOE
Notes
17. Data I/O is high impedance if OE = V
.
IH
18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
19. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05481 Rev. *D
Page 7 of 11
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CY7C1019DV33
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[12, 18]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
DATA I/O
NOTE 19
DATA VALID
t
t
LZWE
HZWE
Truth Table
CE
H
L
OE
WE
X
I/O0–I/O7
Mode
Power
X
L
High Z
Power-Down
Read
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
H
Data Out
Data In
High Z
)
L
X
H
L
Write
)
L
H
Selected, Outputs Disabled
)
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
10
CY7C1019DV33-10VXI
CY7C1019DV33-10ZSXI
CY7C1019DV33-10BVXI
51-85033 32-pin (400-Mil) Molded SOJ (Pb-free)
51-85095 32-pin TSOP Type II (Pb-free)
51-85150 48-ball VFBGA (Pb-free)
Industrial
Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05481 Rev. *D
Page 8 of 11
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CY7C1019DV33
Package Diagrams
Figure 1. 32-pin (400-Mil) Molded SOJ (51-85033)
51-85033-A
51-85033-*B
Figure 2. 32-pin Thin Small Outline Package Type II (51-85095)
51-85095-**
Document #: 38-05481 Rev. *D
Page 9 of 11
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CY7C1019DV33
Package Diagrams (continued)
Figure 3. 48-ball VFBGA (6 x 8 x 1 mm) (51-85150)
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30 0.05ꢀ(48X
1
2
3
(
5
6
6
5
(
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.475
A
A
0.75
B
6.00 0.10
3.75
B
6.00 0.10
0.15ꢀ(8X
51-85150-*D
SEATING PLANE
C
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05481 Rev. *D
Page 10 of 11
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1019DV33
Document History Page
Document Title: CY7C1019DV33, 1-Mbit (128K x 8) Static RAM
Document Number: 38-05481
Orig. of
REV.
ECN NO. Issue Date
Description of Change
Advance Information data sheet for C9 IPP
Change
**
201560
233750
See ECN
See ECN
SWI
*A
RKF
DC parameters modified as per EROS (Spec # 01-02165 Rev *A)
Pb-free Offering in Ordering Information
*B
262950
See ECN
RKF
Added Data Retention Characteristics table
Added Tpower Spec in Switching Characteristics table
Shaded Ordering Information
*C
*D
307598
520652
See ECN
See ECN
RKF
VKN
Reduced Speed bins to -8 and -10 ns
Converted from Preliminary to Final
Removed Commercial Operating range
Removed 8 ns speed bin
Added ICC values for the frequencies 83MHz, 66MHz and 40MHz
Added 48-ball VFBGA package
Updated Thermal Resistance table
Updated Ordering Information table
Changed Overshoot spec from VCC+2V to VCC+1V in footnote #3
Document #: 38-05481 Rev. *D
Page 11 of 11
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