CY7C1021CV26_10 [CYPRESS]
1-Mbit (64 K × 16) Static RAM; 1兆位（ 64千× 16 ）静态RAM
| 型号： | CY7C1021CV26_10 |
| 厂家： | 
CYPRESS |
| 描述： | 1-Mbit (64 K × 16) Static RAM |
| 文件： | 总15页 (文件大小：518K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1021CV26
1-Mbit (64 K × 16) Static RAM
1-Mbit (64
K × 16) Static RAM
an automatic power-down feature that significantly reduces
power consumption when deselected.
Features
■ Temperature Range
❐ Automotive: –40 °C to 125 °C
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A15).
■ High speed
❐ tAA = 15 ns
■ Optimized voltage range: 2.5 V to 2.7 V
■ Low active power: 220 mW (Max)
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O9 to I/O16. See
the truth table at the end of this data sheet for a complete
description of Read and Write modes.
■ Automatic power-down when deselected
■ Independent control of upper and lower bits
■ CMOS for optimum speed/power
■ Available in Pb-free and non Pb-free 44-pin TSOP II , 44-pin
(400-Mil) Molded SOJ and Pb-free 48-ball FPBGA packages
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW, and WE LOW).
Functional Description
The CY7C1021CV26 is a high-performance CMOS static
RAM organized as 65,536 words by 16 bits. This device has
Logic Block Diagram
DATA IN DRIVERS
A7
A6
A5
A4
A3
A2
64K x 16
I/O1–I/O8
RAM Array
I/O9–I/O16
A1
A0
COLUMN DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document Number: 38-05589 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 1, 2010
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CY7C1021CV26
Contents
Selection Guide ................................................................3
Pin Configuration .............................................................3
Pin Definitions ..................................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................4
Thermal Resistance ..........................................................4
AC Test Loads and Waveforms .......................................5
Switching Characteristics ................................................5
Switching Waveforms ......................................................7
Read Cycle No. 1 ........................................................7
Read Cycle No. 2 (OE Controlled) ..............................7
Write Cycle No. 1 (CE Controlled) ...............................8
Write Cycle No. 2 (BLE or BHE Controlled) ................8
Write Cycle No. 3 (WE Controlled, LOW) ....................9
Truth Table ........................................................................9
Ordering Information ......................................................10
Ordering Code Definitions .........................................10
Package Diagrams ..........................................................11
Acronyms ........................................................................13
Document Conventions .................................................13
Units of Measure .......................................................13
Document History Page .................................................14
Sales, Solutions, and Legal Information ......................15
Worldwide Sales and Design Support .......................15
Products ....................................................................15
PSoC Solutions .........................................................15
Document Number: 38-05589 Rev. *E
Page 2 of 15
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CY7C1021CV26
Selection Guide[1]
–15
15
Unit
ns
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
80
mA
mA
10
Pin Configuration[2]
TSOP II -Top View
44
1
A
4
A
5
43
42
41
40
39
38
A
A
2
3
4
5
6
3
6
A
A
2
7
OE
A
1
BHE
BLE
I/O
A
0
CE
I/O
7
1
16
37
36
35
34
33
I/O
I/O
8
I/O
I/O
2
3
15
14
13
9
10
11
12
13
I/O
V
SS
I/O
4
CC
V
SS
V
V
CC
32
I/O
I/O
I/O
5
6
7
8
12
11
31
30
29
28
I/O
I/O
I/O
14
15
16
I/O
10
9
I/O
WE 17
NC
18
27
26
25
A
A
8
15
19
A
A
14
9
A
13
20
21
22
A
11
10
A
A
12
24
23
NC
NC
Pin Definitions
Pin Name Pin Number
I/O Type
Input
Description
A0–A15
1–5, 18–21,
24–27, 42–44
Address Inputs used to select one of the address locations.
Bidirectional Data I/O lines. Used as input or output lines depending on operation.
No Connects. This pin is not connected to the die.
I/O1–I/O16 7–10, 13–16, Input/Output
29–32, 35–38
NC
22, 23, 28
17
No Connect
Input/Control
WE
Write Enable Input, active LOW. When selected LOW, a Write is conducted. When
selected HIGH, a Read is conducted.
CE
6
Input/Control
Input/Control
Input/Control
Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH,
deselects the chip.
BHE, BLE 40, 39
Byte Write Select Inputs, active LOW. BHE controls I/O16–I/O9, BLE controls
I/O8–I/O1.
OE
41
Output Enable, active LOW. Controls the direction of the I/O pins. When LOW, the
I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are
tri-stated, and act as input data pins.
VSS
VCC
12, 34
11, 33
Ground
Ground for the device. Should be connected to ground of the system.
Power Supply Power Supply inputs to the device.
Notes
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ.)
2. NC pins are not connected on the die.
Document Number: 38-05589 Rev. *E
Page 3 of 15
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CY7C1021CV26
DC input voltage[3]............................... –0.5 V to VCC + 0.5 V
Current into outputs (LOW) ......................................... 20 mA
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Static discharge voltage...........................................> 2001 V
(per MIL-STD-883, method 3015)
Storage temperature ................................ –65 C to +150 C
Latch-up current .....................................................> 200 mA
Ambient temperature with
power applied ........................................... –55 C to +125 C
Supply voltage on VCC to relative GND[3].....–0.5 V to +4.6 V
Operating Range
Ambient
Range
Automotive
VCC
DC voltage applied to outputs
Temperature
in high Z state[3]...................................–0.5 V to VCC + 0.5 V
–40 C to +125 C 2.5 V–2.7 V
Electrical Characteristics
Over the Operating Range
–15
Parameter
Description
Test Conditions
VCC = Min, IOH = –1.0 mA
Unit
Min
2.3
–
Max
VOH
VOL
VIH
VIL
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage[3]
Input leakage current
Output leakage current
VCC operating supply current
–
0.4
V
V
VCC = Min, IOL = 1.0 mA
2.0
–0.3
–3
–3
–
VCC + 0.3
0.8
V
V
IIX
GND < VI < VCC
+3
A
A
mA
mA
IOZ
ICC
ISB1
GND < VI < VCC, output disabled
VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC
Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX
+3
80
Automatic CE Power-Down
Current —TTL inputs
–
15
ISB2
Automatic CE Power-Down
Current —CMOS inputs
Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V,
or VIN < 0.3 V, f = 0
–
10
mA
Capacitance[4]
Parameter
Description
Input capacitance
Output capacitance
Test Conditions
Max
Unit
pF
CIN
TA = 25 C, f = 1 MHz, VCC = 2.6 V
8
8
COUT
pF
Thermal Resistance[4]
Parameter
JA
Description
Test Conditions
TSOP-II
76.92
Unit
C/W
C/W
Thermal Resistance (Junction to Ambient) Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
JC
Thermal Resistance (Junction to Case)
15.86
Notes
3.
V (min.) = –2.0V and V (max) = V + 0.5 V for pulse durations of less than 20 ns.
IL IH CC
4. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05589 Rev. *E
Page 4 of 15
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CY7C1021CV26
AC Test Loads and Waveforms[5]
R1
1830
High Z characteristics:
ALL INPUT PULSES
R 317
2.6V
2.6 V
2.6V
90%
10%
90%
10%
OUTPUT
OUTPUT
R2
GND
30 pF
INCLUDING
JIG AND
R2
351
5 pF
1976
Fall Time: 1 V/ns
Rise Time: 1 V/ns
(b)
SCOPE
(c)
(a)
Switching Characteristics
Over the Operating Range[6]
–15
Parameter
Description
Unit
Min
Max
Read Cycle
tRC
Read cycle time
Address to data valid
15
–
3
–
–
0
–
3
–
0
–
–
0
–
–
15
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to low Z[7]
OE HIGH to high Z[7, 8]
CE LOW to low Z[7]
CE HIGH to high Z[7, 8]
CE LOW to power-up
CE HIGH to power-down
Byte enable to data valid
Byte enable to low Z
15
7
–
7
–
7
[9]
tPU
–
[9]
tPD
15
7
tDBE
tLZBE
tHZBE
–
Byte disable to high Z
7
Notes
5. AC characteristics (except high Z) are tested using the Thevenin load shown in Figure (a). High Z characteristics are tested for all speeds using the test load
shown in Figure (c)
6. Test conditions assume signal transition time of 2.6 ns or less, timing reference levels of 1.3 V, input pulse levels of 0 to 2.6 V.
7. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
8.
t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured 500 mV from steady-state voltage.
HZOE HZBE HZCE
HZWE
9. This parameter is guaranteed by design and is not tested.
Document Number: 38-05589 Rev. *E
Page 5 of 15
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CY7C1021CV26
Switching Characteristics
Over the Operating Range[6] (continued)
–15
Parameter
Description
Unit
Min
Max
Write Cycle[10]
tWC
tSCE
tAW
Write cycle time
15
10
10
0
–
–
–
–
–
–
–
–
–
7
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to write end
Address set-up to write end
Address hold from write end
Address set-up to write start
WE pulse width
tHA
tSA
0
tPWE
tSD
10
8
Data set-up to write end
Data hold from write end
WE HIGH to low Z[11]
WE LOW to high Z[11, 12]
Byte enable to end of write
tHD
0
tLZWE
tHZWE
tBW
3
–
9
Notes
10. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write,
and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
11. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
12. t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured 500 mV from steady-state voltage.
HZOE HZBE HZCE
HZWE
Document Number: 38-05589 Rev. *E
Page 6 of 15
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CY7C1021CV26
Switching Waveforms
Read Cycle No. 1[13, 14]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[14, 15]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
BHE, BLE
t
LZOE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
t
LZCE
t
PD
I
CC
t
PU
50%
50%
I
SB
Notes
13. Device is continuously selected. OE, CE, BHE and/or BLE = V .
IL
14. WE is HIGH for Read cycle.
15. Address valid prior to or coincident with CE transition LOW.
Document Number: 38-05589 Rev. *E
Page 7 of 15
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CY7C1021CV26
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[16, 17]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATA I/O
Write Cycle No. 2 (BLE or BHE Controlled)
t
WC
ADDRESS
t
SA
t
BW
BHE, BLE
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
SD
HD
DATA I/O
Notes
16. Data I/O is high-impedance if OE or BHE and/or BLE= V
.
IH
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document Number: 38-05589 Rev. *E
Page 8 of 15
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CY7C1021CV26
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, LOW)
OE
t
WC
ADDRESS
t
SCE
CE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
DATA I/O
t
LZWE
Truth Table
CE OE WE BLE BHE
I/O1–I/O8
High Z
I/O9–I/O16
Mode
Power
H
L
X
L
X
H
X
L
X
L
High Z
Power-down
Read – All bits
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
Data Out
Data Out
High Z
Data Out
High Z
Data Out
Data In
High Z
Data In
High Z
High Z
)
L
H
L
Read – Lower bits only
Read – Upper bits only
Write – All bits
)
H
L
)
L
X
L
L
Data In
Data In
High Z
)
L
H
L
Write – Lower bits only
Write – Upper bits only
)
H
X
H
)
L
L
H
X
H
X
X
H
High Z
Selected, Outputs Disabled
Selected, Outputs Disabled
)
High Z
)
Document Number: 38-05589 Rev. *E
Page 9 of 15
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CY7C1021CV26
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The following table contains only
the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at http://www.cypress.com
and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(ns)
Package
Name
Operating
Range
Package Type
Ordering Code
15
CY7C1021CV26-15ZSXE
CY7C1021CV26-15VXE
CY7C1021CV26-15BAE
CY7C1021CV26-15BAET
CY7C1021CV26-15VXET
51-85087 44-pin TSOP Type II (Pb-free)
Automotive
51-85082 44-pin (400-Mil) Molded SOJ (Pb-free)
51-85150 48-ball FPBGA (6 × 8 × 1 mm) (Pb-free)
51-85150 48-ball FPBGA (6 × 8 × 1 mm) (Pb-free)
51-85082 44-pin (400-Mil) Molded SOJ (Pb-free)
CY7C1021CV26-15ZSXET 51-85087 44-pin TSOP Type II (Pb-free)
Ordering Code Definitions
CY7C 1021 C V26 - 15 XXX E
X
X = T or Blank
T = Tape and Reel; Blank = Tube
Temperature Range: E = Automotive
Package Type: XXX = ZSX or VX or BA
ZSX = 44-pin TSOP Type II (Pb-free)
VX = 44-pin (400-Mil) Molded SOJ (Pb-free)
BA = 48-ball FPBGA (Pb-free)
Speed Grade (15 ns)
V26 = 2.6 V
Process Technology 0.16 µm
1021 = Part Identifier
CY7C = Cypress SRAMs
Document Number: 38-05589 Rev. *E
Page 10 of 15
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CY7C1021CV26
Package Diagrams
Figure 1. 44-pin TSOP II, 51-85087
51-85087 *C
Figure 2. 44-pin (400-Mil) Molded SOJ, 51-85082
51-85082 *C
Document Number: 38-05589 Rev. *E
Page 11 of 15
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CY7C1021CV26
Package Diagrams (continued)
Figure 3. 48-ball FBGA (6 × 8 × 1 mm), 51-85150
51-85150 *F
Document Number: 38-05589 Rev. *E
Page 12 of 15
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CY7C1021CV26
Acronyms
Document Conventions
Units of Measure
Acronym
CMOS
CE
Description
complementary metal oxide semiconductor
chip enable
Symbol
ns
Unit of Measure
nano seconds
Volts
I/O
input/output
V
OE
output enable
µA
mA
mW
MHz
pF
°C
micro Amperes
milli Amperes
milli Watts
Mega Hertz
pico Farad
degree Celcius
Watts
SOJ
small outline J-lead
SRAM
TSOP
TTL
static random access memory
thin small-outline package
transistor-transistor logic
fine-pitch ball grid array
write enable
FPBGA
WE
W
%
percent
Document Number: 38-05589 Rev. *E
Page 13 of 15
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CY7C1021CV26
Document History Page
Document Title: CY7C1021CV26 1-Mbit (64 K × 16) Static RAM
Document Number: 38-05589
Orig. of
Change
REV.
ECN NO. Issue Date
Description of Change
**
238454
335861
See ECN
See ECN
RKF
New data sheet for Automotive
Added Lead-Free Product Information
*A
SYT
Included the 44-Lead (400-Mil) Molded SOJ V34 Package
*B
493543
See ECN
NXR
Changed the description of IIX from Input Load Current to
Input Leakage Current in DC Electrical Characteristics table
Removed IOS parameter from DC Electrical Characteristics table
Updated Ordering Information Table
*C
*D
*E
2897087
03/22/10
AJU
Removed obsolete parts from ordering information table
Updated package diagrams
3057593 10/13/2010
3098812 12/01/2010
PRAS
PRAS
Updated Ordering Information and added Ordering Code Definitions.
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Minor edits and updated in new template.
Document Number: 38-05589 Rev. *E
Page 14 of 15
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CY7C1021CV26
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05589 Rev. *E
Revised December 1, 2010
Page 15 of 15
All products and company names mentioned in this document may be the trademarks of their respective holders.
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CY7C1021CV33-10BAXC
Standard SRAM, 64KX16, 10ns, CMOS, PBGA48, 7 X 7 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-48
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