CY7C1021D-10ZSXIT [CYPRESS]
Standard SRAM, 64KX16, 10ns, CMOS, PDSO44, LEAD FREE, TSOP2-44;
| 型号： | CY7C1021D-10ZSXIT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 64KX16, 10ns, CMOS, PDSO44, LEAD FREE, TSOP2-44 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总17页 (文件大小：1522K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1021D
1-Mbit (64K × 16) Static RAM
1-Mbit (64K
× 16) Static RAM
automatic power down feature that significantly reduces power
consumption when deselected. The input and output pins (I/O0
through I/O15) are placed in a high impedance state when the
device is deselected (CE HIGH), outputs are disabled (OE
HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during
a write operation (CE LOW and WE LOW).
Features
■ Temperature Ranges:
❐ Industrial: –40 °C to 85 °C
❐ Automotive-A: –40 °C to 85 °C
■ Pin and Function Compatible with CY7C1021B
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7), is written into the location
specified on the address pins (A0 through A15). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A15).
■ High Speed
❐ tAA = 10 ns
■ Low Active Power
❐ ICC = 80 mA at 10 ns
■ Low CMOS Standby Power
❐ ISB2 = 3 mA
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 10 for a
complete description of read and write modes.
■ 2.0 V Data Retention
■ Automatic Power Down when Deselected
■ CMOS for Optimum Speed and Power
■ Independent Control of Upper and Lower Bits
The CY7C1021D device is suitable for interfacing with
processors that have TTL I/P levels. It is not suitable for
processors that require CMOS I/P levels. Please see Electrical
Characteristics on page 4 for more details and suggested
alternatives.
■ Available in Pb-free 44-pin 400 Mils Wide Molded SOJ and
44-pin TSOP II Packages
Functional Description
For a complete list of related documentation, click here.
The CY7C1021D is a high performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
Logic Block Diagram
DATA IN DRIVERS
A7
A6
A5
64K x 16
A4
I/O0–I/O7
RAM Array
A3
A2
A1
A0
I/O8–I/O15
COLUMN DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document Number: 38-05462 Rev. *O
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 2, 2016
CY7C1021D
Contents
Pin Configurations ...........................................................3
Selection Guide ................................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics .......................................6
Data Retention Waveform ................................................6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Truth Table ......................................................................10
Ordering Information ......................................................11
Ordering Code Definitions .........................................11
Package Diagrams ..........................................................12
Acronyms ........................................................................14
Document Conventions .................................................14
Units of Measure .......................................................14
Document History Page .................................................15
Sales, Solutions, and Legal Information ......................17
Worldwide Sales and Design Support .......................17
Products ....................................................................17
PSoC®Solutions .......................................................17
Cypress Developer Community .................................17
Technical Support .....................................................17
Document Number: 38-05462 Rev. *O
Page 2 of 17
CY7C1021D
Pin Configurations
Figure 1. 44-pin SOJ / 44-pin TSOP II pinout (Top View) [1]
A
A
A
A
A
A
A
A
7
OE
BHE
BLE
I/O
15
I/O
I/O
13
I/O
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
4
3
2
1
0
5
6
CE
I/O
0
1
2
3
I/O
I/O
I/O
V
14
9
10
11
12
13
14
15
16
12
V
CC
SS
V
SS
V
CC
I/O
I/O
I/O
I/O
I/O
4
5
6
7
11
10
I/O
I/O
I/O
9
8
WE 17
NC
A
A
A
A
A
18
19
20
21
22
15
14
13
12
8
A
9
A
10
A
11
NC
NC
Selection Guide
-10 (Industrial /
Automotive-A)
Description
Unit
Maximum Access Time
10
80
3
ns
Maximum Operating Current
Maximum CMOS Standby Current
mA
mA
Note
1. NC pins are not connected on the die.
Document Number: 38-05462 Rev. *O
Page 3 of 17
CY7C1021D
DC Input Voltage [2] ............................ –0.5 V to VCC + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ..........................> 2001 V
Storage Temperature ............................... –65 C to +150 C
Latch Up Current ...................................................> 200 mA
Ambient Temperature
with Power Applied .................................. –55 C to +125 C
Operating Range
Supply Voltage
Ambient
Temperature
on VCC to Relative GND[2] ...........................–0.5 V to +6.0 V
Range
VCC
Speed
DC Voltage Applied to Outputs
Industrial
–40 C to +85 C
5 V 10%
10 ns
in High Z State [2] ................................–0.5 V to VCC + 0.5 V
Automotive-A
Electrical Characteristics
Over the Operating Range
-10 (Industrial /
Automotive-A)
Parameter
Description
Test Conditions
Unit
Min
2.4
–
Max
VOH
Output HIGH Voltage
IOH = –4.0 mA
IOH = –0.1 mA
IOL = 8.0 mA
–
V
3.4 [3]
0.4
VOL
VIH
VIL
IIX
Output LOW Voltage
–
V
Input HIGH Voltage
2.2
0.5
1
1
–
VCC + 0.5 V
V
Input LOW Voltage [2]
Input Leakage Current
Output Leakage Current
VCC Operating Supply Current
0.8
+1
+1
80
72
58
37
10
V
GND < VI < VCC
A
A
mA
mA
mA
mA
mA
IOZ
ICC
GND < VI < VCC, Output Disabled
VCC = Max, IOUT = 0 mA,
f = fmax = 1/tRC
100 MHz
83 MHz
66 MHz
40 MHz
–
–
–
ISB1
ISB2
Automatic CE Power Down
Current –TTL Inputs
Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fmax
–
Automatic CE Power Down
Current – CMOS Inputs
Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or
–
3
mA
VIN < 0.3 V, f = 0
Note
2.
V (min) = –2.0 V and V (max) = V + 1 V for pulse durations of less than 5 ns.
IL IH CC
3. Please note that the maximum V limit does not exceed minimum CMOS V of 3.5 V. If you are interfacing this SRAM with 5 V legacy processors that require a
OH
IH
minimum V of 3.5 V, please refer to Application Note AN6081 for technical details and options you may consider.
IH
Document Number: 38-05462 Rev. *O
Page 4 of 17
CY7C1021D
Capacitance
Parameter [4]
Description
Input capacitance
Output capacitance
Test Conditions
TA = 25C, f = 1 MHz, VCC = 5.0 V
Max
8
Unit
pF
CIN
COUT
8
pF
Thermal Resistance
Parameter [4]
Description
Test Conditions
44-pin SOJ 44-pin TSOP II Unit
JA
Thermal resistance
(junction to ambient)
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
59.52
53.91
C/W
JC
Thermal resistance
(junction to case)
36.75
21.24
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [5]
ALL INPUT PULSES
3.0 V
Z = 50
90%
10%
90%
10%
OUTPUT
50
GND
30 pF*
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5 V
Fall Time: 3 ns
Rise Time: 3 ns
(b)
(a)
High-Z characteristics:
R1 480
5 V
OUTPUT
R2
255
5 pF
INCLUDING
JIG AND
SCOPE
(c)
Notes
4. Tested initially and after any design or process changes that may affect these parameters.
5. AC characteristics (except High Z) are tested using the load conditions shown in Figure 2 (a). High Z characteristics are tested for all speeds using the test load
shown in Figure 2 (c).
Document Number: 38-05462 Rev. *O
Page 5 of 17
CY7C1021D
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
ICCDR
Description
VCC for Data Retention
Data Retention Current
Conditions
Min
2.0
–
Max
–
Unit
V
VCC = VDR = 2.0 V, CE > VCC – 0.3 V,
IN > VCC – 0.3 V or VIN < 0.3 V
3
mA
V
[6]
tCDR
Chip Deselect to Data Retention
Time
0
–
–
ns
ns
[7]
tR
Operation Recovery Time
tRC
Data Retention Waveform
Figure 3. Data Retention Waveform
DATA RETENTION MODE
4.5 V
4.5 V
VDR > 2 V
V
CC
t
t
R
CDR
CE
Notes
6.
V
(min) = –2.0 V and V (max) = V + 1 V for pulse durations of less than 5 ns.
IH CC
IL
7. Full device operation requires linear V ramp from V to V
> 50 s or stable at V
> 50 s.
CC
DR
CC(min)
CC(min)
Document Number: 38-05462 Rev. *O
Page 6 of 17
CY7C1021D
Switching Characteristics
Over the Operating Range
-10 (Industrial /
Automotive-A)
Parameter [8]
Description
Unit
Min
Max
Read Cycle
[9]
tpower
tRC
VCC(typical) to the first access
100
10
–
–
–
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z [10]
OE HIGH to High Z [10, 11]
CE LOW to Low Z [10]
CE HIGH to High Z [10, 11]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
10
–
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
3
–
10
5
–
0
–
–
5
3
–
–
5
0
–
tPD
–
10
5
tDBE
tLZBE
tHZBE
–
0
–
–
5
Write Cycle [12, 13]
tWC
tSCE
tAW
Write Cycle Time
10
7
7
0
0
7
6
0
3
–
7
–
–
–
–
–
–
–
–
–
5
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
tHA
tSA
tPWE
tSD
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low Z [10]
WE LOW to High Z [10, 11]
Byte Enable to End of Write
tHD
tLZWE
tHZWE
tBW
Notes
8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified I /I
OL OH
and 30-pF load capacitance.
t gives the minimum amount of time that the power supply should be at typical V values until the first memory access can be performed.
POWER
9.
10. At any given temperature and voltage condition, t
CC
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
11. t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in (c) of Figure 2 on page 5. Transition is measured when the outputs enter a high impedance
HZOE HZBE HZCE
HZWE
state.
12. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a write, and
a LOW to HIGH transition on any of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal
that terminates the write.
13. The minimum write cycle pulse width for the Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to the sum of t and t
.
SD
HZWE
Document Number: 38-05462 Rev. *O
Page 7 of 17
CY7C1021D
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [14, 15]
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [15, 16]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
LZOE
BHE, BLE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
t
PU
VCC
SUPPLY
CURRENT
50%
50%
ISB
Notes
14. Device is continuously selected. OE, CE, BHE and/or BLE = V .
IL
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE transition LOW.
Document Number: 38-05462 Rev. *O
Page 8 of 17
CY7C1021D
Switching Waveforms (continued)
Figure 6. Write Cycle No. 1 (CE Controlled) [17, 18]
t
WC
ADDRESS
CE
t
SA
t
SCE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
Data Valid
DATA I/O
Figure 7. Write Cycle No. 2 (BLE or BHE Controlled)
t
WC
ADDRESS
BHE, BLE
t
SA
t
BW
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
SD
HD
Data Valid
DATA I/O
Notes
17. Data I/O is high impedance if OE or BHE and/or BLE = V
.
IH
18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 38-05462 Rev. *O
Page 9 of 17
CY7C1021D
Switching Waveforms (continued)
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
Data Valid
DATA I/O
t
LZWE
Truth Table
CE
H
OE
X
WE
X
BLE BHE
I/O0–I/O7
High Z
I/O8–I/O15
High Z
Mode
Power
X
L
X
L
Power Down
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
L
L
H
Data Out
Data Out
High Z
Data Out
High Z
Read – All bits
)
L
H
L
Read – Lower bits only
Read – Upper bits only
Write – All bits
)
H
L
Data Out
Data In
High Z
)
L
X
L
L
Data In
Data In
High Z
)
L
H
L
Write – Lower bits only
Write – Upper bits only
)
H
X
H
Data In
High Z
)
L
L
H
X
H
X
X
H
High Z
Selected, Outputs Disabled Active (ICC
)
High Z
High Z
Selected, Outputs Disabled Active (ICC)
Document Number: 38-05462 Rev. *O
Page 10 of 17
CY7C1021D
Ordering Information
Speed
Package
Diagram
Operating
Range
Ordering Code
(ns)
Package Type
10
CY7C1021D-10VXI
CY7C1021D-10ZSXI
CY7C1021D-10ZSXA
51-85082 44-pin (400-Mil) Molded SOJ (Pb-free)
51-85087 44-pin TSOP Type II (Pb-free)
Industrial
Automotive-A
Shaded areas contain advance information. Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 7
C
1 02
1
D - 10 XX
X
X
Temperature Range: X = I or A
I = Industrial; A = Automotive-A
Pb-free
Package Type: XX = V or ZS
V = 44-pin Molded SOJ
ZS = 44-pin TSOP Type II
Speed: 10 ns
D = C9, 90 nm Technology
Data Width: 1 = × 16-bits
Density: 02 = 1-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05462 Rev. *O
Page 11 of 17
CY7C1021D
Package Diagrams
Figure 9. 44-pin SOJ (400 Mils) V44.4 Package Outline, 51-85082
51-85082 *E
Document Number: 38-05462 Rev. *O
Page 12 of 17
CY7C1021D
Package Diagrams (continued)
Figure 10. 44-pin TSOP Z44-II Package Outline, 51-85087
51-85087 *E
Document Number: 38-05462 Rev. *O
Page 13 of 17
CY7C1021D
Acronyms
Document Conventions
Units of Measure
Acronym
Description
CE
Chip Enable
Symbol
°C
Unit of Measure
CMOS
I/O
Complementary Metal Oxide Semiconductor
Input/Output
degree Celsius
megahertz
microampere
microsecond
milliampere
millimeter
millisecond
nanosecond
ohm
MHz
µA
µs
OE
Output Enable
SOJ
SRAM
TSOP
TTL
Small Outline J-lead
Static Random Access Memory
Thin Small Outline Package
Transistor-Transistor Logic
Write Enable
mA
mm
ms
ns
WE
%
percent
pF
V
picofarad
volt
W
watt
Document Number: 38-05462 Rev. *O
Page 14 of 17
CY7C1021D
Document History Page
Document Title: CY7C1021D, 1-Mbit (64K × 16) Static RAM
Document Number: 38-05462
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
201560
233695
SWI
RKF
See ECN Advance Information data sheet for C9 IPP
*A
See ECN DC parameters modified as per EROS (Spec # 01-02165)
Pb-free Offering in the Ordering Information
*B
263769
RKF
See ECN Added Data Retention Characteristics Table
Added Tpower Spec in Switching Characteristics Table
Shaded Ordering Information
*C
*D
307601
520647
RKF
VKN
See ECN Reduced Speed bins to –10 and –12 ns
See ECN Changed status from Preliminary to Final.
Removed Commercial Operating range
Added ICC values for the frequencies 83MHz, 66MHz and 40MHz
Updated Thermal Resistance table
Added Automotive Product Information
Updated Ordering Information Table
Changed Overshoot spec from VCC+2V to VCC+1V in footnote #4
*E
*F
802877
VKN
See ECN Changed Commercial operating range ICC spec from 60 mA to 80 mA for
100MHz, 55 mA to 72 mA for 83MHz, 45 mA to 58 mA for 66MHz, 30 mA to
37 mA for 40MHz
Changed Automotive operating range ICC spec from 100 mA to 120 mA for
83MHz, 90 mA to 100 mA for 66MHz, 60 mA to 63 mA for 40MHz
2751755
VKN /
PYRS
08/14/09
For 12 ns speed, changed ICC spec from 120 mA to 90 mA
For 12 ns speed, changed ISB1 spec from 50 mA to 10 mA and ISB2 spec from
15 mA to 10 mA
*G
*H
*I
2898399
3109897
3245199
AJU
AJU
03/24/2010 Updated Package Diagrams.
12/14/2010 Added Ordering Code Definitions.
PRAS
04/30/2011 Dislodged Automotive information to new datasheet (001-68372).
Removed the Note “Automotive Product Information is Preliminary.” in page 3.
Added Acronyms and Units of Measure.
Updated to new template.
*J
3086499
AJU
06/07/2011 Updated Functional Description (Removed “For best practice
recommendations, refer to the Cypress application note AN1064, SRAM
System Guidelines.”).
*K
3540685 TAVA / AJU 03/06/2012 Updated Features (Included Automotive-A Range information).
Updated Selection Guide (Included Automotive-A Range information).
Updated Operating Range (Included Automotive-A Range information).
Updated Electrical Characteristics (Included Automotive-A Range
information).
Updated Switching Characteristics (Included Automotive-A Range
information).
Updated Ordering Information (included the part number
CY7C1021D-10ZSXA).
Updated Package Diagrams.
*L
3998493
MEMJ
05/13/2013 Replaced all instances of IO with I/O across the document.
Updated Switching Characteristics:
Updated Note 12.
Updated Switching Waveforms:
Updated Figure 6, Figure 7, Figure 8.
Updated Package Diagrams:
spec 51-85082 – Changed revision from *D to *E.
spec 51-85087 – Changed revision from *D to *E.
Completing Sunset Review.
Document Number: 38-05462 Rev. *O
Page 15 of 17
CY7C1021D
Document History Page (continued)
Document Title: CY7C1021D, 1-Mbit (64K × 16) Static RAM
Document Number: 38-05462
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
*M
4033925
MEMJ
06/19/2013 Updated Functional Description.
Updated Electrical Characteristics:
Added one more Test Condition “IOH = –0.1mA” for VOH parameter and added
maximum value corresponding to that Test Condition.
Added Note 3 and referred the same note in maximum value for VOH parameter
corresponding to Test Condition “IOH = –0.1mA”.
*N
*O
4573121
5293980
MEMJ
VINI
11/18/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
06/02/2016 Updated Switching Characteristics:
Added Note 13 and referred the same note in “Write Cycle”.
Updated to new template.
Completing Sunset Review.
Document Number: 38-05462 Rev. *O
Page 16 of 17
CY7C1021D
Sales, Solutions, and Legal Information
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closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2004-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-05462 Rev. *O
Revised June 2, 2016
Page 17 of 17
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CY7C1021DV33-10BAXI
Standard SRAM, 64KX16, 10ns, CMOS, PBGA48, 7 X 7 MM, 1.20 MM, LEAD FREE, FBGA-48
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CY7C1021DV33-10BVXIT
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CY7C1021DV33-10VXIT
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