CY7C1041CV33-8ZSXC [CYPRESS]
4-Mbit (256 K × 16) Static RAM; 4兆位（ 256千× 16 ）静态RAM
| 型号： | CY7C1041CV33-8ZSXC |
| 厂家： | 
CYPRESS |
| 描述： | 4-Mbit (256 K × 16) Static RAM |
| 文件： | 总15页 (文件大小：449K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1041CV33
4-Mbit (256 K × 16) Static RAM
4-Mbit (256
K × 16) Static RAM
Features
Functional Description
■ Temperature ranges
❐ Commercial: 0 °C to 70°C
The CY7C1041CV33 is a high performance CMOS static RAM
organized as 262,144 words by 16 bits.
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (/IO0 through I/O7), is written into the location
specified on the address pins (A0 through A17). If Byte High
■ Pin and function compatible with CY7C1041BV33
■ High speed
❐ tAA = 8 ns
Enable (BHE) is LOW, then data from IO pins (I/O8 through I/O15
)
■ Low active power
❐ 360 mW (max)
is written into the location specified on the address pins (A0
through A17).
■ 2.0 V data retention
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. For more information, see the Truth
Table on page 10 for a complete description of Read and Write
modes.
■ Automatic power down when deselected
■ TTL-compatible inputs and outputs
■ Easy memory expansion with CE and OE features
■ Available in Pb-free 44-pin TSOP II package
The input and output pins (I/O0 through I/O15) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE LOW
and WE LOW).
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
INPUT BUFFER
A
A
0
1
A
A
A
A
2
3
4
5
256K x 16
RAM Array
I/O –I/O
0
7
A
A
A
6
7
8
I/O –I/O
8
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document Number: 38-05134 Rev. *L
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 4, 2011
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CY7C1041CV33
Contents
Selection Guide ................................................................3
Pin Configuration .............................................................3
Pin Definitions ..................................................................4
Maximum Ratings .............................................................5
Operating Range ...............................................................5
Electrical Characteristics .................................................5
Capacitance ......................................................................6
Thermal Resistance ..........................................................6
AC Test Loads and Waveforms .......................................6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Truth Table ......................................................................10
Ordering Information ......................................................11
Ordering Code Definitions .........................................11
Package Diagram ............................................................12
Acronyms .......................................................................13
Document Conventions .................................................13
Units of Measure .......................................................13
Document History Page .................................................14
Sales, Solutions, and Legal Information ......................15
Worldwide Sales and Design Support .......................15
Products ....................................................................15
PSoC Solutions .........................................................15
Document Number: 38-05134 Rev. *L
Page 2 of 15
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CY7C1041CV33
Selection Guide
Description
-8
8
Unit
ns
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
100
10
mA
mA
Pin Configuration
Figure 1. 44-pin TSOP II (Top View) [1]
A
A
A
A
A
A
A
A
OE
BHE
BLE
I/O
15
I/O
I/O
13
I/O
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
0
1
2
3
4
17
16
15
CE
I/O
0
1
2
3
I/O
I/O
I/O
V
14
9
10
11
12
13
14
15
16
12
V
CC
SS
V
V
CC
I/O
IO
SS
I/O
4
5
6
7
11
10
IO
IO
IO
IO
IO
9
8
NC
WE 17
A
5
A
6
A
7
A
8
18
19
20
21
22
A
14
A
13
A
12
A
11
A
10
A
9
Note
1. NC pins are not connected on the die.
Document Number: 38-05134 Rev. *L
Page 3 of 15
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CY7C1041CV33
Pin Definitions
TSOP Pin
Number
Pin Name
I/O Type
Description
A0–A17
1–5, 18–27,
42–44
Input
Address Inputs. Used to select one of the address locations.
I/O0–I/O15 7–10,13–16, Input or Output Bidirectional Data IO lines. Used as input or output lines depending on operation.
29–32, 35–38
NC
28
17
No Connect No Connects. Not connected to the die.
WE
Input or
Control
Write Enable Input, Active LOW. When selected LOW, a write is conducted.
When deselected HIGH, a read is conducted.
CE
BHE, BLE
OE
6
Input or
Control
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH,
deselects the chip.
40, 39
41
Input or
Control
Byte Write Select Inputs, Active LOW. BHE controls I/O15 – I/O8, BLE controls
I/O7 – I/O0.
Input or
Control
Output Enable, Active LOW. Controls the direction of the I/O pins. When LOW,
the IO pins are allowed to behave as outputs. When deasserted HIGH, the I/O pins
are tri-stated and act as input data pins.
VSS
VCC
12, 34
11, 33
Ground
Ground for the Device. Connected to ground of the system.
Power Supply Power Supply Inputs to the Device.
Document Number: 38-05134 Rev. *L
Page 4 of 15
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CY7C1041CV33
DC Input Voltage[2] ............................... –0.5 V to VCC + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage..........................................> 2001 V
(MIL-STD-883, Method 3015)
Storage Temperature ............................... –65 C to +150 C
Latch Up Current ....................................................> 200 mA
Ambient Temperature with
Power Applied .......................................... –55 C to +125 C
Supply Voltage on VCC Relative to GND[2]...–0.5 V to +4.6 V
Operating Range
Ambient
Temperature (TA)
Range
Commercial
VCC
DC Voltage Applied to Outputs
in High Z State[2]..................................–0.5 V to VCC + 0.5 V
0 C to +70 C
3.3 V 10%
Electrical Characteristics
Over the Operating Range
-8
Parameter
Description
Test Conditions
Unit
Min
2.4
–
Max
–
VOH
VOL
VIH
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
VCC = Min, IOH = –4.0 mA
VCC = Min, IOL = 8.0 mA
V
V
0.4
2.0
–0.3
–1
–1
–
VCC + 0.3
0.8
V
[2]
VIL
Input LOW Voltage
V
IIX
Input Leakage Current
Output Leakage Current
VCC Operating Supply Current
GND < VI < VCC
+1
A
A
mA
mA
IOZ
ICC
ISB1
GND < VOUT < VCC, Output disabled
VCC = Max, f = fMAX = 1/tRC
+1
100
40
Automatic CE Power Down
Current —TTL Inputs
Max VCC, CE > VIH,
VIN > VIH or VIN < VIL, f = fMAX
–
ISB2
Automatic CE Power Down
Current — CMOS Inputs
Max VCC, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0
–
10
mA
Note
2.
V (min) = –2.0 V and V (max) = V + 0.5 V for pulse durations of less than 20 ns.
IL IH CC
Document Number: 38-05134 Rev. *L
Page 5 of 15
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CY7C1041CV33
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
CIN
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 3.3 V
Max
8
Unit
pF
COUT
8
pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Test Conditions
TSOP II
Unit
JA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and procedures
for measuring thermal impedance, per EIA/JESD51
42.96
C/W
JC
Thermal Resistance
(Junction to Case)
10.75
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [3]
12-, 15-, 20-ns devices:
10-ns devices:
R 317
Z = 50
3.3V
OUTPUT
OUTPUT
50
30 pF*
R2
351
30 pF*
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5 V
(b)
(a)
High Z characteristics:
R 317
ALL INPUT PULSES
90%
3.3 V
OUTPUT
5 pF
3.0 V
90%
10%
10%
R2
351
GND
(c)
Fall Time: 1 V/ns
Rise Time: 1 V/ns
(d)
Note
3. AC characteristics (except High Z) for 10-ns parts are tested using the load conditions shown in Figure 2 (a). All other speeds are tested using the Thevenin load shown
in Figure 2 (b). High Z characteristics are tested for all speeds using the test load shown in Figure 2 (d).
Document Number: 38-05134 Rev. *L
Page 6 of 15
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CY7C1041CV33
Switching Characteristics
Over the Operating Range [4]
-8
Parameter
Description
Unit
Min Max
Read Cycle
[5]
tpower
tRC
VCC(Typical) to the First Access
100
8
–
–
8
–
8
5
–
4
–
4
–
8
5
–
5
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[6]
OE HIGH to High Z[6, 7]
CE LOW to Low Z[6]
CE HIGH to High Z[6, 7]
CE LOW to Power Up
CE HIGH to Power Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
–
tOHA
tACE
3
–
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
–
0
–
3
–
0
tPD
–
tDBE
–
tLZBE
tHZBE
Write Cycle[8, 9]
tWC
0
–
Write Cycle Time
8
6
6
0
0
6
4
0
3
–
6
–
–
–
–
–
–
–
–
–
4
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
tAW
tHA
tSA
tPWE
tSD
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low Z[6]
tHD
tLZWE
tHZWE
tBW
WE LOW to High Z[6, 7]
Byte Enable to End of Write
Notes
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V.
5. gives the minimum amount of time that the power supply is at typical V values until the first memory access is performed.
6. At any temperature and voltage condition, t
t
POWER
CC
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any device.
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
7.
t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in part (d) of Figure 2 on page 6. Transition is measured 500 mV from steady state
HZOE HZCE HZBE
HZWE
voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE must be LOW to initiate a write.
The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write.
9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
Document Number: 38-05134 Rev. *L
Page 7 of 15
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CY7C1041CV33
Switching Waveforms
Figure 3. Read Cycle No. 1 (Address Transition Controlled)[10, 11]
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 4. Read Cycle No. 2 (OE Controlled)[11, 12]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
LZOE
BHE, BLE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
ICC
ISB
PU
VCC
SUPPLY
CURRENT
50%
50%
Notes
10. Device is continuously selected. OE, CE, BHE, and/or BLE = V
11. WE is HIGH for read cycle.
.
IL
12. Address valid prior to or coincident with CE transition LOW.
Document Number: 38-05134 Rev. *L
Page 8 of 15
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CY7C1041CV33
Switching Waveforms (continued)
Figure 5. Write Cycle No. 1 (CE Controlled)[13, 14]
t
WC
ADDRESS
CE
t
SA
t
SCE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATA IO
Figure 6. Write Cycle No. 2 (BLE or BHE Controlled)
t
WC
ADDRESS
BHE, BLE
t
t
BW
SA
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
SD
HD
DATA IO
Notes
13. Data IO is high impedance if OE, BHE, and/or BLE = V
.
IH
14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 38-05134 Rev. *L
Page 9 of 15
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CY7C1041CV33
Switching Waveforms (continued)
Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
DATA IO
t
LZWE
Truth Table
CE
H
OE
X
WE
X
BLE
X
BHE I/O0 – I/O7 I/O8 – I/O15
Mode
Power
X
L
High Z
High Z
Power Down
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
L
L
H
L
Data Out Data Out
Data Out High Z
Read – All Bits
)
L
H
L
Read – Lower Bits Only
Read – Upper Bits Only
Write – All Bits
)
H
L
High Z
Data In
Data In
High Z
High Z
High Z
Data Out
Data In
High Z
Data In
High Z
High Z
)
L
X
L
L
)
L
H
L
Write – Lower Bits Only
Write – Upper Bits Only
)
H
X
)
L
L
H
X
H
X
X
H
Selected, Outputs Disabled
Selected, Outputs Disabled
)
H
)
Document Number: 38-05134 Rev. *L
Page 10 of 15
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CY7C1041CV33
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the
list of parts that are currently available.For a complete listing of all options, visit the Cypress website at www.cypress.com and refer
to the product summary page at http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
8
CY7C1041CV33-8ZSXC
51-85087 44-pin Thin Small Outline Package Type II (Pb-free)
Commercial
Please contact your local Cypress sales representative for availability of these parts
Ordering Code Definitions
CY 7C
1
04
1
C V33 - 8 ZS
X
C
Temperature Range:
C= Commercial
X = Pb-free; X Absent = Leaded
Package Type:
ZS = 44-pin TSOP II
Speed Grade: 8 ns
V33 = 3.0 V to 3.6 V
Process Technology:C 150 nm
Data width: × 16-bits
4-Mbit density
Fast Asynchronous SRAM
Marketing Code: 7C = SRAMs
Company ID: CY = Cypress
Document Number: 38-05134 Rev. *L
Page 11 of 15
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CY7C1041CV33
Package Diagram
Figure 8. 44-pin Thin Small Outline Package Type II, 51-85087
51-85087 *C
Document Number: 38-05134 Rev. *L
Page 12 of 15
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CY7C1041CV33
Acronyms
Document Conventions
Units of Measure
Acronym
CE
Description
Chip Enable
Symbol
Unit of Measure
CMOS
FBGA
I/O
complementary metal oxide semiconductor
fine-pitch ball grid array
input/output
ohms
ns
nano seconds
Volts
V
OE
Output Enable
µs
micro seconds
micro Amperes
milli Amperes
milli meter
milli seconds
Mega Hertz
pico Farad
percent
SOJ
Small Outline J-lead
µA
mA
mm
ms
MHz
pF
%
SRAM
TSOP
TTL
static random access memory
thin small outline package
transistor-transistor logic
Write Enable
WE
mW
W
milli Watts
Watts
°C
degree Celcius
Document Number: 38-05134 Rev. *L
Page 13 of 15
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CY7C1041CV33
Document History Page
Document Title: CY7C1041CV33, 4-Mbit (256 K × 16) Static RAM
Document Number: 38-05134
Orig. of
REV. ECN NO. Issue Date
Change
Description of Change
**
109513
112440
112859
12/13/01
12/20/01
03/25/02
HGK
BSS
DFP
New Data Sheet
*A
*B
Updated 51-85106 from revision *A to *C
Added CY7C1042CV33 in BGA package
Removed 1042 BGA option pin ACC Final Data Sheet
*C
*D
*E
116477
119797
262949
09/16/02
10/21/02
See ECN
CEA
DFP
RKF
Add applications foot note to data sheet
Added 20-ns speed bin
1) Added Lead (Pb)-Free parts in the Ordering info (Page #9)
2) Added Automotive Specs to Datasheet
*F
361795
435387
See ECN
See ECN
SYT
NXR
Added Pb-Free offerings in the Ordering Information
*G
Removed -8 Speed bin from Product offering.
Corrected typo in description for BHE/BLE in pin definitions table on Page# 3
corrected their Pin name from OE2 to OE.
Included the Maximum Ratings for Static Discharge Voltage and Latch up Current.
Changed the description of IIX current from Input Load Current to
Input Leakage Current
Added note# 4 on page# 4
Updated the Ordering Information table
*H
*I
499153
See ECN
NXR
Added Automotive-A Operating Range
Changed tpower value from 1 s to 100 s
Updated Ordering Information table
2104110
2897141
See ECN VKN/AESA Added Automotive-E specs for 12 ns speed
Updated Ordering Information table
*J
*K
*L
03/22/10
AJU/VIVG Removed inactive parts. Updated package diagrams.
3072834 11/12/2010
3186840 03/03/2011
PRAS
PRAS
Removed inactive parts. Added Ordering Code Definitions on page 11.
Updated Features.
Updated Selection Guide (Added -8 ns speed grade devices and removed -10 ns,
-12 ns, -15 ns and -20 ns speed grade devices).
Removed Figure “48-Ball FBGA Pinout (Top View)” and renamed Figure “44-Pin
SOJ/TSOP II (Top View)” as “44-pin TSOP II (Top View)” in Pin Configuration.
Updated Pin Definitions (Deleted the column “BGA Pin Number” and renamed the
column “SOJ, TSOP Pin Number” as “TSOP Pin Number”.
Updated Operating Range
Updated Electrical Characteristics (Added -8 ns speed grade devices and removed
-10 ns, -12 ns, -15 ns and -20 ns speed grade devices).
Updated Thermal Resistance (Deleted the columns SOJ and FBGA).
Updated Switching Characteristics (Added -8 ns speed grade devices and removed
-10 ns, -12 ns, -15 ns and -20 ns speed grade devices).
Updated Ordering Information (Added new speed bin (-8 ns speed grade devices)
and removed -10 ns, -12 ns, -15 ns and -20 ns speed grade devices).
Added Acronyms and Units of Measure.
Dislodged Automotive information to new datasheet (001-67307)
Removed SOJ and FBGA package related information in all instances in the
document.
Updated in new template.
Document Number: 38-05134 Rev. *L
Page 14 of 15
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CY7C1041CV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
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psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
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© Cypress Semiconductor Corporation, 2001-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05134 Rev. *L
Revised March 4, 2011
Page 15 of 15
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