CY7C1041GN-10ZSXI [CYPRESS]
Standard SRAM, 256KX16, 10ns, CMOS, PDSO44, LEAD FREE, TSOP2-44;
| 型号： | CY7C1041GN-10ZSXI |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 256KX16, 10ns, CMOS, PDSO44, LEAD FREE, TSOP2-44 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总18页 (文件大小：1675K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1041GN
4-Mbit (256K words × 16 bit) Static RAM
4-Mbit (256K words
× 16 bit) Static RAM
Data writes are performed by asserting the Chip Enable (CE) and
Write Enable (WE) inputs LOW, while providing the data on I/O0
through I/O15 and address on A0 through A17 pins. The Byte High
Enable (BHE) and Byte Low Enable (BLE) inputs control write
operations to the upper and lower bytes of the specified memory
location. BHE controls I/O8 through I/O15 and BLE controls I/O0
through I/O7.
Features
■ High speed
❐ tAA = 10 ns / 15 ns
■ Low active and standby currents
❐ Active current: ICC = 38-mA typical
❐ Standby current: ISB2 = 6-mA typical
Data reads are performed by asserting the Chip Enable (CE) and
■ Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and
4.5 V to 5.5 V
Output Enable (OE) inputs LOW and providing the required
address on the address lines. Read data is accessible on the I/O
lines (I/O0 through I/O15). Byte accesses can be performed by
asserting the required byte enable signal (BHE or BLE) to read
either the upper byte or the lower byte of data from the specified
address location.
■ 1.0-V data retention
■ TTL-compatible inputs and outputs
■ Pb-free 44-pin SOJ, 44-pin TSOP II, and 48-ball VFBGA
packages
All I/Os (I/O0 through I/O15) are placed in a high-impedance state
during the following events:
Functional Description
■ The device is deselected (CE HIGH)
CY7C1041GN is high-performance CMOS fast static RAM
Organized as 256K words by 16-bits.
■ The control signals (OE, BLE, BHE) are de-asserted
The logic block diagram is on page 2.
Product Portfolio
Power Dissipation
Speed
Operating ICC, (mA)
(ns)
Product
Range
VCC Range (V)
Standby, ISB2 (mA)
f = fmax
10/15
Typ[1]
–
Max
40
Typ[1]
Max
CY7C1041GN18
1.65 V–2.2 V
2.2 V–3.6 V
4.5 V–5.5 V
15
10
10
CY7C1041GN30
CY7C1041GN
Industrial
38
45
6
8
38
45
Notes
1. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for a V range of 1.65 V–2.2 V),
CC
CC
V
= 3 V (for a V range of 2.2 V–3.6 V), and V = 5 V (for a V range of 4.5 V–5.5 V), T = 25 °C.
CC
CC CC CC A
Cypress Semiconductor Corporation
Document Number: 001-95413 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 9, 2016
CY7C1041GN
Logic Block Diagram – CY7C1041GN
INPUT BUFFER
A0
A1
A2
A3
A4
A5
I/O0‐I/O7
I/O8‐I/O15
MEMORY
ARRAY
A6
A7
A8
A9
COLUMN DECODER
BHE
WE
CE1
OE
BLE
Document Number: 001-95413 Rev. *D
Page 2 of 18
CY7C1041GN
Contents
Pin Configurations ...........................................................4
Maximum Ratings .............................................................5
Operating Range ...............................................................5
DC Electrical Characteristics ..........................................5
Capacitance ......................................................................6
Thermal Resistance ..........................................................6
AC Test Loads and Waveforms .......................................6
Data Retention Characteristics .......................................7
Data Retention Waveform ................................................7
AC Switching Characteristics .........................................8
Switching Waveforms ......................................................9
Truth Table ......................................................................12
Ordering Information ......................................................13
Ordering Code Definitions .........................................13
Package Diagrams ..........................................................14
Acronyms ........................................................................16
Document Conventions .................................................16
Units of Measure .......................................................16
Document History Page .................................................17
Sales, Solutions, and Legal Information ......................18
Worldwide Sales and Design Support .......................18
Products ....................................................................18
PSoC® Solutions ......................................................18
Cypress Developer Community .................................18
Technical Support .....................................................18
Document Number: 001-95413 Rev. *D
Page 3 of 18
CY7C1041GN
Pin Configurations
Figure 1. 48-ball VFBGA (6 × 8 × 1.0 mm) pinout,
Package/Grade ID: BVXI[2, 3]
Figure 2. 48-ball VFBGA (6 × 8 × 1.0 mm) pinout,
Package/Grade ID: BVJXI[2]
1
BLE
I/O0
I/O1
VSS
VCC
I/O6
I/O7
NC
2
OE
3
4
A1
5
A2
6
NC
1
BLE
I/O8
I/O9
2
OE
3
4
A1
5
A2
6
NC
A0
A
B
C
D
A0
A
B
C
D
BHE
I/O2
I/O3
I/O4
I/O5
NC
A3
A5
A4
CE
I/O8
I/O9
BHE
I/O10
A3
A5
A4
CE
I/O0
I/O2
VCC
VSS
I/O6
I/O7
NC
A6
I/O1
I/O3
I/O4
I/O5
WE
A11
A6
I/O10
VSS I/O11
VCC I/O12
I/O14 I/O13
A17
NC
A14
A12
A9
A7
A17
NC
A14
A12
A9
A7
I/O11 VCC
I/O12 VSS
I/O13 I/O14
A16
A15
A13
A10
E
F
A16
A15
A13
A10
E
F
I/O15
NC
NC
A8
G
H
WE
A11
I/O15
NC
G
H
A8
Figure 3. 44-pin TSOP II / 44-pin SOJ pinout[2]
A17
A16
A15
A0
A1
A2
1
2
44
43
42
3
A3
4
41 /OE
A4
5
40 /BHE
/BLE
39
/CE
I/O0
I/O1
I/O2
6
7
38 I/O15
8
37
I/O14
9
36 I/O13
44- pin TSOP II
10
11
35
I/O12
VSS
I/O3
VCC
34
33
32
31
VCC
VSS 12
13
14
I/O4
I/O5
I/O11
I/O10
I/O6 15
30 I/O9
16
17
18
19
20
21
22
29
28
27
26
25
24
23
I/O7
I/O8
NC
/WE
A5
A14
A13
A12
A11
A6
A7
A8
A9
A10
Notes
2. NC pins are not connected internally to the die.
3. Package type BVJXI is JEDEC compliant compared to package type BVXI. The difference between the two is that the higher and lower byte I/Os (I/O[7:0] and I/O[15:8]
balls are swapped.
Document Number: 001-95413 Rev. *D
Page 4 of 18
CY7C1041GN
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Current into outputs (in LOW state) ............................ 20 mA
Static discharge voltage
Storage temperature ................................ –65 C to +150 C
(MIL-STD-883, Method 3015) .................................> 2001 V
Ambient temperature
Latch-up current ....................................................> 140 mA
with power applied ................................... –55 C to +125 C
Operating Range
Supply voltage
on VCC relative to GND[4] ................... –0.5 V to VCC + 0.5 V
Grade
Ambient Temperature
VCC
1.65 V to 2.2 V,
2.2 V to 3.6 V,
4.5 V to 5.5 V
DC voltage applied to outputs
in HI-Z State[4] ....................................–0.5 V to VCC + 0.5 V
Industrial
–40 C to +85 C
DC input voltage[4] ..............................–0.5 V to VCC + 0.5 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
10 ns / 15 ns
Parameter
Description
1.65 V to 2.2 V
Test Conditions
Unit
Max
Min
Typ[5]
VCC = Min, IOH = –0.1 mA
1.4
–
–
–
2.2 V to 2.7 V
2.7 V to 3.0 V
3.0 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
1.65 V to 2.2 V
2.2 V to 2.7 V
2.7 V to 3.6 V
4.5 V to 5.5 V
1.65 V to 2.2 V
2.2 V to 2.7 V
2.7 V to 3.6 V
4.5 V to 5.5 V
1.65 V to 2.2 V
2.2 V to 2.7 V
2.7 V to 3.6 V
4.5 V to 5.5 V
VCC = Min, IOH = –1.0 mA
2
–
VCC = Min, IOH = –4.0 mA
2.2
–
–
V
–
Output HIGH
voltage
VOH
VCC = Min, IOH = –4.0 mA
2.4
–
VCC = Min, IOH = –4.0 mA
2.4
VCC – 0.5[6]
–
–
–
VCC = Min, IOH = –0.1 mA
–
VCC = Min, IOL = 0.1 mA
–
–
0.2
VCC = Min, IOL = 2 mA
–
–
0.4
Output LOW
voltage
VOL
VIH
VIL
V
VCC = Min, IOL = 8 mA
–
–
0.4
VCC = Min, IOL = 8 mA
–
1.4
2
–
0.4
VCC + 0.2[4]
–
–
–
–
V
CC + 0.3[4]
VCC + 0.3[4]
VCC + 0.5[4]
Input HIGH
voltage
V
V
–
2
–
–
2
–
–
–0.2[4]
–0.3[4]
–0.3[4]
–0.5[4]
–1
–
0.4
0.6
0.8
0.8
+1
–
–
Input LOW voltage
–
–
–
–
IIX
Input leakage current
Output leakage current
GND < VIN < VCC
–
A
A
IOZ
GND < VOUT < VCC, Output disabled
–1
–
+1
f = 100 MHz
f = 66.7 MHz
–
38
–
45
Max VCC, IOUT = 0 mA,
CMOS levels
ICC
Operating supply current
mA
–
40
Automatic CE power-down current – Max VCC, CE > VIH
,
ISB1
ISB2
–
–
–
6
15
8
mA
mA
TTL inputs IN > VIH or VIN < VIL, f = fMAX
V
Automatic CE power-down current – Max VCC, CE > VCC – 0.2 V,
CMOS inputs IN > VCC – 0.2 V or VIN < 0.2 V, f = 0
V
Notes
4. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC = 3 V
(for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
6. This parameter is guaranteed by design and not tested.
Document Number: 001-95413 Rev. *D
Page 5 of 18
CY7C1041GN
Capacitance
Parameter[7]
Description
Input capacitance
I/O capacitance
Test Conditions
48-ball VFBGA 44-pin SOJ 44-pin TSOP II Unit
CIN
TA = 25 C, f = 1 MHz,
CC = VCC(typ)
10
10
10
10
10
10
pF
pF
V
COUT
Thermal Resistance
Parameter[7]
Description
Test Conditions
48-ball VFBGA 44-pin SOJ 44-pin TSOP II Unit
Thermal resistance
(junction to ambient)
JA
JC
31.35
14.74
55.37
30.41
68.85
15.97
C/W
C/W
Still air, soldered on a
3 × 4.5 inch, four-layer
printed circuit board
Thermal resistance
(junction to case)
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms[8]
High-Z Characteristics:
R1
50
VCC
Output
VTH
Output
R2
Z = 50
30 pF*
0
5 pF*
* Including
jig and
scope
(a)
(b)
* Capacitive load consists
of all components of the
test environment
All Input Pulses
V
HIGH
90%
10%
90%
10%
GND
Fall Time:
> 1 V/ns
Rise Time:
> 1 V/ns
(c)
Parameters
R1
1.8 V
1667
1538
0.9
3.0 V
317
351
1.5
3
5.0 V
Unit
317
351
1.5
3
R2
VTH
V
VHIGH
1.8
V
Notes
7. Tested initially and after any design or process changes that may affect these parameters.
8. Full-device AC operation assumes a 100-µs ramp time from 0 to VCC(min) and a 100-µs wait time after VCC stabilization.
Document Number: 001-95413 Rev. *D
Page 6 of 18
CY7C1041GN
Data Retention Characteristics
Over the operating range of –40 C to 85 C
Parameter
VDR
Description
Conditions
Min
Max
Unit
VCC for data retention
1
–
V
VCC = 1.2 V, CE > VCC – 0.2 V[9]
VIN > VCC – 0.2 V, or VIN < 0.2 V
,
ICCDR
Data retention current
–
0
8
–
mA
ns
Chip deselect to data retention
time
[10]
tCDR
VCC > 2.2 V
VCC < 2.2 V
10
15
–
–
ns
ns
[9, 10]
tR
Operation recovery time
Data Retention Waveform
Figure 5. Data Retention Waveform[9]
DATA RETENTION MODE
VDR = 1.0 V
VCC
VCC(min)
tCDR
VCC(min)
tR
CE
Notes
9. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC (min) > 100 s.
10. These parameters are guaranteed by design.
Document Number: 001-95413 Rev. *D
Page 7 of 18
CY7C1041GN
AC Switching Characteristics
Over the operating range of –40 C to 85 C
10 ns
15 ns
Unit
Parameter[11]
Description
Min
Max
Min
Max
Read Cycle
tRC
Read cycle time
10
–
3
–
–
0
–
3
–
0
–
–
0
–
–
10
–
15
–
3
–
–
0
–
3
–
0
–
–
0
–
–
15
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data
tOHA
Data hold from address change
CE LOW to data[12]
tACE
10
4.5
–
15
8
tDOE
OE LOW to data
tLZOE
tHZOE
tLZCE
tHZCE
tPU
OE LOW to low impedance[13, 14]
OE HIGH to HI-Z[13, 14]
–
5
8
CE LOW to low impedance[12, 13, 14]
CE HIGH to HI-Z[12, 13, 14]
CE LOW to power-up[12, 14, 15]
CE HIGH to power-down[12, 14, 15]
Byte enable to data valid
Byte enable to low impedance[14]
Byte disable to HI-Z[14]
–
–
5
8
–
–
tPD
10
4.5
–
15
8
tDBE
tLZBE
tHZBE
Write Cycle[15, 16]
tWC Write cycle time
tSCE
tAW
–
6
8
10
7
7
0
0
7
5
0
3
–
7
–
–
–
–
–
–
–
–
–
5
–
15
12
12
0
–
–
–
–
–
–
–
–
–
8
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to write end [12]
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
tHA
tSA
0
tPWE
tSD
12
8
Data setup to write end
Data hold from write end
WE HIGH to low impedance [13, 14]
WE LOW to HI-Z [13, 14]
Byte Enable to write end
tHD
0
tLZWE
tHZWE
tBW
3
–
12
Notes
11. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V).Testconditionsforthereadcycleuseoutputloading, asshowninpart(a)ofFigure4onpage6, unlessspecifiedotherwise.
12. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
13. tHZOE, tHZCE, tHZWE, tHZBE, tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF, as shown in part (b) of Figure 4 on page 6. Transition is measured 200 mV from
steady state voltage.
14. These parameters are guaranteed by design and are not tested.
15. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
16. The minimum write cycle pulse width in Write Cycle No. 2 (WE Controlled, OE LOW) should be equal to sum of tSD and tHZWE
.
Document Number: 001-95413 Rev. *D
Page 8 of 18
CY7C1041GN
Switching Waveforms
Figure 6. Read Cycle No. 1 (Address Transition Controlled)[17, 18]
tRC
ADDRESS
tAA
tOHA
PREVIOUS DATAOUT
VALID
DATA I/O
DATAOUT VALID
Figure 7. Read Cycle No. 2 (OE Controlled)[18, 19]
ADDRESS
tRC
CE
OE
tPD
tHZCE
tACE
tHZOE
tDOE
tLZOE
BHE/
BLE
tDBE
tLZBE
tHZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
tLZCE
tPU
DATA I/O
DATAOUT VALID
VCC
SUPPLY
CURRENT
ISB
Notes
17. The device is continuously selected, OE = VIL, CE = VIL, BHE or BLE or both = VIL
.
18. WE is HIGH for the read cycle.
19. Address valid prior to or coincident with CE LOW transition.
Document Number: 001-95413 Rev. *D
Page 9 of 18
CY7C1041GN
Switching Waveforms (continued)
Figure 8. Write Cycle No. 1 (CE Controlled)[20, 21]
tW
C
A D D R E S S
tS A
t S C
E
C E
tA
W
tH
A
t P W
E
W E
tB W
B H E/
B L E
O E
t H
tH
D
Z O
E
tS
D
D A T A I / O
D A T AIN V A L ID
Figure 9. Write Cycle No. 2 (WE Controlled, OE LOW)[20, 21, 22]
tW C
AD DRESS
tSCE
CE
tBW
BH E
BLE
/
tAW
tHA
tSA
tPW E
W E
tLZW E
t
tSD
HZW E
tHD
VALID
DATA I /O
DATA
IN
Notes
20. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
21. Data I/O is in HI-Z state if CE = VIH, or OE = VIH, or BHE, and/or BLE = VIH
.
22. The minimum write cycle pulse width should be equal to sum of tSD and tHZWE
.
Document Number: 001-95413 Rev. *D
Page 10 of 18
CY7C1041GN
Switching Waveforms (continued)
Figure 10. Write Cycle No. 3 (BLE or BHE Controlled)[23, 24]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tBW
BHE/
BLE
tPWE
WE
tHD
tHZWE
tLZWE
tSD
DATAIN VALID
DATA I /O
Figure 11. Write Cycle No. 4 (WE Controlled)[23, 24, 25]
tWC
ADDRESS
CE1
tSCE
CE2
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tHD
tSD
NOTE 26
DATA I/O
DATA IN VALID
tHZOE
Notes
23. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
24. Data I/O is in HI-Z state if CE = VIH, or OE = VIH, or BHE, and/or BLE = VIH
.
25. Data I/O is high impedance if OE = VIH
.
26. During this period the I/Os are in output state. Do not apply input signals.
Document Number: 001-95413 Rev. *D
Page 11 of 18
CY7C1041GN
Truth Table
CE
H
L
OE WE BLE BHE I/O0–I/O7 I/O8–I/O15
Mode
Power
X[27] X[27] X[27] X[27]
HI-Z
Data out
Data out
HI-Z
HI-Z
Data out Read all bits
HI-Z Read lower bits only
Power down
Standby (ISB)
L
L
H
H
H
L
L
L
L
H
L
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
)
)
L
L
L
H
L
Data out Read upper bits only
Data in Write all bits
L
X
X
X
H
L
Data in
Data in
HI-Z
L
L
L
H
L
HI-Z
Data in Write upper bits only
HI-Z Selected, outputs disabled
Write lower bits only
L
L
H
X
L
H
X
HI-Z
Notes
27. The input voltage levels on these pins should be either at VIH or VIL
.
Document Number: 001-95413 Rev. *D
Page 12 of 18
CY7C1041GN
Ordering Information
Speed
(ns)
Voltage
Range
Package
Diagram
Package Type
(all Pb-free)
Operating
Range
Ordering Code
CY7C1041GN30-10ZSXI
CY7C1041GN30-10ZSXI
CY7C1041GN30-10VXI
CY7C1041GN30-10VXIT
CY7C1041GN30-10BVXI
CY7C1041GN30-10BVXIT
CY7C1041GN30-10BVJXI
CY7C1041GN30-10BVJXIT
CY7C1041GN-10ZSXI
CY7C1041GN-10ZSXIT
CY7C1041GN-10VXI
51-85087 44-pin TSOP II
51-85087 44-pin TSOP II, Tape & Reel
51-85082 44-pin SOJ
51-85082 44-pin SOJ, Tape & Reel
51-85150 48-ball VFBGA (6 × 8 × 1.0 mm)
2.2 V–3.6 V
48-ball VFBGA (6 × 8 × 1.0 mm), Tape & Reel
51-85150
51-85150
10
Industrial
48-ball VFBGA (6 × 8 × 1.0 mm), JEDEC Compatible
51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), JEDEC Compatible, Tape & Reel
51-85087 44-pin TSOP II
51-85087 44-pin TSOP II, Tape & Reel
51-85082 44-pin SOJ
4.5 V–5.5 V
CY7C1041GN-10VXIT
51-85082 44-pin SOJ, Tape & Reel
Ordering Code Definitions
CY 7 1 04 1 GN XX
-
XX
X
X
C
XX
I
X: T = Tape & Reel; Blank = Bulk
Temperature Range: I = Industrial
Pb-free
Package Type: XX = ZS or BV or BVJ
ZS = 44-pin TSOP II; V = 44-pin SOJ; BV = 48-ball VFBGA;
BVJ = 48-ball VFBGA JEDEC Compatible
Speed: XX = 10 ns
Voltage Range:
30 = 2.2 V–3.6 V
Process Technology: Revision Code “GN” = 65 nm
Data Width: 1 = × 16-bits
Density: 04 = 4-Mbit
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-95413 Rev. *D
Page 13 of 18
CY7C1041GN
Package Diagrams
Figure 12. 44-pin TSOP II (Z44) Package Outline, 51-85087
51-85087 *E
Figure 13. 44-pin SOJ (400 Mils) Package Outline, 51-85082
51-85082 *E
Document Number: 001-95413 Rev. *D
Page 14 of 18
CY7C1041GN
Package Diagrams (continued)
Figure 14. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *H
Document Number: 001-95413 Rev. *D
Page 15 of 18
CY7C1041GN
Acronyms
Document Conventions
Units of Measure
Acronym
Description
BHE
BLE
byte high enable
Symbol
°C
Unit of Measure
byte low enable
chip enable
Degrees Celsius
megahertz
microamperes
microseconds
milliamperes
millimeters
nanoseconds
ohms
MHz
A
s
CE
CMOS
I/O
complementary metal oxide semiconductor
input/output
mA
mm
ns
OE
output enable
SRAM
TSOP
TTL
static random-access memory
thin small outline package
transistor-transistor logic
very fine-pitch ball grid array
write enable
%
percent
VFBGA
WE
pF
V
picofarads
volts
W
watts
Document Number: 001-95413 Rev. *D
Page 16 of 18
CY7C1041GN
Document History Page
Document Title: CY7C1041GN, 4-Mbit (256K words × 16 bit) Static RAM
Document Number: 001-95413
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
5074414
NILE
NILE
VINI
VINI
01/06/2016 New data sheet.
Updated Logic Block Diagram – CY7C1041GN.
01/12/2016 Updated Ordering Information:
*A
*B
*C
5082573
5120171
5322961
Updated part numbers.
02/01/2016 Updated Logic Block Diagram – CY7C1041GN.
Updated Ordering Information:
06/24/2016 Updated part numbers.
Updated to new template.
Updated Ordering Information: Updated part numbers. Added Tape & Reel
ordering codes.
Updated DC Electrical Characteristics: Enhanced VOH for voltage range 3.0V
09/09/2016 to 3.6V from 2.2V to 2.4V. Enhanced VIH for voltage range 4.5V to 5.5V from
*D
5431651
NILE
2.2V to 2.0V.
Updated Note 4.
Updated Copyright and Disclaimer.
Document Number: 001-95413 Rev. *D
Page 17 of 18
CY7C1041GN
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
ARM® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Forums | Projects | Video | Blogs | Training | Components
Technical Support
Internet of Things
Lighting & Power Control
Memory
cypress.com/support
cypress.com/powerpsoc
cypress.com/memory
cypress.com/psoc
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including
any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide.
Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual
property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby
grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and
reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided
by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-95413 Rev. *D
Revised September 9, 2016
Page 18 of 18
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