CY7C1041 [CYPRESS]
256K x 16 Static RAM; 256K ×16静态RAM
| 型号： | CY7C1041 |
| 厂家： | 
CYPRESS |
| 描述： | 256K x 16 Static RAM |
| 文件： | 总10页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1041
256K x 16 Static RAM
written into the location specified on the address pins (A
Features
0
through A ). If Byte High Enable (BHE) is LOW, then data
17
• High speed
from I/O pins (I/O through I/O ) is written into the location
8
15
specified on the address pins (A through A ).
0
17
— t = 15 ns
AA
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O to I/O . If Byte High Enable (BHE) is LOW,
• Low active power
— 1430 mW (max.)
• Low CMOS standby power (L version)
— 2.75 mW (max.)
0
7
then data from memory will appear on I/O to I/O . See the
8
15
2.0V Data Retention (400 W at 2.0V retention)
•
µ
truth table at the back of this data sheet for a complete descrip-
tion of read and write modes.
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
The input/output pins (I/O through I/O ) are placed in a
0
15
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Functional Description
The CY7C1041 is a high-performance CMOS static RAM or-
ganized as 262,144 words by 16 bits.
The CY7C1041 is available in a standard 44-pin 400-mil-wide
body width SOJ and 44-pin TSOP II package with center pow-
er and ground (revolutionary) pinout.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O through I/O ), is
0
7
Logic Block Diagram
Pin Configuration
SOJ
TSOP II
Top View
INPUT BUFFER
A
44
1
0
A
A
A
A
OE
BHE
BLE
I/O
I/O
14
I/O
0
17
16
15
A
43
42
41
40
39
38
1
A
2
3
4
5
6
1
A
2
A
2
I/O0 – I/O7
I/O8 – I/O15
256K x 16
ARRAY
A
3
4
A
3
A
A
4
1024 x 4096
A
5
6
CE
I/O
A
7
0
15
A
7
8
37
36
35
34
33
I/O
8
1
2
A
I/O
9
13
10
11
12
13
I/O
I/O
3
CC
SS
12
V
V
SS
COLUMN
DECODER
V
V
CC
I/O
32
I/O
4
11
I/O
31
30
29
28
I/O
10
14
15
16
5
I/O
I/O
6
9
8
I/O
I/O
7
WE 17
NC
BHE
18
27
26
25
A
14
A
5
WE
CE
OE
19
A
6
A
13
A
20
21
22
A
7
12
A
BLE
A
24
23
11
8
9
A
A
10
1041–1
1041–2
Selection Guide
7C1041-12
7C1041-15
7C1041-17
7C1041-20
7C1041-25
Maximum Access Time (ns)
12
280
3
15
260
3
17
250
3
20
230
3
25
220
3
Maximum Operating Current (mA)
Maximum CMOS Standby Current Com’l
(mA)
Com’l
L
0.5
6
0.5
6
0.5
6
0.5
6
0.5
6
Ind’l
Shaded areas contain preliminary information.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
October 4, 1999
CY7C1041
[1]
DC Input Voltage ................................ –0.5V to V + 0.5V
Maximum Ratings
CC
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Operating Range
Storage Temperature .................................–65°C to +150°C
Ambient
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
[2]
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
V
CC
5V ± 0.5
[1]
Supply Voltage on V to Relative GND .... –0.5V to +7.0V
CC
DC Voltage Applied to Outputs
[1]
in High Z State ....................................–0.5V to V + 0.5V
CC
Electrical Characteristics Over the Operating Range
7C1041-12
7C1041-15
7C1041-17
Parameter
Description
Test Conditions
= Min., I = –4.0 mA
Min.
Max.
Min.
Max.
Min.
Max. Unit
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
V
V
2.4
2.4
2.4
V
OH
OL
IH
CC
CC
OH
V
V
= Min., I = 8.0 mA
0.4
0.4
0.4
V
V
OL
2.2
V
2.2
V
2.2
V
CC
CC
CC
+ 0.5
0.8
+1
+ 0.5
0.8
+1
+ 0.5
[1]
V
Input LOW Voltage
–0.5
–1
–0.5
–1
–0.5
–1
0.8
+1
+1
V
IL
I
I
Input Load Current
GND < V < V
CC
µA
µA
IX
I
Output Leakage
Current
GND < V
< V ,
CC
–1
+1
–1
+1
–1
OZ
OUT
Output Disabled
I
I
V
Operating
V
CC
= Max.,
280
40
260
40
250
40
mA
mA
CC
SB1
CC
Supply Current
f = f
= 1/t
MAX RC
Automatic CE
Max. V , CE > V
CC IH
Power-Down Current
—TTL Inputs
V
V
> V or
IN
IN
IH
< V , f = f
IL
MAX
I
Automatic CE
Power-Down Current CE > V – 0.3V,
—CMOS Inputs
Max. V
,
CC
Com’l
Com’l
3
0.5
6
3
0.5
6
3
0.5
6
mA
mA
mA
SB2
CC
L
V
> V – 0.3V,
IN CC
or V < 0.3V, f = 0 Ind’l
IN
Shaded areas contain preliminary information.
Notes:
1.
VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the case temperature.
2
CY7C1041
Electrical Characteristics Over the Operating Range (continued)
Test Conditions
7C1041-20
7C1041-25
Parameter
Description
Min.
Max.
Min.
Max.
Unit
V
V
V
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
V
V
= Min., I = –4.0 mA
OH
2.4
2.4
OH
OL
IH
CC
CC
= Min., I = 8.0 mA
0.4
0.4
V
OL
2.2
V
2.2
V
+ 0.5
CC
V
CC
+ 0.5
0.8
+1
[1]
V
Input LOW Voltage
–0.5
–1
–0.5
–1
0.8
+1
+1
V
IL
I
I
Input Load Current
GND < V < V
CC
µA
µA
IX
I
Output Leakage
Current
GND < V
< V
,
–1
+1
–1
OZ
OUT
CC
Output Disabled
I
I
V
Operating
V
CC
= Max.,
230
40
220
40
mA
mA
CC
SB1
CC
Supply Current
f = f
= 1/t
MAX RC
Automatic CE
Max. V , CE > V
CC
IH
Power-Down Current
—TTL Inputs
V
V
> V or
IN
IN
IH
< V , f = f
IL
MAX
I
Automatic CE
Power-Down Current
—CMOS Inputs
Max. V
CE > V – 0.3V,
,
Com’l
Com’l
Ind’l
3
0.5
6
3
0.5
6
mA
mA
mA
SB2
CC
CC
L
V
> V – 0.3V,
CC
IN
or V < 0.3V, f = 0
IN
Capacitance[3]
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
pF
C
C
Input Capacitance
I/O Capacitance
8
8
IN
A
V
= 5.0V
CC
pF
OUT
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
ALL INPUT PULSES
90%
R1 481
Ω
R1 481
Ω
5V
5V
3.0V
GND
90%
10%
OUTPUT
OUTPUT
10%
R2
255
R2
255
30 pF
5 pF
Ω
Ω
3 ns
3 ns
≤
≤
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(b)
1041–3
(a)
1041–4
THÉ
VENIN EQUIVALENT
Equivalent to:
167
Ω
1.73V
OUTPUT
3
CY7C1041
Switching Characteristics[4] Over the Operating Range
7C1041-12
Min. Max.
7C1041-15
Min. Max.
7C1041-17
Min. Max.
Parameter
Description
Unit
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
12
3
15
3
17
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
12
15
17
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
12
6
15
7
17
7
0
3
0
0
3
0
0
3
0
[5, 6]
OE HIGH to High Z
6
6
7
7
7
7
[6]
CE LOW to Low Z
[5, 6]
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
12
6
15
7
17
7
PD
DBE
LZBE
HZBE
0
0
0
Byte Disable to High Z
6
7
7
[7, 8]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
12
10
10
0
15
12
12
0
17
14
14
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
HA
0
0
0
SA
10
7
12
8
14
8
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
0
0
0
HD
[6]
WE HIGH to Low Z
3
3
3
LZWE
HZWE
BW
[5, 6]
WE LOW to High Z
6
7
7
Byte Enable to End of Write
10
12
12
Shaded areas contain preliminary information.
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5.
tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. The internal write time of the memory is defined by the overlap of CELOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
4
CY7C1041
Switching Characteristics[4] Over the Operating Range (continued)
7C1041-20
7C1041-25
Min. Max.
Parameter
Description
Min.
Max.
Unit
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
20
3
25
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
20
25
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
20
8
25
10
0
3
0
0
5
0
[5, 6]
OE HIGH to High Z
8
8
10
10
[6]
CE LOW to Low Z
[5, 6]
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
20
8
25
10
PD
DBE
LZBE
HZBE
0
0
Byte Disable to High Z
8
10
[7, 8]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
20
13
13
0
25
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
HA
0
0
SA
13
9
15
10
0
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
0
HD
[6]
WE HIGH to Low Z
3
5
LZWE
HZWE
BW
[5, 6]
WE LOW to High Z
8
10
Byte Enable to End of Write
13
15
Data Retention Characteristics Over the Operating Range
[10]
Parameter
Description
for Data Retention
Conditions
Min.
2.0
Max.
200
Unit
V
V
V
CC
DR
I
Data Retention Current
V
= V = 2.0V,
µA
µA
µA
ns
CCDR
CC
DR
CE > V – 0.3V,
CC
Com’l L
V
> V – 0.3V or V < 0.3V
IN
CC IN
[3]
t
t
Chip Deselect to Data Retention Time
Operation Recovery Time
0
CDR
[9]
R
See Note 9
Notes:
9. tr < 100 µs for all speeds.
10. No input may exceed VCC + 0.5V.
5
CY7C1041
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
V
V
CC
DR
t
t
R
CDR
CE
1041–5
Switching Waveforms
[11, 12]
Read Cycle No.1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
1041-6
[12, 13]
Read Cycle No.2 (OE Controlled)
ADDRESS
t
RC
CE
t
ACE
OE
t
HZOE
t
DOE
BHE, BLE
t
LZOE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
I
t
CC
PU
V
CC
50%
50%
SUPPLY
CURRENT
I
SB
1041-7
Notes:
11. Device is continuously selected. OE, CE, BHE, and/or BHE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
6
CY7C1041
Switching Waveforms (continued)
[14, 15]
Write Cycle No. 1 (CE Controlled)
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATAI/O
1041-8
Write Cycle No. 2 (BLEor BHE Controlled)
t
WC
ADDRESS
t
SA
t
BW
BHE, BLE
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
HD
SD
DATAI/O
1041-9
Notes:
14. Data I/O is high impedance if OE or BHE and/or BLE= VIH
.
15. If CEgoes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
7
CY7C1041
Switching Waveforms (continued)
Write Cycle No.3
Controlled, LOW)
(WE
t
WC
ADDRESS
t
SCE
CE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
SD
t
HD
DATA I/O
t
LZWE
1041-10
Truth Table
CE
H
L
OE WE BLE
BHE
X
I/O –I/O
I/O –I/O
15
Mode
Power
0
7
8
X
L
X
H
H
H
L
X
L
High Z
High Z
Power Down
Read All Bits
Standby (I
)
SB
L
Data Out
Data Out
High Z
Data Out
High Z
Active (I
Active (I
Active (I
Active (I
Active (I
Active (I
Active (I
)
)
)
)
)
)
)
CC
CC
CC
CC
CC
CC
CC
L
L
L
H
L
Read Lower Bits Only
Read Upper Bits Only
Write All Bits
L
L
H
L
Data Out
Data In
High Z
L
X
X
X
H
L
Data In
Data In
High Z
L
L
L
H
L
Write Lower Bits Only
Write Upper Bits Only
Selected, Outputs Disabled
L
L
H
X
Data In
High Z
L
H
X
High Z
8
CY7C1041
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Lead TSOP Type II
15
CY7C1041-15VC
CY7C1041L-15VC
CY7C1041-15ZC
CY7C1041L-15ZC
CY7C1041-17VC
CY7C1041L-17VC
CY7C1041-17ZC
CY7C1041L-17ZC
CY7C1041-20VC
CY7C1041L-20VC
CY7C1041-20ZC
CY7C1041L-20ZC
CY7C1041-25VC
CY7C1041L-25VC
CY7C1041-25ZC
CY7C1041L-25ZC
CY7C1041-15ZI
CY7C1041-15VI
CY7C1041-17ZI
CY7C1041-17VI
CY7C1041-20ZI
CY7C1041-20VI
CY7C1041-25ZI
CY7C1041-25VI
V34
V34
Z44
Z44
V34
V34
Z44
Z44
V34
V34
Z44
Z44
V34
V34
Z44
Z44
Z44
V34
V34
Z44
Z44
Z44
Z44
Z44
Commercial
44-Lead TSOP Type II
17
20
25
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Lead TSOP Type II
44-Lead TSOP Type II
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Lead TSOP Type II
44-Lead TSOP Type II
44-Lead (400-Mil) Molded SOJ
44-Lead (400-Mil) Molded SOJ
44-Lead TSOP Type II
44-Lead TSOP Type II
15
17
20
25
44-Lead TSOP Type II
Industrial
44-Lead (400-Mil) Molded SOJ
44-Lead TSOP Type II
44-Lead (400-Mil) Molded SOJ
44-Lead TSOP Type II
44-Lead (400-Mil) Molded SOJ
44-Lead TSOP Type II
44-Lead (400-Mil) Molded SOJ
Document #: 38-00644-B
9
CY7C1041
Package Diagrams
44-Lead (400-Mil) Molded SOJ V34
51-85082-B
44-Pin TSOP II Z44
51-85087-A
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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