CY7C1046BV33 [CYPRESS]
1M x 4 Static RAM; 1M ×4静态RAM
| 型号： | CY7C1046BV33 |
| 厂家： | 
CYPRESS |
| 描述： | 1M x 4 Static RAM |
| 文件： | 总8页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
046BV33
PRELIMINARY
CY7C1046BV33
1M x 4 Static RAM
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. Writ-
ing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. Data on the four I/O pins
(I/O0 through I/O3) is then written into the location specified on
the address pins (A0 through A19).
Features
• High speed
— tAA = 10 ns
• Low active power for 10 ns speed
— 540 mW (max.)
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
• Low CMOS standby power (L version)
— 1.8 mW (max.)
• 2.0V Data Retention (400 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
The four input/output pins (I/O0 through I/O3) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
Functional Description
The CY7C1046BV33 is available in a standard 400-mil-wide
32-pin SOJ package with center power and ground (revolution-
ary) pinout.
The CY7C1046BV33 is a high-performance CMOS static
RAM organized as 1,048,576 words by 4 bits. Easy memory
Logic Block Diagram
Pin Configuration
SOJ
Top View
A
32
31
30
29
28
1
2
3
4
5
6
A
0
19
A
1
A
A
A
A
18
17
16
15
A
2
A
A
3
4
INPUT BUFFER
A
0
CE
27
26
25
OE
I/O
GND
A
1
I/O
7
8
0
A
3
2
I/O
0
V
A
CC
3
4
A
24
23
GND
9
10
11
V
I/O
CC
A
6
I/O
I/O
I/O
5
1
2
3
1M x 4
I/O
A
2
1
ARRAY
A
WE
22
21
20
19
18
17
A
7
14
13
12
A
8
A
A
A
A
A
A
12
13
14
15
16
5
9
A
6
A
10
A
7
11
10
A
8
POWER
DOWN
COLUMN
DECODER
A
CE
NC
9
WE
1046BV33–1
1046BV33–2
OE
Selection Guide
7C1046BV33-10 7C1046BV33-12 7C1046BV33-15
Maximum Access Time (ns)
10
150
8
12
140
8
15
130
8
Maximum Operating Current (mA)
Maximum CMOS Standby
Current (mA)
Com’l
L version
0.5
0.5
0.5
Shaded areas contain advance information.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05170 Rev. **
Revised September 21, 2001
PRELIMINARY
CY7C1046BV33
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V
Range
Temperature[2]
VCC
DC Voltage Applied to Outputs
Commercial
0°C to +70°C
3.0V - 3.6V
in High Z State[1]....................................–0.5V to VCC + 0.5V
DC Input Voltage[1] ................................–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range
7C1046BV33-10 7C1046BV33-12 7C1046BV33-15
Parameter
VOH
Description
Test Conditions
Min.
Max.
Min.
Max.
Min.
Max. Unit
Output HIGH Voltage VCC = Min., IOH = –4.0 mA
Output LOW Voltage VCC = Min., IOL = 8.0 mA
Input HIGH Voltage
2.4
2.4
2.4
V
VOL
0.4
0.4
0.4
V
V
VIH
2.2
VCC
2.2
VCC
2.2
VCC
+ 0.5
+ 0.5
+ 0.5
VIL
IIX
Input LOW Voltage[1]
–0.5
–1
0.8
+1
+1
–0.5
–1
0.8
+1
+1
–0.5
–1
0.8
+1
+1
V
Input Load Current
GND < VI < VCC
µA
µA
IOZ
Output Leakage
Current
GND < VOUT < VCC
Output Disabled
,
–1
–1
–1
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
150
20
140
20
130
20
mA
mA
ISB1
Automatic CE
Max. VCC, CE > VIH
Power-Down Current VIN > VIH or
—TTL Inputs
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current CE > VCC – 0.3V,
—CMOS Inputs
Max. VCC
,
Com’l
8
8
8
mA
L version
0.5
0.5
0.5
VIN > VCC – 0.3V,
or VIN < 0.3V,
f = 0
Shaded areas contain advance information.
Capacitance[3]
Parameter
Description
Input Capacitance
I/O Capacitance
Test Conditions
Max.
Unit
pF
CIN
TA = 25°C, f = 1 MHz,
VCC = 3.3V
6
6
COUT
pF
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. A is the “Instant On” case temperature.
T
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05170 Rev. **
Page 2 of 8
PRELIMINARY
CY7C1046BV33
AC Test Loads and Waveforms
ALL INPUT PULSES
90%
10%
Ω
R1 317
R1 317Ω
3.3V
GND
3.3V
OUTPUT
3.3V
90%
10%
OUTPUT
R2
351Ω
R2
351Ω
30 pF
5 pF
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
Fall Time: 1 V/ns
Rise Time: 1 V/ns
(b)
1046BV33–3
(a)
1046BV33–4
THÉ
Equivalent to:
OUTPUT
VENIN EQUIVALENT
167Ω
1.73V
Switching Characteristics[4] Over the Operating Range
7C1046BV33-10 7C1046BV33-12 7C1046BV33-15
Parameter
Description
Min.
10
3
Max.
Min.
Max.
Min.
15
3
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
Address to Data Valid
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
10
12
15
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[6]
OE HIGH to High Z[5, 6]
CE LOW to Low Z[6]
CE HIGH to High Z[5, 6]
CE LOW to Power-Up
CE HIGH to Power-Down
3
10
4
12
6
15
7
0
3
0
0
3
0
0
3
0
5
5
6
6
7
7
tPD
10
12
15
WRITE CYCLE[7, 8]
tWC
tSCE
tAW
Write Cycle Time
10
7
12
10
10
0
15
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
7
tHA
0
tSA
0
0
0
tPWE
tSD
7
10
7
12
8
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[6]
5
tHD
0
0
0
tLZWE
tHZWE
3
3
3
WE LOW to High Z[5, 6]
5
6
7
Shaded areas contain advance information.
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5.
tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
Document #: 38-05170 Rev. **
Page 3 of 8
PRELIMINARY
CY7C1046BV33
s
Data Retention Characteristics Over the Operating Range
Parameter
VDR
Description
VCC for Data Retention
Conditions[10]
Min.
Max Unit
2.0
V
ICCDR
Data Retention Current
Com’l
VCC = VDR = 2.0V,
CE > VCC – 0.3V
VIN > VCC – 0.3V or VIN < 0.3V
200
µA
ns
µs
[3]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
[9]
tR
10
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
V
V
CC
DR
t
t
R
CDR
CE
1046BV33–5
Switching Waveforms
Read Cycle No. 1[11, 12]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
1046BV33–6
Read Cycle No. 2 (OE Controlled)[12, 13]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
I
t
PU
CC
V
CC
50%
50%
SUPPLY
CURRENT
I
SB
1046BV33-7
Notes:
9. tr < 3 ns for the -10, -12, and -15 speeds.
10. No input may exceed VCC + 0.5V.
11. Device is continuously selected. OE, CE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05170 Rev. **
Page 4 of 8
PRELIMINARY
CY7C1046BV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[14, 15]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
1046BV33–8
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 16
t
HZOE
1046BV33–9
Notes:
14. Data I/O is high impedance if OE = VIH
.
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
16. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05170 Rev. **
Page 5 of 8
PRELIMINARY
CY7C1046BV33
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[15]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 16
DATA I/O
DATA VALID
t
t
LZWE
HZWE
1046BV33–10
Truth Table
CE
H
L
OE
X
WE
X
I/O0 - I/O7
Mode
Power
High Z
Power-Down
Read
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
L
H
Data Out
Data In
High Z
)
L
X
L
Write
)
L
H
H
Selected, Outputs Disabled
)
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
10
12
15
10
12
15
Ordering Code
CY7C1046BV33-10VC
Package Type
32-Lead (400-Mil) Molded SOJ
32-Lead (400-Mil) Molded SOJ
32-Lead (400-Mil) Molded SOJ
32-Lead (400-Mil) Molded SOJ
32-Lead (400-Mil) Molded SOJ
32-Lead (400-Mil) Molded SOJ
V33
V33
V33
V33
V33
V33
Commercial
CY7C1046BV33-12VC
CY7C1046BV33-15VC
CY7C1046BV33L-10VC
CY7C1046BV33L-12VC
CY7C1046BV33L-15VC
Shaded areas contain pre-release information.
Document #: 38-05170 Rev. **
Page 6 of 8
PRELIMINARY
CY7C1046BV33
Package Diagram
32-Lead (400-Mil) Molded SOJ V33
51-85033-A
Document #: 38-05170 Rev. **
Page 7 of 8
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
CY7C1046BV33
Document Title: CY7C1046BV33 1M x 4 Static RAM
Document Number: 38-05170
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
110210
12/02/01
SZV
Change from Spec number: 38-00949 to 38-05170
Document #: 38-05170 Rev. **
Page 8 of 8
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