CY7C1049BN-17VC [CYPRESS]
512K x 8 Static RAM; 512K ×8静态RAM
| 型号： | CY7C1049BN-17VC |
| 厂家： | 
CYPRESS |
| 描述： | 512K x 8 Static RAM |
| 文件： | 总10页 (文件大小：454K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1CY7C1049BN
CY7C1049BN
512K x 8 Static RAM
Features
Functional Description[1]
• High speed
The CY7C1049BN is a high-performance CMOS static RAM
organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A18).
— tAA = 12 ns
• Low active power
— 1320 mW (max.)
• Low CMOS standby power (Commercial L version)
— 2.75 mW (max.)
• 2.0V Data Retention (400 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1049BN is available in a standard 400-mil-wide
36-pin SOJ package with center power and ground (revolu-
tionary) pinout.
Logic Block Diagram
Pin Configuration
SOJ
Top View
A
A
36
35
34
33
32
1
NC
0
1
2
3
4
A
A
A
A
18
17
16
15
A
2
A
A
3
4
5
CE
31
30
29
28
6
OE
I/O
I/O
7
8
9
0
1
7
I/O
I/O
V
I/O
6
0
GND
INPUT BUFFER
CC
27
26
25
GND
10
11
12
13
V
CC
A
1
0
A
I/O
I/O
I/O
I/O
A
A
A
A
A
I/O
1
5
4
2
I/O3
WE
A
2
24
23
22
21
20
19
14
2
A
A
5
3
14
15
16
17
18
13
A
A
4
12
6
A
7
A
11
10
5
I/O
I/O
I/O
3
4
5
512K x 8
ARRAY
A
A
8
6
A
9
NC
A
7
A
8
A
9
A
10
I/O
6
7
POWER
DOWN
COLUMN
DECODER
CE
I/O
WE
OE
Cypress Semiconductor Corporation
Document #: 001-06501 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 2, 2006
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CY7C1049BN
Selection Guide
7C1049BN-12 7C1049BN-15 7C1049BN-17 7C1049BN-20 7C1049BN-25
Maximum Access Time (ns)
12
15
17
195
8
20
185
8
25
180
8
Maximum Operating Current (mA)
240
220
Maximum CMOS Standby
Current (mA)
Com’l
8
-
8
-
Com’l/Ind’l L
Ind’l
0.5
-
0.5
9
0.5
9
-
-
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage............................................>2001V
(Above which the useful life may be impaired. For user guide-
(per MIL-STD-883, Method 3015)
lines, not tested.)
Latch-Up Current.....................................................>200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
Supply Voltage on VCC to Relative GND[2] .... –0.5V to +7.0V
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VCC
DC Voltage Applied to Outputs
4.5V–5.5V
in High Z State[2] ....................................–0.5V to VCC + 0.5V
DC Input Voltage[2].................................–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
7C1049B-12
7C1049B-15
7C1049B-17
Min.
Max.
Min.
Max.
Min.
Max. Unit
VOH
VOL
VIH
VIL
Output HIGH Voltage VCC = Min., IOH = –4.0 mA
Output LOW Voltage VCC = Min., IOL = 8.0 mA
Input HIGH Voltage
2.4
2.4
2.4
V
0.4
0.4
0.4
V
V
2.2 VCC+0.3 2.2 VCC+0.3 2.2 VCC+0.3
Input LOW Voltage[2]
–0.3
–1
0.8
+1
+1
–0.3
–1
0.8
+1
+1
–0.3
–1
0.3
+1
+1
V
IIX
Input Load Current
GND < VI < VCC
µA
µA
IOZ
Output Leakage
Current
GND < VOUT < VCC
Output Disabled
,
–1
–1
–1
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
240
40
220
40
195
40
mA
mA
ISB1
Automatic CE
Max. VCC, CE > VIH
Power-Down Current VIN > VIH or
—TTL Inputs
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current CE > VCC – 0.3V,
—CMOS Inputs IN > VCC – 0.3V,
Max. VCC
,
Com’l
Com’l
8
-
8
-
8
mA
mA
mA
mA
L
L
0.5
8
V
or VIN < 0.3V, f = 0 Ind’l
-
-
Ind’l
-
-
0.5
Note:
2. Minimum voltage is–2.0V for pulse durations of less than 20 ns.
Document #: 001-06501 Rev. **
Page 2 of 10
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CY7C1049BN
Electrical Characteristics Over the Operating Range (continued)
Test Conditions
7C1049B-20
7C1049B-25
Parameter
VOH
Description
Min.
Max.
Min.
Max.
Unit
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[2]
Input Load Current
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
2.4
2.4
VOL
VIH
VIL
IIX
0.4
VCC + 0.3
0.8
0.4
V
2.2
–0.3
–1
2.2 VCC + 0.3
V
–0.3
–1
0.8
+1
+1
V
GND < VI < VCC
+1
µA
µA
IOZ
Output Leakage
Current
GND < VOUT < VCC
Output Disabled
,
–1
+1
–1
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
185
40
180
40
mA
mA
ISB1
Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
V
IN < VIL, f = fMAX
Max. VCC
CE > VCC – 0.3V,
IN > VCC – 0.3V,
or VIN < 0.3V, f = 0
ISB2
Automatic CE
Power-Down Current
—CMOS Inputs
,
Com’l
Com’l
Ind’l
8
8
mA
mA
mA
mA
L
L
0.5
8
0.5
8
V
Ind’l
0.5
0.5
Capacitance[3]
Parameter
Description
Test Conditions
Max.
Unit
pF
CIN
Input Capacitance
I/O Capacitance
TA = 25°C, f = 1 MHz,
CC = 5.0V
8
8
V
COUT
pF
AC Test Loads and Waveforms
ALL INPUT PULSES
90%
R1 481Ω
R1 481Ω
5V
5V
OUTPUT
3.0V
90%
10%
OUTPUT
10%
R2
255Ω
R2
255Ω
GND
≤ 3 ns
30 pF
5 pF
≤ 3 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(b)
(a)
THÉ
Equivalent to:
VENIN EQUIVALENT
167Ω
1.73V
OUTPUT
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-06501 Rev. **
Page 3 of 10
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CY7C1049BN
Switching Characteristics[4] Over the Operating Range
7C1049B-12
7C1049B-15
7C1049B-17
Parameter
Read Cycle
tpower
tRC
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
VCC(typical) to the First Access[5]
Read Cycle Time
1
1
1
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
15
17
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[7]
OE HIGH to High Z[6, 7]
CE LOW to Low Z[7]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
12
15
17
tOHA
3
3
3
tACE
12
6
15
7
17
8
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
0
3
0
0
3
0
0
3
0
6
6
7
7
7
7
tPD
12
15
17
Write Cycle[8, 9]
tWC
tSCE
tAW
tHA
Write Cycle Time
12
10
10
0
15
12
12
0
17
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tSA
0
0
0
tPWE
tSD
10
7
12
8
12
8
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[7]
tHD
0
0
0
tLZWE
3
3
3
tHZWE
WE LOW to High Z[6, 7]
6
7
8
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I and 30-pF load capacitance.
OL OH
5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. t
started.
time has to be provided initially before a read/write operation is
power
6. t
, t
, and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
HZWE
HZOE HZCE
7. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of
either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
and t
.
SD
HZWE
Document #: 001-06501 Rev. **
Page 4 of 10
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CY7C1049BN
Switching Characteristics[4] Over the Operating Range (continued)
7C1049B-20
Min. Max.
7C1049B-25
Parameter
Read Cycle
tpower
tRC
Description
Min.
Max.
Unit
VCC(typical) to the First Access[5]
Read Cycle Time
1
1
1
20
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[7]
OE HIGH to High Z[6, 7]
CE LOW to Low Z[7]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
20
25
tOHA
3
5
tACE
20
8
25
10
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
0
3
0
0
5
0
8
8
10
10
25
tPD
20
Write Cycle[8]
tWC
Write Cycle Time
20
13
13
0
25
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tAW
tHA
tSA
0
0
tPWE
13
9
15
10
0
tSD
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[7]
tHD
0
tLZWE
tHZWE
3
5
WE LOW to High Z[6, 7]
8
10
Data Retention Characteristics Over the Operating Range
Parameter
VDR
Description
VCC for Data Retention
Conditions[11]
Min.
Max
Unit
V
2.0
ICCDR
Data Retention Current
Com’l
Ind’l
L
VCC = VDR = 3.0V,
CE > VCC – 0.3V
VIN > VCC – 0.3V or VIN < 0.3V
200
1
µA
mA
ns
[3]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
[10]
tR
tRC
ns
Notes:
10. t < 3 ns for the -12 and -15 speeds. t < 5 ns for the -20 and slower speeds.
r
r
11. No input may exceed V + 0.5V.
CC
Document #: 001-06501 Rev. **
Page 5 of 10
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CY7C1049BN
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
V
V
CC
DR
t
t
R
CDR
CE
Switching Waveforms
Read Cycle No. 1[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
t
PU
V
CC
50%
50%
SUPPLY
CURRENT
ISB
Notes:
12. Device is continuously selected. OE, CE = V .
IL
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
Document #: 001-06501 Rev. **
Page 6 of 10
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CY7C1049BN
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[15, 16]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[15, 16]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
t
PWE
SA
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 17
t
HZOE
Notes:
15. Data I/O is high impedance if OE = V
.
IH
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
17. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 001-06501 Rev. **
Page 7 of 10
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CY7C1049BN
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[16]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 17
DATA I/O
DATA VALID
t
t
LZWE
HZWE
Truth Table
CE
H
L
WE
X
OE
X
Inputs/Outputs
Mode
Power
High Z
Power-down
Read
Standby (ISB)
H
L
Data Out
Data In
High Z
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
L
X
Write
L
H
H
Selected, Output disabled
Ordering Information
Speed
Package
Diagram
Operating
Range
(ns)
Ordering Code
CY7C1049BN-12VC
CY7C1049BN-12VXC
CY7C1049BN-15VC
CY7C1049BN-15VXC
CY7C1049BN-15VI
CY7C1049BN-15VXI
CY7C1049BN-17VC
CY7C1049BNL-17VC
CY7C1049BN-17VXC
CY7C1049BN-20VC
CY7C1049BNL-20VC
CY7C1049BN-20VXC
CY7C1049BN-20VI
CY7C1049BN-20VXI
CY7C1049BNL-25VC
CY7C1049BN-25VI
CY7C1049BN-25VXI
Package Type
36-Lead (400-Mil) Molded SOJ
12
51-85090
51-85090
51-85090
51-85090
51-85090
51-85090
51-85090
51-85090
51-85090
51-85090
51-85090
51-85090
51-85090
51-85090
51-85090
51-85090
51-85090
Commercial
36-Lead (400-Mil) Molded SOJ (Pb-free)
36-Lead (400-Mil) Molded SOJ
15
36-Lead (400-Mil) Molded SOJ (Pb-free)
36-Lead (400-Mil) Molded SOJ
Industrial
36-Lead (400-Mil) Molded SOJ (Pb-free)
36-Lead (400-Mil) Molded SOJ
17
20
Commercial
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ (Pb-free)
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ (Pb-free)
36-Lead (400-Mil) Molded SOJ
Industrial
36-Lead (400-Mil) Molded SOJ (Pb-free)
36-Lead (400-Mil) Molded SOJ
25
Commercial
Industrial
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ (Pb-free)
Please contact local sales representative regarding availability of these parts.
Document #: 001-06501 Rev. **
Page 8 of 10
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CY7C1049BN
Package Diagram
36-Lead (400-Mil) Molded SOJ (51-85090)
51-85090-*B
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-06501 Rev. **
Page 9 of 10
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1049BN
Document History Page
Document Title: CY7C1049BN 512K x 8 Static RAM
Document Number: 001-06501
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
424111
See ECN
NXR
New Data Sheet
Document #: 001-06501 Rev. **
Page 10 of 10
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