CY7C1049BV33L-15VC [CYPRESS]
512K x 8 Static RAM; 512K ×8静态RAM
| 型号： | CY7C1049BV33L-15VC |
| 厂家： | 
CYPRESS |
| 描述： | 512K x 8 Static RAM |
| 文件： | 总10页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
049BV33
CY7C1049BV33
512K x 8 Static RAM
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. Writ-
ing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. Data on the eight I/O pins
(I/O0 through I/O7) is then written into the location specified on
the address pins (A0 through A18).
Features
• High speed
— tAA = 15 ns
• Low active power
— 504 mW (max.)
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
• Low CMOS standby power (Commercial L version)
— 1.8 mW (max.)
• 2.0V Data Retention (660 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
Functional Description[1]
The CY7C1049BV33 is available in a standard 400-mil-wide
36-pin SOJ and 44-pin TSOPII packages with center power
and ground (revolutionary) pinout.
The CY7C1049BV33 is a high-performance CMOS Static
RAM organized as 524,288 words by 8 bits. Easy memory
Logic Block Diagram
Pin Configuration
SOJ
TSOP II
Top View
Top View
A
A
36
35
34
33
1
2
3
4
5
6
7
8
9
44
NC
NC
NC
1
0
1
NC
NC
43
42
41
40
39
38
2
3
4
5
6
A
A
A
A
18
17
16
15
NC
A
0
A
2
A
A18
1
A
A
3
4
A
17
A
2
32
I/O0
A
16
A
3
INPUT BUFFER
CE
31
30
29
28
OE
I/O
A
15
A
7
4
A0
A1
A2
A3
A4
37
36
35
34
33
I/O1
I/O
CE
OE
I/O
8
0
1
7
I/O
9
0
I/O
I/O
V
7
6
I/O2
10
11
12
I/O
V
SS
I/O
1
CC
6
GND
CC
V
SS
27
26
25
GND
I/O
I/O3
10
11
12
13
A5
V
I/O3
I/O4
I/O5
CC
V
V
512K x 8
ARRAY
CC
A6
I/O
32
I/O
I/O
2
5
13
14
2
5
4
A7
A8
A9
I/O
I/O
A
31
30
29
28
I/O
4
3
WE 15
WE
24
23
22
21
20
19
14
A
14
A10
A
A
A
16
17
18
19
20
A
13
12
11
5
A
A
A
A
A
14
15
16
17
18
13
5
A
6
A
A
12
6
27
26
25
I/O6
I/O7
7
POWER
DOWN
COLUMN
DECODER
A
A
CE
A
7
11
10
8
9
A
NC
NC
NC
A
8
10
WE
NC 21
24
23
A
NC
9
22
NC
OE
Selection Guide
-12
-15
-17
17
-20
-25
Maximum Access Time (ns)
12
15
180
200
8
20
25
150
170
8
Maximum Operating Current (mA) Comm’l
Ind’l
200
220
8
170
180
8
160
170
8
Maximum CMOS Standby
Current (mA)
Com’l/Ind’l
Com’l
L
0.5
0.5
0.5
0.5
0.5
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05139 Rev. *A
Revised September 13, 2002
CY7C1049BV33
DC Input Voltage[2] ................................ –0.5V to VCC + 0.5V
Maximum Ratings
Current into Outputs (LOW) ........................................ 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Operating Range
Storage Temperature .................................–65°C to +150°C
Ambient
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[2].....–0.5V to +4.6V
DC Voltage Applied to Outputs[2]
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VCC
3.3V ± 0.3V
in High Z State .......................................–0.5V to VCC + 0.5V
DC Electrical Characteristics Over the Operating Range
-12
-15
-17
Parame-
ter
Description
Test Conditions
Min.
Max.
Min.
Max.
Min.
Max. Unit
VOH
Output HIGH Voltage VCC = Min.,
2.4
2.4
2.4
V
IOH = –4.0 mA
VOL
VIH
Output LOW Voltage VCC = Min.,
IOL = 8.0 mA
0.4
0.4
0.4
V
V
Input HIGH Voltage
2.2
VCC
+ 0.5
2.2
VCC
+ 0.5
2.2
VCC
+ 0.5
VIL
IIX
Input LOW Voltage[2]
–0.5
–1
0.8
+1
+1
–0.5
–1
0.8
+1
+1
–0.5
–1
0.8
+1
+1
V
Input Load Current
GND < VI < VCC
µA
µA
IOZ
Output Leakage
Current
GND < VOUT < VCC
Output Disabled
,
–1
–1
–1
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
Comm’l
Ind’l
200
220
30
180
200
30
170
180
30
mA
mA
mA
ISB1
Automatic CE
Max. VCC, CE > VIH
Power-Down Current VIN > VIH or
—TTL Inputs
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current CE > VCC – 0.3V,
—CMOS Inputs
Max. VCC
,
Com’l/Ind’l
8
8
8
mA
mA
Com’l
L
0.5
0.5
0.5
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
Note:
2. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
Document #: 38-05139 Rev. *A
Page 2 of 10
CY7C1049BV33
DC Electrical Characteristics Over the Operating Range (continued)
-20
-25
Parameter
VOH
Description
Test Conditions
VCC = Min.,
IOH = –4.0 mA
Min.
Max.
Min.
Max.
Unit
Output HIGH Voltage
2.4
2.4
V
VOL
Output LOW Voltage
VCC = Min.,
IOL = 8.0 mA
0.4
0.4
V
VIH
VIL
IIX
Input HIGH Voltage
Input LOW Voltage[2]
Input Load Current
2.2
–0.5
–1
VCC + 0.5
2.2
–0.5
–1
VCC + 0.5
V
V
0.8
+1
+1
0.8
+1
+1
GND < VI < VCC
µA
µA
IOZ
Output Leakage
Current
GND < VOUT < VCC
Output Disabled
,
–1
–1
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
Com’l
Ind’l
160
170
30
150
170
30
mA
mA
mA
ISB1
Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC
,
Com’l/Ind’l
8
8
mA
mA
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
Com’l
L
0.5
0.5
Capacitance[3]
Parameter
Description
Input Capacitance
I/O Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Max.
Unit
CIN
8
8
pF
pF
COUT
AC Test Loads and Waveforms
R1 317Ω
THÉ
VENIN EQUIVALENT
ALL INPUT PULSES
90%
3.3V
3.3V
167Ω
90%
1.73V
OUTPUT
OUTPUT
10%
10%
R2
351Ω
30 pF
GND
(b)
Fall time:
1 V/ns
RiseTime:1 V/ns
INCLUDING
JIG AND
SCOPE
(a)
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05139 Rev. *A
Page 3 of 10
CY7C1049BV33
AC Switching Characteristics[4] Over the Operating Range
-12
-15
-17
Parameter
Read Cycle
tpower
tRC
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
VCC(typical) to the First Access[5]
Read Cycle Time
1
1
1
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
15
17
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[6, 7]
CE LOW to Low Z[7]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
12
15
17
tOHA
3
3
3
tACE
12
6
15
7
17
8
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
0
3
0
0
3
0
0
3
0
6
6
7
7
8
8
tPD
12
15
17
Write Cycle[8, 9]
tWC
tSCE
tAW
tHA
Write Cycle Time
12
10
10
0
15
12
12
0
17
13
13
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tSA
0
0
0
tPWE
tSD
10
7
12
8
13
9
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[7]
tHD
0
0
0
tLZWE
3
3
3
tHZWE
WE LOW to High Z[6, 7]
6
7
8
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. T.power time has to be provided initially before a read/write operation
is started.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
Document #: 38-05139 Rev. *A
Page 4 of 10
CY7C1049BV33
AC Switching Characteristics[4] Over the Operating Range (continued)
-20
-25
Parameter
Read Cycle
tpower
tRC
Description
Min.
Max.
Min.
Max.
Unit
VCC(typical) to the First Access[6]
Read Cycle Time
1
1
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
25
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[6, 7]
CE LOW to Low Z[7]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
20
25
tOHA
3
3
tACE
20
8
25
10
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
0
3
0
0
3
0
8
8
10
10
25
tPD
20
Write Cycle[9]
tWC
Write Cycle Time
20
13
13
0
25
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tAW
tHA
tSA
0
0
tPWE
13
9
15
10
0
tSD
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[7]
tHD
0
tLZWE
tHZWE
3
3
WE LOW to High Z[6, 7]
8
10
Data Retention Characteristics Over the Operating Range (For L version only)
Parameter
Description
VCC for Data Retention
Data Retention Current
Conditions[10]
Min.
Max
Unit
V
VDR
2.0
ICCDR
VCC = VDR = 2.0V,
CE > VCC – 0.3V
VIN > VCC – 0.3V or VIN < 0.3V
330
µA
ns
[3]
tCDR
Chip Deselect to Data Retention
Time
0
[11]
tR
Operation Recovery Time
tRC
ns
Notes:
10. No input may exceed VCC + 0.5V
11. .tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 ns and slower speeds.
Document #: 38-05139 Rev. *A
Page 5 of 10
CY7C1049BV33
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
V
V
DR
CC
t
t
R
CDR
CE
Switching Waveforms
Read Cycle No. 1[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
I
t
PU
CC
V
CC
50%
50%
SUPPLY
CURRENT
I
SB
Notes:
12. Device is continuously selected. OE, CE = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05139 Rev. *A
Page 6 of 10
CY7C1049BV33
Switching Waveforms (continued)
Write Cycle No. 1(WE Controlled, OE HIGH During Write)[15, 16]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 17
t
HZOE
Write Cycle No. 2 (WE Controlled, OE LOW)[16]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 17
DATA I/O
DATA VALID
t
t
LZWE
HZWE
Truth Table
CE
H
OE
WE
X
I/O0 – I/O7
Mode
Power
X
L
High Z
Power-Down
Read
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
L
H
Data Out
Data In
High Z
)
L
X
H
L
Write
)
L
H
Selected, Outputs Disabled
)
Notes:
15. Data I/O is high-impedance if OE = VIH
.
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
17. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05139 Rev. *A
Page 7 of 10
CY7C1049BV33
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
36-Lead (400-Mil) Molded SOJ
44-Pin TSOP II Z44
12
CY7C1049BV33-12VC
CY7C1049BV33-12ZC
CY7C1049BV33L-12VC
CY7C1049BV33-12VI
CY7C1049BV33-15VC
CY7C1049BV33L-15VC
CY7C1049BV33-15ZC
CY7C1049BV33L-15ZC
CY7C1049BV33-15VI
CY7C1049BV33-15ZI
CY7C1049BV33-17VC
CY7C1049BV33L-17VC
CY7C1049BV33-17ZC
CY7C1049BV33L-17ZC
CY7C1049BV33-17VI
CY7C1049BV33L-17VI
CY7C1049BV33-17ZI
CY7C1049BV33-20VC
CY7C1049BV33L-20VC
CY7C1049BV33-20ZC
CY7C1049BV33L-20ZC
CY7C1049BV33-20VI
CY7C1049BV33-20ZI
CY7C1049BV33-25VC
CY7C1049BV33L-25VC
CY7C1049BV33-25ZC
CY7C1049BV33L-25ZC
CY7C1049BV33-25VI
V36
Z44
V36
V36
V36
V36
Z44
Z44
V36
Z44
V36
V36
Z44
Z44
V36
V36
Z44
V36
V36
Z44
Z44
V36
Z44
V36
V36
Z44
Z44
v36
Commercial
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
44-Pin TSOP II Z44
Industrial
15
17
Commercial
44-Pin TSOP II Z44
36-Lead (400-Mil) Molded SOJ
44-Pin TSOP II Z44
Industrial
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
44-Pin TSOP II Z44
Commercial
44-Pin TSOP II Z44
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
44-Pin TSOP II Z44
Industrial
20
25
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
44-Pin TSOP II Z44
Commercial
44-Pin TSOP II Z44
36-Lead (400-Mil) Molded SOJ
44-Pin TSOP II Z44
Industrial
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
44-Pin TSOP II Z44
Commercial
44-Pin TSOP II Z44
36-Lead (400-Mil) Molded SOJ
Industrial
Document #: 38-05139 Rev. *A
Page 8 of 10
CY7C1049BV33
Package Diagrams
36-Lead (400-Mil) Molded SOJ V36
51-85090-*B
44-Pin TSOP II Z44
51-85087-*A
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05139 Rev. *A
Page 9 of 10
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1049BV33
Document History Page
Document Title: CY7C1049BV33 512K x 8 Static RAM
Document Number: 38-05139
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
113091
116475
Description of Change
02/13/02
09/16/02
DSG
CEA
Change from Spec number: 38-00931 to 38-05139
Add applications foot note to data sheet, page 1
*A
Document #: 38-05139 Rev. *A
Page 10 of 10
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