CY7C1049CV33-15VC [CYPRESS]
512K x 8 Static RAM; 512K ×8静态RAM
| 型号： | CY7C1049CV33-15VC |
| 厂家： | 
CYPRESS |
| 描述： | 512K x 8 Static RAM |
| 文件： | 总9页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1049CV33
4-Mbit (512K x 8) Static RAM
Features
Functional Description[1]
• Temperature Ranges
The CY7C1049CV33 is a high-performance CMOS Static
RAM organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A18).
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
• High speed
— tAA = 10 ns
• Low active power
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
— 324 mW (max.)
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW, and WE LOW).
The CY7C1049CV33 is available in standard 400-mil-wide
36-pin SOJ package and 44-pin TSOP II package with center
power and ground (revolutionary) pinout.
Logic Block Diagram
Pin Configuration
SOJ
Top View
TSOP II
Top View
A0
A1
36
35
34
33
1
NC
A18
A17
A16
A15
44
1
NC
NC
NC
NC
NC
A18
A17
A16
A15
OE
I/O
2
3
4
43
42
41
40
39
38
2
3
4
5
6
A2
A
0
A
A3
A4
1
2
A
32
5
I/O
0
A3
A4
CE
I/O0
I/O1
VCC
INPUT BUFFER
31
30
29
28
6
OE
I/O7
I/O6
7
A
37
36
35
34
33
7
8
9
10
11
12
13
0
CE
I/O
8
I/O
I/O
1
A
1
9
0
7
A
2
10
11
12
13
I/O
I/O
GND
1
6
SS
2
A
3
V
V
CC
27
26
25
A
GND
I/O2
I/O3
WE
VCC
I/O5
I/O4
A14
A13
A12
4
V
V
SS
CC
A
6
5
I/O
I/O
I/O
I/O
3
4
5
512K x 8
ARRAY
32
I/O
I/O
2
5
A
31
30
29
28
I/O
4
A14
A13
I/O
14
15
16
17
18
19
20
21
22
3
A
7
24
23
22
21
20
WE
A5
A6
A
8
9
A
A5
A6
A7
A8
A9
14
15
16
17
18
A12
A
10
27
26
25
A
11
A
7
A11
A10
NC
A
A
8
10
6
7
POWER
DOWN
A
NC
NC
9
COLUMN
DECODER
CE
NC
NC
24
23
19
NC
I/O
WE
OE
Notes:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05006 Rev. *C
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised July 19, 2004
CY7C1049CV33
Selection Guide
-8[]
8
-10
10
90
100
-
-12
12
85
95
-
-15
15
80
90
95
10
15
Unit
ns
Maximum Access Time
Maximum Operating Current
Commercial
100
110
-
mA
mA
mA
mA
mA
Industrial
Automotive
Maximum CMOS Standby Current
Commercial / Industrial
Automotive
10
-
10
-
10
-
Shaded areas contain advance information.
Pin Definitions
36-SOJ
44 TSOP-II
Pin Name Pin Number Pin Number
I/O Type
Description
Address Inputs used to select one of the address locations.
A0-A18 1-5,14-18, 3-7,16-20,
20-24,32-35 26-30,38-41
Input
I/O0 - I/O7 7,8,11,12,25, 9,10,13,14,
Input/Output Bidirectional Data I/O lines. Used as input or output lines
26,29,30
depending on operation
31,32,35,36
NC[2]
19,36
1,2,21,22,23,
24,25,42,43,
No Connect No Connects. This pin is not connected to the die
44
15
WE
CE
OE
13
6
Input/Control Write Enable Input, active LOW. When selected LOW, a WRITE
is conducted. When selected HIGH, a READ is conducted.
8
Input/Control Chip Enable Input, active LOW. When LOW, selects the chip.
When HIGH, deselects the chip.
31
37
Input/Control Output Enable, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins are allowed to behave as outputs. When
deasserted HIGH, I/O pins are three-stated, and act as input data
pins.
V
SS, GND
10,28
9,27
12,34
11,33
Ground
Ground for the device. Should be connected to ground of the
system.
VCC
Power Supply Power Supply inputs to the device.
Notes:
2. NC pins are not connected on the die.
Document #: 38-05006 Rev. *C
Page 2 of 9
CY7C1049CV33
DC Voltage Applied to Outputs
Maximum Ratings
in High-Z State[3].................................... –0.5V to VCC + 0.5V
DC Input Voltage[3] ................................ –0.5V to VCC + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Operating Range
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[3] .... –0.5V to +4.6V
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VCC
3.3V ± 0.3V
–40°C to +85°C
–40°C to +125°C
Automotive
Electrical Characteristics Over the Operating Range
-8[]
-10
-12
-15
Parame-
ter
Description
Test Conditions
Min. Max. Min. Max. Min. Max. Min. Max. Unit
VOH
Output HIGH Voltage VCC = Min.; IOH = –4.0 mA
Output LOW Voltage VCC = Min.,; IOL = 8.0 mA
Input HIGH Voltage
2.4
2.4
2.4
2.4
V
V
V
VOL
VIH
0.4
2.0 VCC 2.0 VCC 2.0 VCC 2.0 VCC
+ 0.3 + 0.3 + 0.3 + 0.3
–0.3 0.8 –0.3 0.8 –0.3 0.8 –0.3 0.8
0.4
0.4
0.4
VIL
IIX
Input LOW Voltage[3]
V
Input Load Current
GND < VI < VCC Com’l / Ind’l –1
+1
–1
+1
–1
+1
–1
+1
µA
Automotive
-
-
-
-
-
-
–20 +20 µA
–1 +1 µA
IOZ
Output Leakage
Current
GND < VOUT
VCC
<
Com’l / Ind’l –1
+1
–1
+1
–1
+1
,
Output Disabled
Automotive
Com’l
-
-
100
110
-
-
-
90
100
-
-
-
85
95
-
–20 +20 µA
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
80
90
95
40
45
mA
mA
mA
mA
mA
Ind’l
Automotive
ISB1
Automatic CE
Max. VCC, CE > Com’l / Ind’l
Power-down Current VIH; VIN > VIH or
40
-
40
-
40
-
Automotive
—TTL Inputs
VIN < VIL, f = fMAX
ISB2
Automatic CE
Max. VCC
,
Com’l/Ind’l
Automotive
10
-
10
-
10
-
10
15
mA
mA
Power-down Current CE > VCC – 0.3V,
—CMOS Inputs IN > VCC – 0.3V,
or VIN < 0.3V, f = 0
V
Capacitance[4]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Max.
Unit
pF
CIN
Input Capacitance
I/O Capacitance
8
8
COUT
pF
Thermal Resistance[4]
36-pin SOJ
44-TSOP-II
(Non
Pb-Free)
(Non
36-pin SOJ
( Pb-Free)
44-TSOP-II
( Pb-Free)
Parameter
Description
Test Conditions
Pb-Free)
Unit
ΘJA
Thermal Resistance Test conditions follow
46.51
18.8
46.51
41.66
41.66
°C/W
(Junction to
Ambient)
standardtestmethods
and procedures for
measuring thermal
impedance, per EIA /
JESD51.
ΘJC
Thermal Resistance
(Junction to Case)
18.8
10.56
10.56
°C/W
Notes:
3. V (min.) = –2.0V and V (max) = V + 0.5V for pulse durations of less than 20 ns.
IL
IH
CC
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05006 Rev. *C
Page 3 of 9
CY7C1049CV33
AC Test Loads and Waveforms[5]
12-, 15-ns devices:
8-, 10-ns devices:
R 317Ω
Z = 50Ω
3.3V
OUTPUT
OUTPUT
30 pF
50Ω
30 pF*
R2
351Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
(a)
(b)
(d)
High-Z characteristics:
R 317Ω
ALL INPUT PULSES
3.3V
3.0V
90%
10%
90%
10%
OUTPUT
R2
351Ω
5 pF
GND
(c)
Fall Time: 1 V/ns
Rise Time: 1 V/ns
AC Switching Characteristics[6] Over the Operating Range
-8[]
-10
-12
-15
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max.
Unit
Read Cycle
[7]
tpower
VCC(typical) to the first access
Read Cycle Time
1
8
1
1
1
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
10
12
15
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z[8, 9]
CE LOW to Low-Z[9]
CE HIGH to High-Z[8, 9]
CE LOW to Power-up
CE HIGH to Power-down
8
10
12
15
3
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
3
3
3
8
4
10
5
12
6
15
7
0
3
0
0
3
0
0
3
0
0
3
0
4
4
8
5
5
6
6
7
7
tPD
10
12
15
Write Cycle[10, 11]
tWC
tSCE
tAW
tHA
Write Cycle Time
8
6
6
0
0
6
4
0
3
10
7
12
8
15
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
7
8
0
0
tSA
0
0
0
tPWE
tSD
7
8
10
7
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z[9]
5
6
tHD
0
0
0
tLZWE
3
3
3
tHZWE
WE LOW to High-Z[8, 9]
4
5
6
7
Notes:
5. AC characteristics (except High-Z) for all 8-ns and 10-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the
Thevenin load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
Document #: 38-05006 Rev. *C
Page 4 of 9
CY7C1049CV33
Switching Waveforms
Read Cycle No. 1[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
t
RC
CE
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
ISB
t
PU
VCC
SUPPLY
CURRENT
50%
50%
Notes:
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
7. t
8. t
gives the minimum amount of time that the power supply should be at stable, typical V values until the first memory access can be performed.
POWER
CC
, t
, and t
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
HZOE HZCE
HZWE
9. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
10. The internal Write time of the memory is defined by the overlap of CELOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these
signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
and t
.
SD
HZWE
12. Device is continuously selected. OE, CE = V .
IL
13. WE is HIGH for Read cycle.
Document #: 38-05006 Rev. *C
Page 5 of 9
CY7C1049CV33
Switching Waveforms (continued)
Write Cycle No. 1(WE Controlled, OE HIGH During Write)[15, 16]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
t
PWE
SA
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 17
t
HZOE
Write Cycle No. 2 (WE Controlled, OE LOW)[16]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 17
DATA I/O
DATA VALID
t
t
LZWE
HZWE
Notes:
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high-impedance if OE = V
.
IH
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
17. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05006 Rev. *C
Page 6 of 9
CY7C1049CV33
Truth Table
CE
H
L
OE
WE
X
I/O0–I/O7
Mode
Power
X
L
High-Z
Power-down
Read
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
H
Data Out
Data In
High-Z
)
L
X
H
L
Write
)
L
H
Selected, Outputs Disabled
)
Ordering Information
Speed
Package
Operating
Range
(ns)
Ordering Code
CY7C1049CV33-10VC
CY7C1049CV33-10ZC
CY7C1049CV33-10VI
CY7C1049CV33-10ZI
CY7C1049CV33-12VC
CY7C1049CV33-12ZC
CY7C1049CV33-12VI
CY7C1049CV33-12ZI
CY7C1049CV33-15VXC
CY7C1049CV33-15VC
CY7C1049CV33-15ZXC
CY7C1049CV33-15ZC
CY7C1049CV33-15VI
CY7C1049CV33-15ZI
CY7C1049CV33-15VE
CY7C1049CV33-15ZE
Name
V36
Z44
V36
Z44
V36
Z44
V36
Z44
V36
V36
Z44
Z44
V36
Z44
V36
Z44
Package Type
36-lead (400-Mil) Molded SOJ
44-pin TSOP II
10
Commercial
36-lead (400-Mil) Molded SOJ
44-pin TSOP II
Industrial
12
15
36-lead (400-Mil) Molded SOJ
44-pin TSOP II
Commercial
Industrial
36-lead (400-Mil) Molded SOJ
44-pin TSOP II
36-lead (400-Mil) Molded SOJ (Pb-Free)
36-lead (400-Mil) Molded SOJ
44-pin TSOP II (Pb-Free)
44-pin TSOP II
Commercial
36-lead (400-Mil) Molded SOJ
44-pin TSOP II
Industrial
36-lead (400-Mil) Molded SOJ
44-pin TSOP II
Automotive
Document #: 38-05006 Rev. *C
Page 7 of 9
CY7C1049CV33
Package Diagrams
36-Lead (400-Mil) Molded SOJ V36
51-85090-B
44-pin TSOP II Z44
51-85087-*A
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05006 Rev. *C
Page 8 of 9
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1049CV33
Document History Page
Document Title: CY7C1049CV33 4-Mbit (512K x 8) Static RAM
Document Number: 38-05006
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
112569
114091
116479
262949
Description of Change
03/06/02
04/25/02
09/16/02
See ECN
HGK
DFP
CEA
RKF
New Data Sheet
*A
Changed Tpower unit from ns to µs
*B
Add applications foot note to data sheet, page 1.
*C
Added Automotive Specs to Datasheet
Added ΘJA and ΘJC values on Page #3.
Document #: 38-05006 Rev. *C
Page 9 of 9
相关型号：
CY7C1049CV33-15VXCT
Standard SRAM, 512KX8, 15ns, CMOS, PDSO36, 0.400 INCH, LEAD FREE, SOJ-36
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CY7C1049CV33-15VXIT
Standard SRAM, 512KX8, 15ns, CMOS, PDSO36, 0.400 INCH, LEAD FREE, SOJ-36
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