CY7C1049DV33_07 [CYPRESS]
4-Mbit (512K x 8) Static RAM; 4兆位（ 512K ×8）静态RAM
| 型号： | CY7C1049DV33_07 |
| 厂家： | 
CYPRESS |
| 描述： | 4-Mbit (512K x 8) Static RAM |
| 文件： | 总10页 (文件大小：863K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1049DV33
4-Mbit (512K x 8) Static RAM
Features
Functional Description
■ Pin and function compatible with CY7C1049CV33
The CY7C1049DV33 is a high performance CMOS Static RAM
organized as 512K words by 8-bits. Easy memory expansion is
provided by an Active LOW Chip Enable (CE), an Active LOW
Output Enable (OE), and tri-state drivers. You can write to the
device by taking Chip Enable (CE) and Write Enable (WE) inputs
LOW. Data on the eight IO pins (IO0 through IO7) is then written
into the location specified on the address pins (A0 through A18).
■ High speed
❐ tAA = 10 ns
■ Low active power
❐ ICC = 90 mA @ 10 ns (Industrial)
■ Low CMOS standby power
❐ ISB2 = 10 mA
You can read from the device by taking Chip Enable (CE) and
Output Enable (OE) LOW while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins appear on the IO pins.
■ 2.0V data retention
■ Automatic power down when deselected
■ TTL compatible inputs and outputs
■ Easy memory expansion with CE and OE features
The eight input or output pins (IO0 through IO7) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), or during a write operation
(CE LOW, and WE LOW).
■ Available in Pb-free 36-pin (400 Mil) Molded SOJ and 44-pin
TSOP II packages
The CY7C1049DV33 is available in standard 400 Mil wide 36
-pin SOJ package and 44-pin TSOP II package with center
power and ground (revolutionary) pinout.
Refer to the Cypress application note AN1064, SRAM System
Guidelines for best practice recommendations.
Logic Block Diagram
IO
0
INPUT BUFFER
A
0
IO
1
A
1
A
2
IO
2
A
3
A
4
512K x 8
ARRAY
IO
3
A
A
A
A
A
A
5
6
IO
4
7
8
IO
5
9
10
IO
6
CE
IO
POWER
DOWN
7
COLUMN DECODER
WE
OE
Cypress Semiconductor Corporation
Document Number: 38-05475 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 23, 2007
CY7C1049DV33
Pin Configuration
44-Pin TSOP II
Top View
36-Pin SOJ
Top View
1
2
3
4
5
6
7
8
NC
NC
NC
44
43
42
41
40
39
38
37
NC
NC
A
A
A
A
A
1
NC
A
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
0
1
A
0
2
3
4
5
6
7
8
9
18
A
A
1
18
A
17
2
3
4
A
2
A
17
A
16
A
16
A
3
A
15
OE
A
4
CE
A
15
OE
CE
IO
IO
7
0
IO
0
IO
7
9
36
35
34
33
32
31
30
29
28
27
26
25
24
23
IO
IO
6
GND
1
IO
1
IO
10
11
12
13
14
15
16
17
18
19
20
21
22
6
SS
V
CC
V
V
CC
V
CC
IO
GND 10
V
SS
V
CC
IO
IO
IO
2
3
11
12
13
14
15
16
17
18
5
IO
IO
2
3
5
IO
4
14
IO
4
14
A
WE
A
A
WE
A
A
5
13
A
13
5
A
A
12
6
A
A
6
12
A
7
A
11
A
A
11
7
A
8
A
10
NC
A
A
10
8
A
9
A
NC
NC
NC
9
NC
NC
Selection Guide
-10 (Industrial)
-12 (Automotive)[1]
Unit
ns
Maximum Access Time
10
90
10
12
95
15
Maximum Operating Current
mA
mA
Maximum CMOS Standby Current
Note
1. Automotive product information is preliminary.
Document Number: 38-05475 Rev. *D
Page 2 of 10
CY7C1049DV33
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage............................................>2001V
(MIL-STD-883, Method 3015)
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Latch up Current......................................................>200 mA
Operating Range
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage on VCC to Relative GND[2].....–0.3V to +4.6V
Ambient
Range
Industrial
Temperature
VCC
Speed
10 ns
12 ns
–40°C to +85°C
3.3V ± 0.3V
DC Voltage Applied to Outputs
in High Z State[2]....................................–0.3V to VCC + 0.3V
Automotive
–40°C to +125°C 3.3V ± 0.3V
DC Input Voltage[2] ................................–0.3V to VCC + 0.3V
Electrical Characteristics Over the Operating Range
-10 (Industrial)
-12 (Automotive)
Parameter
Description
Test Conditions
VCC = Min,
Min
Max
Min
Max
Unit
VOH
Output HIGH Voltage
2.4
2.4
V
IOH = –4.0 mA
VOL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[2]
Input Leakage Current
VCC = Min, IOL = 8.0 mA
0.4
VCC + 0.3
0.8
0.4
VCC + 0.3
0.8
V
V
[2]
VIH
2.0
–0.3
–1
2.0
–0.3
–1
[2]
VIL
V
IIX
GND < VI < VCC
+1
+1
µA
µA
IOZ
Output Leakage
Current
GND < VOUT < VCC
,
–1
+1
–1
+1
Output Disabled
ICC
VCC Operating
Supply Current
VCC = Max, f = fMAX = 1/tRC 100 MHz
90
80
70
60
20
-
mA
mA
mA
mA
mA
83 MHz
95
85
75
25
66 MHz
40 MHz
ISB1
Automatic CE
Max VCC, CE > VIH;
Power down Current
—TTL Inputs
V
IN > VIH or
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power down Current
—CMOS Inputs
Max VCC, CE > VCC – 0.3V,
IN > VCC – 0.3V,
or VIN < 0.3V, f = 0
10
15
mA
V
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
CIN
Description
Input Capacitance
IO Capacitance
Test Conditions
Max
Unit
TA = 25°C, f = 1 MHz, VCC = 3.3V
8
8
pF
pF
COUT
Note
2. V (min.) = –2.0V and V (max) = V + 2V for pulse durations of less than 20 ns.
IL
IH
CC
Document Number: 38-05475 Rev. *D
Page 3 of 10
CY7C1049DV33
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
SOJ
Package
TSOP II
Package
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch,
two layer printed circuit board
57.91
50.66
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
36.73
17.17
°C/W
AC Test Loads and Waveforms
Figure 1. AC Test Loads and Waveforms [4]
10 ns device
ALL INPUT PULSES
Z = 50Ω
3.0V
90%
10%
90%
10%
OUTPUT
50Ω
30 pF*
GND
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
(b)
Fall Time: 1 V/ns
Rise Time: 1 V/ns
(a)
High Z characteristics:
R 317Ω
3.3V
OUTPUT
R2
351Ω
5 pF
(c)
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
Description
VCC for Data Retention
Data Retention Current
Conditions [5]
Min Max Unit
2.0
V
ICCDR
VCC = VDR = 2.0V, CE > VCC – 0.3V
VIN > VCC – 0.3V or VIN < 0.3V
Ind’l
10
15
mA
mA
ns
Auto
[3]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
[6]
tR
tRC
ns
Figure 2. Data Retention Waveform
DATA RETENTION MODE
3.0V
3.0V
V
DR
> 2V
V
CC
t
t
R
CDR
CE
Note
3. Tested initially and after any design or process changes that may affect these parameters.
4. AC characteristics (except High Z) are tested using the load conditions shown in Figure 1. High Z characteristics are tested for all speeds using the test load shown in
Figure (c).
5. No input may exceed V + 0.3V.
CC
6. Full device operation requires linear V ramp from V to V
> 50 µs or stable at V
> 50 µs.
CC(min.)
CC
DR
CC(min.)
Document Number: 38-05475 Rev. *D
Page 4 of 10
CY7C1049DV33
AC Switching Characteristics
Over the Operating Range [7]
-10 (Industrial)
-12 (Automotive)
Parameter
Description
Min
Max
Min
Max
Unit
Read Cycle
[8]
tpower
VCC(typical) to the first access
Read Cycle Time
100
10
100
12
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[9, 10]
CE LOW to Low Z[10]
CE HIGH to High-Z[9, 10]
CE LOW to Power up
CE HIGH to Power down
10
12
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
3
3
10
5
12
6
0
3
0
0
3
0
5
5
6
6
tPD
10
12
Write Cycle[11, 12]
tWC
Write Cycle Time
10
12
ns
tSCE
tAW
tHA
CE LOW to Write End
7
7
0
0
8
8
0
0
ns
ns
ns
ns
Address Set up to Write End
Address Hold from Write End
Address Set up to Write Start
tSA
tPWE
tSD
WE Pulse Width
7
5
0
8
6
0
ns
ns
ns
Data Set up to Write End
tHD
Data Hold from Write End
tLZWE
tHZWE
WE HIGH to Low Z[10]
WE LOW to High Z[9, 10]
3
3
ns
ns
5
6
Notes
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I /I
OL OH
and 30 pF load capacitance.
8.
9.
t
gives the minimum amount of time that the power supply must be at stable, typical V values until the first memory access is performed.
P
O
W
E
R
C
C
t
, t
, and t
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured when the outputs enter a high impedance state.
HZOE HZCE
HZWE
10. At any temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
11. The internal write time of the memory is defined by the overlap of CELOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals
can terminate the write. The input data set up and hold timing must be referred to the leading edge of the signal that terminates the write.
12. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of t
and t
.
SD
HZWE
Document Number: 38-05475 Rev. *D
Page 5 of 10
CY7C1049DV33
Switching Waveforms
Figure 3. Read Cycle No. 1[13, 14]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 4. Read Cycle No. 2 (OE Controlled)[14, 15]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
t
PU
VCC
SUPPLY
CURRENT
50%
50%
ISB
Figure 5. Write Cycle No. 1 (WE Controlled, OE HIGH During Write)[16, 17]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 17
t
HZOE
Notes
13. Device is continuously selected. OE, CE = V .
IL
14. WE is HIGH for read cycle.
15. Address valid prior to or coincident with CE transition LOW.
16. Data IO is high impedance if OE = V
.
IH
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 38-05475 Rev. *D
Page 6 of 10
CY7C1049DV33
Switching Waveforms (continued)
Figure 6. Write Cycle No. 2 (WE Controlled, OE LOW)[17]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 18
DATA I/O
DATA VALID
t
t
LZWE
HZWE
Figure 7. Write Cycle No. 3 (CE Controlled)[16, 17]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Note
18. During this period the IOs are in the output state and input signals must not be applied.
Document Number: 38-05475 Rev. *D
Page 7 of 10
CY7C1049DV33
Truth Table
IO0–IO7
High Z
Mode
Power
CE
OE
WE
H
X
X
Power down
Read
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
L
L
L
L
X
H
H
L
Data Out
Data In
High Z
)
Write
)
H
Selected, Outputs Disabled
)
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C1049DV33-10VXI
CY7C1049DV33-10ZSXI
CY7C1049DV33-12VXE
CY7C1049DV33-12ZSXE
Package Type
10
51-85090 36-pin (400-Mil) Molded SOJ (Pb-free)
51-85087 44-pin TSOP II (Pb-free)
Industrial
12
51-85090 36-pin (400-Mil) Molded SOJ (Pb-free)
51-85087 44-pin TSOP II (Pb-free)
Automotive
Contact your local Cypress sales representative for availability of these parts.
Package Diagrams
Figure 8. 36-Pin (400-Mil) Molded SOJ (51-85090)
51-85090-*C
Document Number: 38-05475 Rev. *D
Page 8 of 10
CY7C1049DV33
Package Diagrams (continued)
Figure 9. 44-Pin Thin Small Outline Package Type II (51-85087)
51-85087-*A
Document Number: 38-05475 Rev. *D
Page 9 of 10
CY7C1049DV33
Document History Page
Document Title: CY7C1049DV33, 4-Mbit (512K x 8) Static RAM
Document Number: 38-05475
Issue
Date
Orig. of
Change
REV. ECN NO.
Description of Change
Advance Datasheet for C9 IPP
**
201560 See ECN
233729 See ECN
SWI
SYT
*A
1.AC, DC parameters are modified as per EROS (Specification # 01-2165)
2.Pb-free offering in the Ordering Information Table
*B
351096 See ECN
PCI
Changed from Advance to Preliminary
Removed 20 ns Speed bin
Corrected DC voltage (min) value in maximum ratings section from - 0.5 to
- 0.3V
Redefined ICC values for Com’l and Ind’l temperature ranges
I
CC (Com’l): Changed from 100, 80, and 67 mA to 90, 80 and, 75 mA for 8, 10, and
12ns speed bins respectively
ICC (Ind’l): Changed from 80 and 67 mA to 90 and 85 mA for 10 and 12ns speed bins
respectively
Added VIH(max) specification in Note# 2
Changed reference voltage level for measurement of High Z parameters from ±500 mV
to ±200 mV
Added Data Retention Characteristics, Waveform, and footnotes 11 and 12
Changed Package Diagram name from 44-pin TSOP II Z44 to 44-pin TSOP II ZS44
Changed part names from Z to ZS in the Ordering Information Table
Added 8 ns parts in the Ordering Information Table
Added Pb-free Ordering Information
Shaded Ordering Information Table
*C
*D
446328 See ECN
NXR
Converted from Preliminary to Final
Removed -8 speed bin
Removed Commercial Operating Range product information
Added Automotive Operating Range product information
Updated Thermal Resistance table
Updated footnote #8 on High Z parameter measurement
Replaced Package Name column with Package Diagram in the Ordering Information
table
1274726 See ECN VKN/AESA Corrected typo in the 44-Pin TSOP II pinout
© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05475 Rev. *D
Revised July 23, 2007
Page 10 of 10
All products and company names mentioned in this document may be the trademarks of their respective holders.
相关型号：
CY7C1049G18-15ZSXIT
4-Mbit (512K words à 8 bit) Static RAM with Error-Correcting Code (ECC)
CYPRESS
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