CY7C1049V33-12VC [CYPRESS]
Standard SRAM, 512KX8, 12ns, CMOS, PDSO36, 0.400 INCH, PLASTIC, SOJ-36;
| 型号： | CY7C1049V33-12VC |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 512KX8, 12ns, CMOS, PDSO36, 0.400 INCH, PLASTIC, SOJ-36 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总9页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
049V33
CY7C1049V33
512K x 8 Static RAM
sion is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE), and three-state drivers. Writing to
the device is accomplished by taking Chip Enable (CE) and
Write Enable (WE) inputs LOW. Data on the eight I/O pins
(I/O0 through I/O7) is then written into the location specified on
the address pins (A0 through A18).
Features
• High speed
— tAA = 15 ns
• Low active power
— 504 mW (max.)
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
• Low CMOS standby power (Commercial L version)
— 1.8 mW (max.)
• 2.0V Data Retention (660 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
Functional Description
The CY7C1049V33 is available in a standard 400-mil-wide
36-pin SOJ package with center power and ground (revolu-
tionary) pinout.
The CY7C1049V33 is a high-performance CMOS Static RAM
organized as 524,288 words by 8 bits. Easy memory expan-
Logic Block Diagram
Pin Configuration
SOJ
Top View
A
36
35
34
33
1
NC
0
A
2
3
1
A
A
A
A
18
17
16
15
A
2
4
A
A
3
4
32
31
30
29
28
5
I/O
0
CE
6
OE
I/O
INPUT BUFFER
I/O
7
0
1
7
A
0
I/O
I/O
1
I/O
I/O
V
8
9
6
A
1
A
GND
CC
2
2
A
27
26
25
3
4
GND
10
11
12
13
V
CC
A
I/O
I/O
A
I/O
2
5
4
A
6
5
I/O
I/O
I/O
3
4
5
512K x 8
ARRAY
I/O3
A
A
WE
24
23
22
7
14
13
12
A
8
A
A
A
A
14
15
16
17
18
5
9
A
6
A
10
21
20
19
A
A
A
7
11
10
A
8
I/O
6
7
POWER
DOWN
A
COLUMN
DECODER
NC
9
CE
I/O
WE
1049V33–2
1049V33–1
OE
Selection Guide
1049V33-12
1049V33-15
1049V33-17
1049V33-20
1049V33-25
Maximum Access Time (ns)
12
150
8
15
140
8
17
130
8
20
120
8
25
110
8
Maximum Operating Current (mA)
Maximum CMOS Standby
Current (mA)
Com’l/Ind’l
Com’l
L
0.5
0.5
0.5
0.5
0.5
Shaded areas contain preliminary information.
Cypress Semiconductor Corporation
Document #: 38-05067 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised July 9, 2001
CY7C1049V33
DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V
Maximum Ratings
Current into Outputs (LOW) ........................................ 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Operating Range
Storage Temperature .................................–65°C to +150°C
Ambient
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V
Range
Commercial
Industrial
Temperature[2]
0°C to +70°C
VCC
3.3V ± 0.3V
–40°C to +85°C
DC Voltage Applied to Outputs
in High Z State[1]....................................–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range
Parame-
ter
Description
Test Conditions
7C1049V33-12 7C1049V33-15 7C1049V33-17
Min.
Max.
Min.
Max.
Min.
Max. Unit
VOH
Output HIGH Voltage VCC = Min.,
2.4
2.4
2.4
V
IOH = –4.0 mA
VOL
VIH
Output LOW Voltage VCC = Min.,
IOL = 8.0 mA
0.4
0.4
0.4
V
V
Input HIGH Voltage
2.2
VCC
+ 0.5
2.2
VCC
+ 0.5
2.2
VCC
+ 0.5
VIL
IIX
Input LOW Voltage[1]
–0.5
–1
0.8
+1
+1
–0.5
–1
0.8
+1
+1
–0.5
–1
0.8
+1
+1
V
Input Load Current
GND < VI < VCC
µA
µA
IOZ
Output Leakage
Current
GND < VOUT < VCC
Output Disabled
,
–1
–1
–1
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
150
30
140
30
130
30
mA
mA
ISB1
Automatic CE
Max. VCC, CE > VIH
Power-Down Current VIN > VIH or
—TTL Inputs
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current CE > VCC – 0.3V,
—CMOS Inputs
Max. VCC
,
Com’l/Ind’l
Com’l
8
8
8
mA
mA
L
0.5
0.5
0.5
VIN > VCC – 0.3V,
or VIN < 0.3V, f=0
Shaded areas contain preliminary information.
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. A is the “Instant On” case temperature.
T
Document #: 38-05067 Rev. **
Page 2 of 9
CY7C1049V33
Electrical Characteristics Over the Operating Range (continued)
7C1049V33-20
7C1049V33-25
Parameter
VOH
Description
Test Conditions
VCC = Min.,
IOH = –4.0 mA
Min.
Max.
Min.
Max.
Unit
Output HIGH Voltage
2.4
2.4
V
VOL
Output LOW Voltage
VCC = Min.,
IOL = 8.0 mA
0.4
0.4
V
VIH
VIL
IIX
Input HIGH Voltage
Input LOW Voltage[1]
Input Load Current
2.2
–0.5
–1
VCC + 0.5
2.2
–0.5
–1
VCC + 0.5
V
V
0.8
+1
+1
0.8
+1
+1
GND < VI < VCC
µA
µA
IOZ
Output Leakage
Current
GND < VOUT < VCC
Output Disabled
,
–1
–1
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
120
30
110
30
mA
mA
ISB1
Automatic CE
Power-Down Current
Max. VCC, CE > VIH
VIN > VIH or
—TTL Inputs
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC
,
Com’l/Ind’l
Com’l
8
8
mA
mA
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f=0
L
0.5
0.5
Capacitance[3]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Max.
Unit
CIN
Input Capacitance
I/O Capacitance
8
8
pF
pF
COUT
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
ALL INPUT PULSES
90%
R1 317Ω
THÉ
VENIN EQUIVALENT
3.3V
3.3V
GND
167Ω
90%
10%
1.73V
OUTPUT
OUTPUT
10%
R2
351Ω
30 pF
(b)
≤ 3 ns
≤ 3 ns
INCLUDING
JIG AND
SCOPE
(a)
1049V33–4
1049V33–3
Document #: 38-05067 Rev. **
Page 3 of 9
CY7C1049V33
Switching Characteristics[5] Over the Operating Range
7C1049V33-12
7C1049V33-15
7C1049V33-17
Parameter
READ CYCLE
tRC
Description
Min.
12
Max.
Min.
15
3
Max.
Min.
17
3
Max.
Unit
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[5, 6]
CE LOW to Low Z[6]
12
15
17
tOHA
3
tACE
12
6
15
7
17
8
tDOE
tLZOE
tHZOE
tLZCE
0
3
0
0
3
0
0
3
0
6
6
7
7
8
8
tHZCE
tPU
CE HIGH to High Z[5, 6]
CE LOW to Power-Up
CE HIGH to Power-Down
tPD
12
15
17
WRITE CYCLE[7, 8]
tWC
Write Cycle Time
12
10
10
0
15
12
12
0
17
13
13
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tHA
tSA
0
0
0
tPWE
tSD
10
7
12
8
13
9
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[6]
tHD
0
0
0
tLZWE
tHZWE
3
3
3
WE LOW to High Z[5, 6]
6
7
8
Shaded areas contain preliminary information.
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5.
tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
Document #: 38-05067 Rev. **
Page 4 of 9
CY7C1049V33
Switching Characteristics[5] Over the Operating Range (continued)
7C1049V33-20
7C1049V33-25
Parameter
READ CYCLE
tRC
Description
Min.
20
3
Max.
Min.
Max.
Unit
Read Cycle Time
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
20
25
tOHA
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[5, 6]
CE LOW to Low Z[6]
CE HIGH to High Z[5, 6]
CE LOW to Power-Up
CE HIGH to Power-Down
5
tACE
20
8
25
10
tDOE
tLZOE
tHZOE
tLZCE
0
3
0
0
5
0
8
8
10
10
25
tHZCE
tPU
tPD
20
WRITE CYCLE[7]
tWC
tSCE
tAW
Write Cycle Time
20
13
13
0
25
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tHA
tSA
0
0
tPWE
tSD
13
9
15
10
0
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[6]
tHD
0
tLZWE
tHZWE
3
5
WE LOW to High Z[5, 6]
8
10
Data Retention Characteristics Over the Operating Range (For L version only)
Parameter
Description
VCC for Data Retention
Data Retention Current
Conditions[10]
Min.
Max
Unit
V
VDR
2.0
ICCDR
VCC = VDR = 2.0V,
CE > VCC – 0.3V
VIN > VCC – 0.3V or VIN < 0.3V
330
µA
ns
[3]
tCDR
Chip Deselect to Data Retention
Time
0
[9]
tR
Operation Recovery Time
tRC
ns
Notes:
9. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 ns and slower speeds.
10. No input may exceed VCC + 0.5V.
Document #: 38-05067 Rev. **
Page 5 of 9
CY7C1049V33
Data Retention Waveform
DATA RETENTION MODE
> 2V
3.0V
3.0V
V
V
DR
CC
t
t
R
CDR
CE
1049V33-5
Switching Waveforms
Read Cycle No. 1[11, 12]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
1049V33–6
Read Cycle No. 2 (OE Controlled)[12, 13]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
I
t
PU
CC
V
CC
50%
50%
SUPPLY
CURRENT
I
SB
1049V33–7
Notes:
11. Device is continuously selected. OE, CE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05067 Rev. **
Page 6 of 9
CY7C1049V33
Switching Waveforms (continued)
Write Cycle No. 1(WE Controlled, OE HIGH During Write)[14, 15]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 16
t
HZOE
1049V33–8
Write Cycle No. 2 (WE Controlled, OE LOW)[15]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 16
DATA I/O
DATA VALID
t
t
LZWE
HZWE
1049V33-9
Notes:
14. Data I/O is high impedance if OE = VIH
.
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
16. During this period the I/Os are in the output state and input signals should not be applied.
Truth Table
CE
H
L
OE
X
WE
X
I/O0 – I/O7
High Z
Mode
Power
Power-Down
Read
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
L
H
Data Out
Data In
High Z
)
L
X
L
Write
)
L
H
H
Selected, Outputs Disabled
)
Document #: 38-05067 Rev. **
Page 7 of 9
CY7C1049V33
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
36-Lead (400-Mil) Molded SOJ
12
CY7C1049V33-12VC
CY7C1049V33L-12VC
CY7C1049V33-15VC
CY7C1049V33L-15VC
CY7C1049V33-17VC
CY7C1049V33L-17VC
CY7C1049V33-20VC
CY7C1049V33L-20VC
CY7C1049V33-20VI
CY7C1049V33-25VC
CY7C1049V33-25VI
V36
V36
V36
V36
V36
V36
V36
V36
V36
V36
v36
Commercial
15
17
20
Industrial
Commercial
Industrial
25
Package Diagram
36-Lead (400-Mil) Molded SOJ V36
51-85090
Document #: 38-05067 Rev. **
Page 8 of 9
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1049V33
Document Title: 512K x 8 Static RAM
Document Number: 38-05067
Issue
ECN NO. Date
Orig. of
Change
REV.
Description of Change
**
107260
07/11/01
SZV
Change from Spec number: 38-00643 to 38-05067
Document #: 38-05067 Rev. **
Page 9 of 9
相关型号：
CY7C1051DV33-10BAXIT
Standard SRAM, 512KX16, 10ns, CMOS, PBGA48, 6 X 8 MM, 1.20 MM HEIGHT, LEAD FREE, MO-207, FBGA-48
CYPRESS
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