CY7C1061AV25 [CYPRESS]
1M x 16 Static RAM; 1M ×16静态RAM
| 型号： | CY7C1061AV25 |
| 厂家： | 
CYPRESS |
| 描述： | 1M x 16 Static RAM |
| 文件： | 总11页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
CY7C1061AV25
1M x 16 Static RAM
specified on the address pins (A0 through A19). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A19).
Features
• High speed
— tAA = 8, 10, 12 ns
Reading from the device is accomplished by enabling the chip
by taking CE1 LOW and CE2 HIGH while forcing the Output
Enable (OE) LOW and the Write Enable (WE) HIGH. If Byte
Low Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O0 to I/O7. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O8 to I/O15. See the truth table at the back of this data
sheet for a complete description of Read and Write modes.
• Low active power
— 1080 mW (max.)
• Operating voltages of 2.5 ± 0.2V
• 1.5V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1 and CE2 features
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE1
HIGH / CE2 LOW), the outputs are disabled (OE HIGH), the
BHE and BLE are disabled (BHE, BLE HIGH), or during a
Write operation (CE1 LOW, CE2 HIGH, and WE LOW).
Functional Description
The CY7C1061AV25 is a high-performance CMOS Static
RAM organized as 1,048,576 words by 16 bits.
Writing to the device is accomplished by enabling the chip
(CE1 LOW and CE2 HIGH) while forcing the Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7), is written into the location
The CY7C1061AV25 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout, and a
48-ball fine-pitch ball grid array (FBGA) package.
Pin Configuration
Logic Block Diagram
TSOP II (Top View)
1
54 I/O
11
INPUT BUFFER
I/O
V
12
CC
53
52
51
50
V
I/O
I/O
2
3
4
5
6
SS
I/O
13
14
10
A
0
A
1
I/O
V
9
V
CC
SS
A
2
I/O
49 I/O
15
8
A
3
4
I/O –I/O
1M x 16
ARRAY
0
7
A
A
3
A
A
1
A
48
47
A
5
A
6
7
A
4
8
A
5
6
4096 x 4096
I/O –I/O
8
15
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
A
7
A
9
2
A
10
11
12
13
A
8
7
A
A
9
8
A
0
NC
9
BHE
CE
OE
1
V
V
CC
14
15
16
17
18
19
20
21
22
23
SS
WE
DNU (Do Not Use)
BLE
COLUMN
DECODER
CE
2
A
19
A
10
A
18
A
11
A
12
A
13
A
A
A
17
16
15
BHE
WE
A
14
I/O
V
I/O
V
0
7
CE
2
1
CC
SS
CE
24
25
26
27
I/O
I/O
OE
BLE
6
5
1
2
I/O
I/O
V
V
SS
CC
I/O
I/O
3
4
Selection Guide
-8
8
-10
10
-12
12
Unit
ns
Maximum Access Time
Maximum Operating Current
Commercial
Industrial
300
300
50
275
275
50
260
260
50
mA
Maximum CMOS Standby Current
Commercial/Industrial
mA
Cypress Semiconductor Corporation
Document #: 38-05331 Rev. **
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised January 27, 2003
PRELIMINARY
CY7C1061AV25
Pin Configurations
48-ball FBGA
(Top View)
1
2
4
3
5
6
A
A
A
2
CE
OE
BLE
0
1
2
A
B
C
I/O
8
A
A
4
BHE
CE
I/O
I/O
0
3
1
I/O
10
A
A
6
I/O
9
I/O
2
5
1
I/O
I/O
A
I/O
11
V
CC
V
A
D
E
F
3
SS
7
17
A
V
CC
NC
V
SS
I/O
12
16
4
I/O
A
A
I/O
5
I/O
13
I/O
14
6
14
15
A
I/O
7
A
G
H
I/O
15
DNU
WE
13
12
A
A
9
A
A
19
A
A
8
10
11
18
Document #: 38-05331 Rev. **
Page 2 of 11
PRELIMINARY
CY7C1061AV25
DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Current into Outputs (LOW)......................................... 20 mA
Operating Range
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +3.6V
Ambient
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VCC
2.5V ± 0.2V
DC Voltage Applied to Outputs
in High-Z State[1] ....................................–0.5V to VCC + 0.5V
DC Electrical Characteristics Over the Operating Range
-8
-10
-12
Parameter
Description
Test Conditions
Min. Max. Min. Max. Min. Max. Unit
VOH
Output HIGH Voltage VCC = Min.,
2.0
2.0
2.0
V
V
V
IOH = –1.0 mA
VOL
VIH
Output LOW Voltage
Input HIGH Voltage
VCC = Min.,
IOL = 1.0 mA
0.4
0.4
0.4
2.0 VCC 2.0 VCC 2.0 VCC
+ 0.3 + 0.3 + 0.3
VIL
IIX
Input LOW Voltage[1]
Input Load Current
–0.3 0.8 –0.3 0.8 –0.3 0.8
V
GND < VI < VCC
–1
–1
+1
+1
–1
–1
+1
+1
–1
–1
+1
+1
µA
µA
IOZ
ICC
Output Leakage Current GND < VOUT < VCC, Output Disabled
VCC Operating
Supply Current
VCC = Max., f = fMAX
1/tRC
=
Commercial
Industrial
300
300
100
275
275
100
260 mA
260 mA
100 mA
ISB1
Automatic CE
CE2 <= VIL
Power-down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-down Current
—CMOS Inputs
CE2 <= 0.2V
Max. VCC,
CE > VCC – 0.2V,
VIN > VCC – 0.2V,
or VIN < 0.2V, f = 0
Commercial/
Industrial
50
50
50
mA
Capacitance[2]
Parameter
Package
Z54
Description
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 2.5V
Max.
6
Unit
CIN
Input Capacitance
pF
pF
pF
pF
BA48
Z54
8
COUT
I/O Capacitance
8
BA48
10
Notes:
1.
VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05331 Rev. **
Page 3 of 11
PRELIMINARY
CY7C1061AV25
AC Test Loads and Waveforms[3]
R1 1667 Ω
50Ω
2.5V
OUTPUT
= V /2
VTH
DD
OUTPUT
Z = 50Ω
30 pF*
0
R2
1538Ω
5 pF*
INCLUDING
JIG AND
SCOPE
(a)
* Capacitive Load consists of all com-
ponents of the test environment.
(b)
ALL INPUT PULSES
90%
10%
2.5V
90%
10%
GND
Fall time:
> 1V/ns
Rise time > 1V/ns
(c)
AC Switching Characteristics Over the Operating Range [4]
-8
-10
-12
Parameter
Read Cycle
tpower
tRC
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
VCC(typical) to the first access[5]
Read Cycle Time
1
8
1
1
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
12
tAA
Address to Data Valid
8
10
12
tOHA
Data Hold from Address Change
CE1 LOW/CE2 HIGH to Data Valid
OE LOW to Data Valid
3
3
3
tACE
8
5
10
5
12
6
tDOE
tLZOE
OE LOW to Low-Z
OE HIGH to High-Z[6]
1
3
0
1
3
0
1
3
0
tHZOE
tLZCE
5
5
5
5
6
6
CE1 LOW/CE2 HIGH to Low-Z[6]
CE1 HIGH/CE2 LOW to High-Z[6]
CE1 LOW/CE2 HIGH to Power-up[7]
CE1 HIGH/CE2 LOW to Power-down[7]
Byte Enable to Data Valid
Byte Enable to Low-Z
tHZCE
tPU
tPD
8
5
10
5
12
6
tDBE
tLZBE
1
1
1
tHZBE
Byte Disable to High-Z
5
5
6
Write Cycle[8, 9]
tWC
Write Cycle Time
8
6
10
7
12
8
ns
ns
tSCE
CE1 LOW / CE2 HIGH to Write End
Notes:
3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (2.3V). As soon as 1ms (Tpower) after reaching the
minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 1.5V) voltage.
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.1V, input pulse levels of 0 to 2.5V, and output loading of the specified
IOL/IOH and specified transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise.
5. This part has a voltage regulator which steps down the voltage from 2.5V to 2V internally. tpower time has to be provided initially before a Read/Write operation
is started.
6. tHZOE, tHZCE, tHZWE, tHZBE and tLZOE, tLZCE, t\LZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from
steady-state voltage.
7. These parameters are guaranteed by design and are not tested.
8. The internal Write time of the memory is defined by the overlap of CE1 LOW (CE2 HIGH) and WE LOW. Chip enables must be active and WE and byte enables must
be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of
the signal that terminates the Write.
9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
Document #: 38-05331 Rev. **
Page 4 of 11
PRELIMINARY
CY7C1061AV25
AC Switching Characteristics Over the Operating Range (continued)[4]
-8
-10
-12
Parameter
Description
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Min.
6
Max.
Min.
7
Max.
Min.
8
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAW
tHA
tSA
0
0
0
0
0
0
tPWE
tSD
6
7
8
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z[6]
5
5.5
0
6
tHD
0
0
tLZWE
tHZWE
tBW
3
3
3
WE LOW to High-Z[6]
5
5
6
Byte Enable to End of Write
6
7
8
Data Retention Waveform
DATA RETENTION MODE
> 1.5V
2.3V
2.3V
V
V
CC
DR
t
t
R
CDR
CE
Switching Waveforms
[10, 11]
Read Cycle No. 1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes:
10. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. CE2 = VIH
.
11. WE is HIGH for Read cycle.
Document #: 38-05331 Rev. **
Page 5 of 11
PRELIMINARY
CY7C1061AV25
Switching Waveforms (continued)
(OEControlled)[11, 12]
Read Cycle No. 2
ADDRESS
t
RC
CE
1
CE
2
t
ACE
OE
t
HZOE
t
DOE
BHE, BLE
t
LZOE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
I
t
CC
PU
V
CC
50%
50%
SUPPLY
CURRENT
I
SB
[13, 14, 15]
Write Cycle No. 1 (CE Controlled)
t
WC
ADDRESS
t
SA
t
SCE
CE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATAI/O
Notes:
12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
13. Data I/O is high-impedance if OE or BHE and/or BLE = VIH
.
14. If CE1 goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
15. CE is a shorthand combination of both CE1 and CE2 combined. It is active LOW.
Document #: 38-05331 Rev. **
Page 6 of 11
PRELIMINARY
CY7C1061AV25
Switching Waveforms (continued)
Write Cycle No. 2 (BLEor BHE Controlled)
t
WC
ADDRESS
t
t
BW
SA
BHE, BLE
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
HD
SD
DATAI/O
Write Cycle No.3 (WE Controlled, OE LOW)[13, 14, 15]
t
WC
ADDRESS
t
SCE
CE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
DATA I/O
t
LZWE
Document #: 38-05331 Rev. **
Page 7 of 11
PRELIMINARY
CY7C1061AV25
Truth Table
CE1 CE2 OE WE BLE
BHE
X
I/O0–I/O7
High-Z
I/O8–I/O15
High-Z
Mode
Power
H
X
L
L
L
L
L
L
L
X
L
X
X
L
X
X
H
H
H
L
X
X
L
Power-down
Power-down
Read All Bits
Standby (ISB
)
)
X
High-Z
High-Z
Standby (ISB
H
H
H
H
H
H
H
L
Data Out
Data Out
High-Z
Data Out
High-Z
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
)
)
L
L
H
L
Read Lower Bits Only
Read Upper Bits Only
Write All Bits
L
H
L
Data Out
Data In
High-Z
X
X
X
H
L
Data In
Data In
High-Z
L
L
H
L
Write Lower Bits Only
Write Upper Bits Only
Selected, Outputs Disabled
L
H
X
Data In
High-Z
H
X
High-Z
Ordering Information
Speed
Package
Name
(ns)
Ordering Code[16]
CY7C1061AV25-8ZC
CY7C1061AV25-8ZI
Package Type
Operating Range
Commercial
Industrial
8
Z54
BA48
Z54
54-pin TSOP II
48-ball Mini BGA
54-pin TSOP II
48-ball Mini BGA
54-pin TSOP II
48-ball Mini BGA
CY7C1061AV25-8BAC
CY7C1061AV25-8BAI
CY7C1061AV25-10ZC
CY7C1061AV25-10ZI
CY7C1061AV25-10BAC
CY7C1061AV25-10BAI
CY7C1061AV25-12ZC
CY7C1061AV25-12ZI
CY7C1061AV25-12BAC
CY7C1061AV25-12BAI
Commercial
Industrial
10
12
Commercial
Industrial
BA48
Z54
Commercial
Industrial
Commercial
Industrial
BA48
Commercial
Industrial
Note:
16. Contact a Cypress Representative for availability of the 48-ball Mini BGA (BA48) package.
Document #: 38-05331 Rev. **
Page 8 of 11
PRELIMINARY
CY7C1061AV25
Package Diagrams
54-lead Thin Small Outline Package, Type II Z54-II
51-85160-**
Document #: 38-05331 Rev. **
Page 9 of 11
PRELIMINARY
CY7C1061AV25
Package Diagrams (continued)
48-ball (8 mm x 20 mm x 1.2 mm) FBGA BA48G
51-85162-*A
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05331 Rev. **
Page 10 of 11
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
CY7C1061AV25
Document History Page
Document Title: CY7C1061AV25 1M x 16 Static RAM
Document Number: 38-05331
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
119624
01/30/03
DFP
New Data Sheet
Document #: 38-05331 Rev. **
Page 11 of 11
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