CY7C1061DV33_07 [CYPRESS]
16-Mbit (1M x 16) Static RAM; 16兆位（ 1M ×16 ）静态RAM
| 型号： | CY7C1061DV33_07 |
| 厂家： | 
CYPRESS |
| 描述： | 16-Mbit (1M x 16) Static RAM |
| 文件： | 总11页 (文件大小：542K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1061DV33
16-Mbit (1M x 16) Static RAM
Features
Functional Description
■ High speed
❐ tAA = 10 ns
The CY7C1061DV33 is a high performance CMOS Static RAM
organized as 1,048,576 words by 16 bits.
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO0 through IO7), is written
into the location specified on the address pins (A0 through A19).
If Byte High Enable (BHE) is LOW, then data from IO pins (IO8
through IO15) is written into the location specified on the address
pins (A0 through A19).
■ Low active power
❐ ICC = 175 mA at 10 ns
■ Low CMOS standby power
❐ ISB2 = 25 mA
■ Operating voltages of 3.3 ± 0.3V
■ 2.0V data retention
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from
memory appears on IO8 to IO15. See the Truth Table on page 9
for a complete description of Read and Write modes.
■ Automatic power down when deselected
■ TTL compatible inputs and outputs
■ Easy memory expansion with CE1 and CE2 features
■ Available in Pb-free 54-Pin TSOP II and 48-Ball VFBGA
packages
The input or output pins (IO0 through IO15) are placed in a high
impedance state when the device is deselected (CE1 HIGH/CE2
LOW), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE1
LOW, CE2 HIGH, and WE LOW).
The CY7C1061DV33 is available in a 54-Pin TSOP II package
with center power and ground (revolutionary) pinout, and a
48-Ball VFBGA package.
Logic Block Diagram
INPUT BUFFER
A
0
A
1
A
2
A
4
3
IO0 – IO7
1M x 16
ARRAY
A
A
5
IO8 – IO15
A
6
A
7
A
8
A
9
COLUMN
DECODER
BHE
WE
CE2
CE1
OE
BLE
Cypress Semiconductor Corporation
Document Number: 38-05476 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 06, 2007
CY7C1061DV33
Selection Guide
–10
10
Unit
ns
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
175
25
mA
mA
Pin Configuration
Figure 1. 54-Pin TSOP II (Top View) [1]
Figure 2. 48-Ball VFBGA (Top View) [1]
IO
V
1
2
3
4
6
5
IO
V
12
1
2
3
4
5
6
54
53
52
51
50
49
48
47
46
11
CC
SS
IO
IO
13
14
A2
A0
A1
CE2
A
B
C
10
9
OE
BLE
IO
V
IO
V
SS
CC
A4
A6
A7
A3
A5
CE1
IO1
IO3
IO8 BHE
IO9 IO10
IO0
IO2
IO
15
IO
8
A
A
A
A
A
A
7
4
3
2
1
0
5
A
A
A
A
8
9
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
45
44
IO11
VSS
VCC
D
E
F
A17
NC
BHE
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VCC
A16 IO4 VSS
IO12 NC
OE
V
CE
V
1
CC
SS
A14
A12 A13
A9
A15
IO5
WE
IO6
IO7
A19
WE
CE
NC
BLE
IO14 IO13
IO15 NC
2
A
A
10
19
G
H
A
18
A
11
A
17
A
12
A
16
A10 A11
A8
A
A18
13
A
15
IO
0
A
14
IO
7
V
CC
V
SS
IO
6
IO
5
IO
1
IO
2
V
SS
V
CC
IO
3
IO
4
Note
1. NC pins are not connected on the die.
Document Number: 38-05476 Rev. *D
Page 2 of 11
CY7C1061DV33
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage............. ...............................>2001V
(MIL-STD-883, Method 3015)
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Latch Up Current..................................................... >200 mA
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Operating Range
Ambient
Supply Voltage on VCC Relative to GND [2]....–0.5V to +4.6V
Range
VCC
Temperature
DC Voltage Applied to Outputs
Industrial
–40°C to +85°C
3.3V ± 0.3V
in High Z State [2]................................... –0.5V to VCC + 0.5V
DC Input Voltage [2] ............................... –0.5V to VCC + 0.5V
DC Electrical Characteristics
Over the Operating Range
–10
Parameter
Description
Test Conditions
Unit
Min
Max
VOH
VOL
VIH
VIL
IIX
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
VCC = Min, IOH = –4.0 mA
VCC = Min, IOL = 8.0 mA
2.4
V
V
0.4
2.0
–0.3
–1
VCC + 0.3
0.8
V
Input LOW Voltage [2]
Input Leakage Current
Output Leakage Current
V
GND < VI < VCC
GND < VOUT < VCC, Output disabled
VCC = Max, f = fMAX = 1/tRC, OUT = 0 mA CMOS levels
+1
µA
µA
mA
IOZ
ICC
–1
+1
VCC Operating Supply
Current
I
175
ISB1
ISB2
Automatic CE Power Down Max VCC, CE1 > VIH, CE2 < VIL,
Current — TTL Inputs VIN > VIH or VIN < VIL, f = fMAX
30
25
mA
mA
Automatic CE Power Down Max VCC, CE1 > VCC – 0.3V, CE2 < 0.3V,
Current —CMOS Inputs IN > VCC – 0.3V, or VIN < 0.3V, f = 0
V
Note
2.
V (min) = –2.0V and V (max) = V + 2V for pulse durations of less than 20 ns.
IL IH CC
Document Number: 38-05476 Rev. *D
Page 3 of 11
CY7C1061DV33
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
CIN
Description
Input Capacitance
IO Capacitance
Test Conditions
TSOP II
VFBGA
Unit
pF
TA = 25°C, f = 1 MHz, VCC = 3.3V
6
8
8
COUT
10
pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Test Conditions
TSOP II
VFBGA
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Still air, soldered on a 3 × 4.5 inch,
four layer printed circuit board
24.18
28.37
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
5.40
5.79
°C/W
AC Test Loads and Waveforms
The AC test loads and waveform diagram follows. [3]
HIGH-Z CHARACTERISTICS:
R1 317Ω
50
Ω
3.3V
= 1.5V
OUTPUT
VTH
OUTPUT
5 pF*
Z = 50
Ω
R2
351Ω
30 pF*
0
INCLUDING
JIG AND
SCOPE
(a)
(b)
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
ALL INPUT PULSES
3.0V
90%
10%
90%
10%
GND
FALL TIME:
> 1 V/ns
RISE TIME:
> 1 V/ns
(c)
Note
3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V (3.0V). 100 µs (t
) after reaching the minimum operating
power
DD
V
, normal SRAM operation begins including reduction in V to the data retention (V
, 2.0V) voltage.
CCDR
DD
DD
Document Number: 38-05476 Rev. *D
Page 4 of 11
CY7C1061DV33
AC Switching Characteristics
Over the Operating Range [4]
–10
Parameter
Description
Unit
Max
Min
Read Cycle
tpower
tRC
VCC(Typical) to the First Access [5]
Read Cycle Time
100
10
µs
ns
tAA
Address to Data Valid
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOHA
tACE
Data Hold from Address Change
CE1 LOW/CE2 HIGH to Data Valid
OE LOW to Data Valid
3
10
5
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
OE LOW to Low Z
OE HIGH to High Z [6]
1
3
0
5
5
CE1 LOW/CE2 HIGH to Low Z [6]
CE1 HIGH/CE2 LOW to High Z [6]
CE1 LOW/CE2 HIGH to Power Up [7]
CE1 HIGH/CE2 LOW to Power Down [7]
Byte Enable to Data Valid
Byte Enable to Low Z
tPD
10
5
tDBE
tLZBE
tHZBE
Write Cycle [8, 9]
tWC
1
Byte Disable to High Z
5
Write Cycle Time
10
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE1 LOW/CE2 HIGH to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
tAW
7
tHA
0
tSA
0
tPWE
tSD
7
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low Z [6]
5.5
0
tHD
tLZWE
tHZWE
tBW
3
WE LOW to High Z [6]
5
Byte Enable to End of Write
7
Notes
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use output
loading shown in part a) of AC Test Loads and Waveforms, unless specified otherwise.
5.
6.
t
t
gives the minimum amount of time that the power supply is at typical V values until the first memory access is performed.
CC
POWER
, t
, t
, t
, t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ±200 mV
HZOE HZCE HZWE HZBE LZOE LZCE LZWE
LZBE
from steady state voltage.
7. These parameters are guaranteed by design and are not tested.
8. The internal write time of the memory is defined by the overlap of WE, CE = V , and CE = V . Chip enables must be active and WE and byte enables must be LOW
1
IL
2
IH
to initiate a write, and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal that
terminates the write.
9. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
Document Number: 38-05476 Rev. *D
Page 5 of 11
CY7C1061DV33
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
Description
VCC for Data Retention
Conditions
Min
Typ
Max
Unit
V
2
ICCDR
Data Retention Current
VCC = 2V , CE1 > VCC – 0.2V,
CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V
25
mA
[10]
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
ns
[ 11]
tR
tRC
Data Retention Waveform
DATA RETENTION MODE
3.0V
3.0V
VCC
CE
VDR > 2V
t
t
R
CDR
Switching Waveforms
Figure 3. Read Cycle No. 1 [12, 13]
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes
10. Tested initially and after any design or process changes that may affect these parameters.
11. Full device operation requires linear V ramp from V to V > 50 µs or stable at V > 50 µs.
CC(min.)
CC
DR
CC(min.)
12. The device is continuously selected. OE, CE = V , BHE, BLE or both = V , and CE = V .
1
IL
IL
2
IH
13. WE is HIGH for read cycle.
Document Number: 38-05476 Rev. *D
Page 6 of 11
CY7C1061DV33
Switching Waveforms (continued)
Figure 4. Read Cycle No. 2 (OE Controlled) [13, 14]
ADDRESS
t
RC
CE1
CE2
t
ACE
OE
t
HZOE
t
DOE
BHE, BLE
t
LZOE
t
HZCE
t
DBE
t
LZBE
t
HZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
DATA VALID
t
LZCE
t
PD
ICC
ISB
t
PU
50%
SUPPLY
CURRENT
50%
Figure 5. Write Cycle No. 1 (CE Controlled) [15, 16, 17]
t
WC
ADDRESS
CE
t
SA
t
SCE
t
AW
t
HA
t
PWE
WE
t
BW
BHE, BLE
t
t
SD
HD
DATA IO
Notes
14. Address valid before or similar to CE transition LOW and CE transition HIGH.
1
2
15. CE is a shorthand combination of both CE and CE combined. It is active LOW.
1
2
16. Data IO is high impedance if OE, BHE, and/or BLE = V
.
IH
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 38-05476 Rev. *D
Page 7 of 11
CY7C1061DV33
Switching Waveforms (continued)
Figure 6. Write Cycle No. 2 (WE Controlled, OE LOW) [15, 16, 17]
t
WC
ADDRESS
CE
t
SCE
t
AW
t
HA
t
SA
t
PWE
WE
t
BW
BHE, BLE
t
HZWE
t
t
SD
HD
DATA IO
t
LZWE
Figure 7. Write Cycle No. 3 (BLE or BHE Controlled) [15]
t
WC
ADDRESS
BHE, BLE
t
SA
t
BW
t
AW
t
HA
t
PWE
WE
CE
t
SCE
t
t
SD
HD
DATA IO
Document Number: 38-05476 Rev. *D
Page 8 of 11
CY7C1061DV33
Truth Table
CE1 CE2 OE WE BLE BHE
IO0 – IO7
High Z
IO8 – IO15
High Z
Mode
Power Down
Power
H
X
L
L
L
L
L
L
L
X
L
X
X
L
X
X
H
H
H
L
X
X
L
X
X
L
Standby (ISB
)
)
High Z
High Z
Power Down
Standby (ISB
H
H
H
H
H
H
H
Data Out
Data Out
High Z
Data Out
High Z
Read All Bits
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
)
)
L
L
H
L
Read Lower Bits Only
Read Upper Bits Only
Write All Bits
L
H
L
Data Out
Data In
High Z
X
X
X
H
L
Data In
Data In
High Z
L
L
H
L
Write Lower Bits Only
Write Upper Bits Only
Selected, Outputs Disabled
L
H
X
Data In
High Z
H
X
High Z
Ordering Information
Speed
Package
Diagram
Operating
Range
Ordering Code
(ns)
Package Type
10
CY7C1061DV33-10ZSXI 51-85160 54-Pin TSOP II (Pb-Free)
Industrial
CY7C1061DV33-10BVXI 51-85178 48-Ball VFBGA (8 × 9.5 × 1 mm) (Pb-Free)
Package Diagrams
Figure 8. 54-Pin TSOP Type II
51-85160-**
Document Number: 38-05476 Rev. *D
Page 9 of 11
CY7C1061DV33
Package Diagrams (continued)
Figure 9. 48-Ball VFBGA (8 x 9.5 x 1 mm)
BOTTOM VIEW
A1 CORNER
TOP VIEW
C
C
Ø0.05 M
Ø0.25 M
A
B
A1 CORNER
Ø0.30 0.05ꢀ(48X
1
2
3
(
5
6
6
5
(
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.475
0.75
3.75
4.00 0.10
A
A
B
4.00 0.10
B
0.15ꢀ(8X
SEATING PLANE
C
51-85178. **
Document Number: 38-05476 Rev. *D
Page 10 of 11
CY7C1061DV33
Document History Page
Document Title: CY7C1061DV33 16-Mbit (1M x 16) Static RAM
Document Number: 38-05476
Issue
Date
Orig. of
Change
REV. ECN NO.
Description of Change
**
201560 See ECN
233748 See ECN
SWI
RKF
Advance datasheet for C9 IPP
*A
AC, DC parameters are modified as per EROS
(Specification number 01-2165)
Added Pb-free devices in the Ordering Information
*B
469420 See ECN
NXR
Converted from Advance Information to Preliminary
Corrected typo in the Document Title
Removed –8 and –12 speed bins from product offering
Removed Commercial Operating Range
Changed 2G-Ball of FBGA and pin 40 of TSOPII from DNU to NC
Included the Maximum ratings for Static Discharge Voltage and Latch Up Current on
page 3
Changed ICC(Max) from 220 mA to 125 mA
Changed ISB1(Max) from 70 mA to 30 mA
Changed ISB2(Max) from 40 mA to 25 mA
Specified the Overshoot specification in footnote 1.
Updated the Ordering Information Table
*C
*D
499604 See ECN
NXR
Added note 1 for NC pins
Updated Test Condition for ICC in DC Electrical Characteristics table
Updated the 48-Ball FBGA Package
1462583 See ECN VKN/AESA Converted from preliminary to final
Changed ICC specification from 125 mA to 175 mA
Updated thermal specs
© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05476 Rev. *D
Revised September 06, 2007
Page 11 of 11
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