CY7C109BL-15VC [CYPRESS]
128K x 8 Static RAM; 128K ×8静态RAM
| 型号： | CY7C109BL-15VC |
| 厂家： | 
CYPRESS |
| 描述： | 128K x 8 Static RAM |
| 文件： | 总12页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
009B
CY7C109B
CY7C1009B
128K x 8 Static RAM
put Enable (OE), and three-state drivers. Writing to the device
is accomplished by taking Chip Enable One (CE1) and Write
Enable (WE) inputs LOW and Chip Enable Two (CE2) input
HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then
written into the location specified on the address pins (A0
through A16).
Features
• High speed
— tAA = 12 ns
• Low active power
— 495 mW (max. 12 ns)
Reading from the device is accomplished by taking Chip En-
able One (CE1) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
• Low CMOS standby power
— 55 mW (max.) 4 mW
• 2.0V Data Retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OEoptions
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
Functional Description
The CY7C109B is available in standard 400-mil-wide SOJ and
32-pin TSOP type I packages. The CY7C1009B is available in
300-mil-wide SOJ package. The CY7C1009B and
CY7C109B are functionally equivalent in all other respects.
The CY7C109B / CY7C1009B is a high-performance CMOS
static RAM organized as 131,072 words by 8 bits. Easy mem-
ory expansion is provided by an active LOW Chip Enable
(CE1), an active HIGH Chip Enable (CE2), an active LOW Out-
a
Logic Block Diagram
Pin Configurations
SOJ
Top View
V
NC
32
31
30
1
CC
A
16
A
15
2
3
A
14
CE
2
A
4
12
29
28
WE
5
A
A
A
A
13
A
8
A
7
27
26
6
6
5
7
9
25
24
23
22
21
A
A
3
8
9
10
11
12
13
A
4
11
OE
I/O
A
A
10
2
0
A
1
CE
I/O
I/O
INPUT BUFFER
1
7
6
A
0
I/O
I/O
I/O
I/O
I/O
0
1
2
20
19
1
A
0
A
1
I/O
5
14
15
16
I/O
I/O
18
17
4
2
A
2
GND
3
109B–2
A
3
4
A
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
32
31
OE
A10
CE
I/O
I/O
I/O
3
4
5
512 x 256 x 8
ARRAY
A
5
6
3
4
5
6
7
8
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A
7
8
A
TSOP I
Top View
9
(not to scale)
I/O
10
11
12
13
14
15
16
6
7
POWER
DOWN
COLUMN
DECODER
CE
1
2
CE
I/O
WE
A1
A2
A3
109B–1
OE
109B–3
Selection Guide
7C109B-12
7C1009B-12
7C109B-15
7C1009B-15
7C109B-20
7C1009B-20
7C109B-25
7C1009B-25
7C109B-35
7C1009B-35
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
12
90
10
15
80
10
20
75
10
25
70
10
35
60
10
Maximum CMOS Standby Current (mA)
Low Power Version
2
2
2
-
-
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05038 Rev. **
Revised August 24, 2001
CY7C109B
CY7C1009B
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V
Ambient
Range
Commercial
Industrial
Temperature[2]
0°C to +70°C
VCC
5V ± 10%
5V ± 10%
DC Voltage Applied to Outputs
in High Z State[1]....................................–0.5V to VCC + 0.5V
−40°C to +85°C
DC Input Voltage[1] ................................–0.5V to VCC + 0.5V
Current into Outputs (LOW).........................................20 mA
Electrical Characteristics Over the Operating Range
7C109B-12
7C1009B-12
7C109B-15
7C1009B-15
Parameter
Description
Test Conditions
Min.
Max.
Min. Max.
Unit
VOH
Output HIGH Voltage VCC = Min.,
2.4
2.4
V
IOH = –4.0 mA
VOL
VIH
Output LOW Voltage VCC = Min.,
IOL = 8.0 mA
0.4
0.4
V
V
Input HIGH Voltage
2.2
VCC
+ 0.3
2.2
VCC
+ 0.3
VIL
IIX
Input LOW Voltage[1]
–0.3
–1
0.8
+1
+5
–0.3
–1
0.8
+1
+5
V
Input Load Current
GND < VI < VCC
µA
µA
IOZ
Output Leakage
Current
GND < VI < VCC
,
–5
–5
Output Disabled
IOS
ICC
Output Short
VCC = Max.,
VOUT = GND
–300
–300
mA
mA
Circuit Current[3]
VCC Operating
Supply Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
90
80
ISB1
Automatic CE
Power-Down Current or CE2 < VIL,
Max. VCC, CE1 > VIH
45
40
mA
—TTL Inputs
VIN > VIH or
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current CE1 > VCC – 0.3V,
—CMOS Inputs
Max. VCC
,
10
2
10
2
mA
mA
L
or CE2 < 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. A is the case temperature.
T
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Document #: 38-05038 Rev. **
Page 2 of 12
CY7C109B
CY7C1009B
Electrical Characteristics Over the Operating Range (continued)
7C109B-20
7C109B-25
7C109B-35
7C1009B-20 7C1009B-25 7C1009B-35
Parameter
Description
Test Conditions
VCC = Min.,
IOH = –4.0 mA
Min. Max. Min. Max. Min. Max. Unit
VOH
Output HIGH Voltage
2.4
2.4
2.4
V
V
V
VOL
VIH
Output LOW Voltage
Input HIGH Voltage
VCC = Min.,
IOL = 8.0 mA
0.4
0.4
0.4
2.2
VCC
2.2
VCC
2.2
VCC
+ 0.3
+ 0.3
+ 0.3
VIL
IIX
Input LOW Voltage[1]
Input Load Current
–0.3
–1
0.8
+1
+5
–0.3
–1
0.8
+1
+5
–0.3
–1
0.8
+1
+5
V
GND < VI < VCC
µA
µA
IOZ
Output Leakage
Current
GND < VI < VCC
,
–5
–5
–5
Output Disabled
IOS
ICC
Output Short
VCC = Max.,
VOUT = GND
–300
–300
–300 mA
Circuit Current[3]
VCC Operating
Supply Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
75
70
60
25
mA
mA
ISB1
Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE1 > VIH
or CE2 < VIL,
VIN > VIH or
30
30
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC
CE1 > VCC – 0.3V,
or CE2 < 0.3V,
,
10
2
10
10
mA
mA
L
—
—
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
Capacitance[4]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
Unit
CIN
TA = 25°C, f = 1 MHz,
VCC = 5.0V
9
8
pF
pF
COUT
AC Test Loads and Waveforms
R1 480Ω
ALL INPUT PULSES
90%
10%
R1 480Ω
5V
5V
OUTPUT
3.0V
90%
10%
OUTPUT
R2
255Ω
R2
255Ω
GND
≤ 3 ns
30 pF
5 pF
≤ 3 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(b)
10B9–4
(a)
109B–5
THÉ
Equivalent to:
VENIN EQUIVALENT
167Ω
1.73V
OUTPUT
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05038 Rev. **
Page 3 of 12
CY7C109B
CY7C1009B
Switching Characteristics[5] Over the Operating Range
7C109B-12
7C1009B-12
7C109B-15
7C1009B-15
Parameter
Description
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
Address to Data Valid
12
3
15
3
ns
ns
ns
ns
tAA
12
15
tOHA
tACE
Data Hold from Address Change
CE1 LOW to Data Valid, CE2 HIGH to Data
Valid
12
6
15
7
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
OE LOW to Data Valid
ns
ns
ns
ns
ns
ns
OE LOW to Low Z
OE HIGH to High Z[6, 7]
CE1 LOW to Low Z, CE2 HIGH to Low Z[7]
CE1 HIGH to High Z, CE2 LOW to High Z[6, 7]
0
3
0
0
3
0
6
6
7
7
CE1 LOW to Power-Up, CE2 HIGH to
Power-Up
tPD
CE1 HIGH to Power-Down, CE2 LOW to
Power-Down
12
15
ns
WRITE CYCLE[8]
tWC
tSCE
tAW
tHA
Write Cycle Time[9]
12
10
10
0
15
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE1 LOW to Write End, CE2 HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tSA
0
0
tPWE
tSD
10
7
12
8
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[7]
tHD
0
0
tLZWE
3
3
tHZWE
WE LOW to High Z[6, 7]
6
7
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6.
tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write, and
the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
Document #: 38-05038 Rev. **
Page 4 of 12
CY7C109B
CY7C1009B
Switching Characteristics[5] Over the Operating Range (continued)
7C109B-20
7C109B-25
7C1009B-25
7C109B-35
7C1009B-35
7C1009B-20
Parameter
Description
Min.
20
3
Max.
Min.
25
5
Max.
Min.
35
5
Min.
Unit
READ CYCLE
tRC
Read Cycle Time
Address to Data Valid
ns
ns
ns
ns
tAA
20
25
35
tOHA
tACE
Data Hold from Address Change
CE1 LOW to Data Valid, CE2 HIGH to Data
Valid
20
8
25
10
35
15
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
OE LOW to Data Valid
ns
ns
ns
ns
ns
ns
OE LOW to Low Z
OE HIGH to High Z[6, 7]
CE1 LOW to Low Z, CE2 HIGH to Low Z[7]
CE1 HIGH to High Z, CE2 LOW to High Z[6, 7]
0
3
0
0
5
0
0
5
0
8
8
10
10
15
15
CE1 LOW to Power-Up, CE2 HIGH to
Power-Up
tPD
CE1 HIGH to Power-Down, CE2 LOW to
Power-Down
20
25
35
ns
WRITE CYCLE[8]
tWC
Write Cycle Time[9]
20
15
15
0
25
20
20
0
35
25
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
CE1 LOW to Write End, CE2 HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tHA
tSA
0
0
0
tPWE
tSD
12
10
0
15
15
0
20
20
0
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[7]
tHD
tLZWE
tHZWE
3
5
5
WE LOW to High Z[6, 7]
8
10
15
Data Retention Characteristics Over the Operating Range (Low Power version only)
Parameter
VDR
Description
VCC for Data Retention
Conditions
Min.
Max
Unit
V
No input may exceed VCC + 0.5V
VCC = VDR = 2.0V,
CE1 > VCC – 0.3V or CE2 < 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
2.0
ICCDR
tCDR
Data Retention Current
150
µA
ns
Chip Deselect to Data Retention Time
Operation Recovery Time
0
tR
200
µs
Document #: 38-05038 Rev. **
Page 5 of 12
CY7C109B
CY7C1009B
Data Retention Waveform
DATA RETENTION MODE
> 2V
V
CC
4.5V
4.5V
V
DR
t
t
R
CDR
CE
109B-6
Switching Waveforms
Read Cycle No. 1[10, 11]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
109B–7
Read Cycle No. 2 (OE Controlled)[11, 12]
ADDRESS
t
RC
CE
1
CE
2
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
I
t
CC
PU
V
CC
50%
50%
SUPPLY
CURRENT
I
SB
109B–8
Notes:
10. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH
.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
Document #: 38-05038 Rev. **
Page 6 of 12
CY7C109B
CY7C1009B
Switching Waveforms (continued)
Write Cycle No. 1 (CE1 or CE2 Controlled)[13, 14]
t
WC
ADDRESS
t
SCE
CE
1
t
SA
CE
2
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
109B–9
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14]
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 15
t
HZOE
109B–10
Notes:
13. Data I/O is high impedance if OE = VIH
.
14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
15. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05038 Rev. **
Page 7 of 12
CY7C109B
CY7C1009B
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[14]
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 15
DATA I/O
DATA VALID
t
t
LZWE
HZWE
10B9–11
Truth Table
CE1
H
CE2
X
OE
X
WE
I/O0 – I/O7
Mode
Power
X
X
H
L
High Z
High Z
Data Out
Data In
High Z
Power-Down
Power-Down
Read
Standby (ISB)
X
L
X
Standby (ISB
)
L
H
L
Active (ICC
Active (ICC
Active (ICC)
)
L
H
X
Write
)
L
H
H
H
Selected, Outputs Disabled
Document #: 38-05038 Rev. **
Page 8 of 12
CY7C109B
CY7C1009B
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
32-Lead (400-Mil) Molded SOJ
32-Lead (300-Mil) Molded SOJ
32-Lead TSOP Type I
12
CY7C109B-12VC
CY7C1009B-12VC
CY7C109B-12ZC
CY7C109B-15VC
CY7C109BL-15VC
CY7C1009B-15VC
CY7C109B-15ZC
CY7C109BL-15ZC
CY7C109B-15VI
CY7C109BL-15VI
CY7C1009B-15VI
CY7C109B-15ZI
CY7C109B-20VC
CY7C1009B-20VC
CY7C109B-20VI
CY7C109B-20ZC
CY7C109B-20ZI
CY7C109B-25VC
CY7C1009B-25VC
CY7C109B-25VI
CY7C109B-25ZC
CY7C109B-25ZI
CY7C109B-35VC
CY7C1009B-35VC
CY7C109B-35VI
V33
V32
Z32
V33
V33
V32
Z32
Z32
V33
V33
V32
Z32
V33
V32
V33
Z32
Z32
V33
V32
V33
Z32
Z32
V33
V32
V33
Commercial
15
32-Lead (400-Mil) Molded SOJ
32-Lead (400-Mil) Molded SOJ
32-Lead (300-Mil) Molded SOJ
32-Lead TSOP Type I
Commercial
32-Lead TSOP Type I
32-Lead (400-Mil) Molded SOJ
32-Lead (400-Mil) Molded SOJ
32-Lead (300-Mil) Molded SOJ
32-Lead TSOP Type I
Industrial
20
25
35
32-Lead (400-Mil) Molded SOJ
32-Lead (300-Mil) Molded SOJ
32-Lead (400-Mil) Molded SOJ
32-Lead TSOP Type I
Commercial
Industrial
Commercial
Industrial
32-Lead TSOP Type I
32-Lead (400-Mil) Molded SOJ
32-Lead (300-Mil) Molded SOJ
32-Lead (400-Mil) Molded SOJ
32-Lead TSOP Type I
Commercial
Industrial
Commercial
Industrial
32-Lead TSOP Type I
32-Lead (400-Mil) Molded SOJ
32-Lead (300-Mil) Molded SOJ
32-Lead (400-Mil) Molded SOJ
Commercial
Industrial
Document #: 38-05038 Rev. **
Page 9 of 12
CY7C109B
CY7C1009B
Package Diagrams
32-Lead (300-Mil) Molded SOJ V32
51-85041-A
32-Lead (400-Mil) Molded SOJ V33
51-85033-A
Document #: 38-05038 Rev. **
Page 10 of 12
CY7C109B
CY7C1009B
Package Diagrams (continued)
32-Lead Thin Small Outline Package Z32
51-85056-C
Document #: 38-05038 Rev. **
Page 11 of 12
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C109B
CY7C1009B
Document Title: CY7C109B, CY7C1009 128K x 8 SRAM
Document Number: 38-05038
Issue
ECN NO. Date
Orig. of
Change
REV.
Description of Change
**
106832
09/22/01
SZV
Change from Spec number: 38-00971 to 38-05038
Document #: 38-05038 Rev. **
Page 12 of 12
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