CY7C109BN-15VCT [CYPRESS]
Standard SRAM, 128KX8, 15ns, CMOS, PDSO32, 0.400 INCH, SOJ-32;
| 型号： | CY7C109BN-15VCT |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 128KX8, 15ns, CMOS, PDSO32, 0.400 INCH, SOJ-32 静态存储器 光电二极管 |
| 文件： | 总9页 (文件大小：443K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C109BN
CY7C1009BN
128K x 8 Static RAM
Features
Functional Description[1]
• High speed
The CY7C109BN/CY7C1009BN is a high-performance
CMOS static RAM organized as 131,072 words by 8 bits. Easy
memory expansion is provided by an active LOW Chip Enable
(CE1), an active HIGH Chip Enable (CE2), an active LOW
Output Enable (OE), and three-state drivers. Writing to the
device is accomplished by taking Chip Enable One (CE1) and
Write Enable (WE) inputs LOW and Chip Enable Two (CE2)
input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is
then written into the location specified on the address pins (A0
through A16).
— tAA = 12 ns
• Low active power
— 495 mW (max. 12 ns)
• Low CMOS standby power
— 55 mW (max.) 4 mW
• 2.0V Data Retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OE options
Reading from the device is accomplished by taking Chip
Enable One (CE1) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
The CY7C109BN is available in standard 400-mil-wide SOJ
and 32-pin TSOP type I packages. The CY7C1009BN is
available in a 300-mil-wide SOJ package. The CY7C1009BN
and CY7C109BN are functionally equivalent in all other
respects.
Logic Block Diagram
Pin Configurations
SOJ
Top View
V
NC
32
31
30
1
CC
A
16
A
15
CE
2
3
4
A
14
2
A
12
29
28
WE
5
A
7
A
6
A
5
A
A
A
13
8
27
26
6
7
9
25
24
23
22
21
A
A
8
9
10
11
12
13
A
4
3
11
OE
I/O
0
A
A
A
10
2
1
INPUT BUFFER
CE
I/O
I/O
1
7
6
A
I/O
0
0
I/O
I/O
1
20
19
A
0
A
1
I/O
I/O
GND
I/O
1
5
14
15
16
I/O
I/O
2
18
17
4
3
2
A
2
A
4
3
A
A
A
A
A
WE
CE
A
1
2
32
31
OE
11
I/O
I/O
I/O
I/O
3
4
5
512 x 256 x 8
ARRAY
A
A
9
8
10
5
6
3
4
5
6
7
8
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CE
I/O
A
13
7
A
7
8
I/O
I/O
6
5
A
2
15
I/O
I/O
TSOP I
4
3
V
Top View
CC
NC
A
A
A
A
A
6
A
A
9
GND
(not to scale)
I/O
10
11
12
13
14
15
16
16
2
6
7
POWER
DOWN
I/O
1
COLUMN
DECODER
14
12
CE
2
WE
1
I/O
0
CE
A
0
7
I/O
A
1
A
2
5
4
A
3
OE
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-06430 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 1, 2006
CY7C109BN
CY7C1009BN
Selection Guide
7C109B-12
7C109B-15
7C109B-20
7C1009B-12
7C1009B-15
7C1009B-20
Unit
ns
Maximum Access Time
12
90
10
2
15
80
10
2
20
75
10
2
Maximum Operating Current
Maximum CMOS Standby Current
mA
mA
mA
L
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-Up Current.....................................................>200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[2] .... –0.5V to +7.0V
Operating Range
Ambient
Range
Commercial
Industrial
Temperature
0°C to +70°C
−40°C to +85°C
VCC
DC Voltage Applied to Outputs
in High Z State[2] ....................................–0.5V to VCC + 0.5V
5V ± 10%
5V ± 10%
DC Input Voltage[2].................................–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range
7C109BN-12
7C1009BN-12
7C109BN-15
7C1009BN-15
7C109BN-20
7C1009BN-20
Parameter
VOH
Description
Test Conditions
Min.
Max.
Min.
Max.
Min.
Max.
Unit
V
Output HIGH Voltage VCC = Min., IOH = –4.0 mA
Output LOW Voltage VCC = Min., IOL = 8.0 mA
Input HIGH Voltage
2.4
2.4
2.4
VOL
0.4
VCC + 0.3
0.8
0.4
0.4
V
VIH
2.2
–0.3
–1
2.2
–0.3
–1
VCC + 0.3 2.2 VCC + 0.3
V
VIL
Input LOW Voltage[2]
0.8
+1
–0.3
–1
0.8
+1
V
IIX
Input Leakage
Current
GND < VI < VCC
+1
µA
IOZ
IOS
ICC
ISB1
Output Leakage
Current
GND < VI < VCC
Output Disabled
,
–5
+5
–300
90
–5
+5
–300
80
–5
+5
–300
75
µA
mA
mA
mA
Output Short
VCC = Max., VOUT = GND
Circuit Current[3]
VCC Operating
Supply Current
VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC
Automatic CE
Power-Down Current or CE2 < VIL, VIN > VIH or
Max. VCC, CE1 > VIH
45
40
30
—TTL Inputs
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current CE1 > VCC – 0.3V,
—CMOS Inputs or CE2 < 0.3V,
Max. VCC
,
10
2
10
2
10
2
mA
mA
L
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
Capacitance[4]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz,
CC = 5.0V
Max.
Unit
CIN
Input Capacitance
Output Capacitance
9
8
pF
pF
V
COUT
Notes:
2. Minimum voltage is –2.0V for pulse durations of less than 20 ns.
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-06430 Rev. **
Page 2 of 9
CY7C109BN
CY7C1009BN
AC Test Loads and Waveforms
R1 480Ω
ALL INPUT PULSES
90%
10%
R1 480Ω
5V
5V
OUTPUT
3.0V
GND
90%
10%
OUTPUT
R2
255Ω
R2
255Ω
30 pF
5 pF
≤ 3 ns
≤ 3 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(b)
(a)
THÉ
Equivalent to:
VENIN EQUIVALENT
167Ω
1.73V
OUTPUT
Switching Characteristics[5] Over the Operating Range
7C109BN-12
7C1009BN-12
7C109BN-15
7C1009BN-15
7C109BN-20
7C1009BN-20
Parameter
Read Cycle
tRC
Description
Min.
12
3
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
15
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
12
15
20
tOHA
Data Hold from Address Change
CE LOW to Data Valid, CE HIGH to Data
3
3
tACE
12
6
15
7
20
8
Valid
1
2
tDOE
OE LOW to Data Valid
tLZOE
tHZOE
tLZCE
tHZCE
tPU
OE LOW to Low Z
OE HIGH to High Z[6, 7]
CE1 LOW to Low Z, CE2 HIGH to Low Z[7]
CE1 HIGH to High Z, CE2 LOW to High Z[6, 7]
0
3
0
0
3
0
0
3
0
6
6
7
7
8
8
CE1 LOW to Power-Up, CE2 HIGH to Power-Up
tPD
CE1 HIGH to Power-Down, CE2 LOW to
Power-Down
12
15
20
Write Cycle[8]
tWC
tSCE
tAW
tHA
Write Cycle Time[9]
12
10
10
0
15
12
12
0
20
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE1 LOW to Write End, CE2 HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tSA
0
0
0
tPWE
tSD
10
7
12
8
12
10
0
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[7]
tHD
0
0
tLZWE
3
3
3
tHZWE
WE LOW to High Z[6, 7]
6
7
8
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I and 30-pF load capacitance.
OL OH
6. t
, t
, and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
HZOE HZCE
HZWE
7. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
8. The internal write time of the memory is defined by the overlap of CE LOW, CE HIGH, and WE LOW. CE and WE must be LOW and CE HIGH to initiate a
1
2
1
2
write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the
signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
Document #: 001-06430 Rev. **
Page 3 of 9
CY7C109BN
CY7C1009BN
Data Retention Characteristics Over the Operating Range (Low Power version only)
Parameter
VDR
Description
VCC for Data Retention
Conditions
Min.
Max
Unit
V
No input may exceed VCC + 0.5V
VCC = VDR = 2.0V,
CE1 > VCC – 0.3V or CE2 < 0.3V,
2.0
ICCDR
tCDR
Data Retention Current
150
µA
ns
Chip Deselect to Data Retention Time
Operation Recovery Time
0
V
IN > VCC – 0.3V or VIN < 0.3V
tR
200
µs
Data Retention Waveform
DATA RETENTION MODE
V
CC
4.5V
4.5V
>
V
DR
2V
t
t
R
CDR
CE
Switching Waveforms
Read Cycle No. 1[10, 11]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[11, 12]
ADDRESS
t
RC
CE
1
CE
2
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
ICC
t
PU
V
CC
50%
50%
SUPPLY
CURRENT
ISB
Notes:
10. Device is continuously selected. OE, CE = V , CE = V .
IH
1
IL
2
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW and CE transition HIGH.
1
2
Document #: 001-06430 Rev. **
Page 4 of 9
CY7C109BN
CY7C1009BN
Switching Waveforms (continued)
Write Cycle No. 1 (CE1 or CE2 Controlled)[13, 14]
t
WC
ADDRESS
t
SCE
CE
1
t
SA
CE
2
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14]
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
SCE
t
t
HA
AW
t
t
PWE
SA
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 15
t
HZOE
Notes:
13. Data I/O is high impedance if OE = V
.
IH
14. If CE goes HIGH or CE goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
1
2
15. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 001-06430 Rev. **
Page 5 of 9
CY7C109BN
CY7C1009BN
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[14]
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 15
DATA I/O
DATA VALID
t
t
LZWE
HZWE
Truth Table
CE1
H
CE2
X
OE
X
WE
I/O0–I/O7
Mode
Power
X
X
H
L
High Z
High Z
Data Out
Data In
High Z
Power-Down
Power-Down
Read
Standby (ISB
)
)
X
L
X
Standby (ISB
L
H
L
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
H
X
Write
L
H
H
H
Selected, Outputs Disabled
Document #: 001-06430 Rev. **
Page 6 of 9
CY7C109BN
CY7C1009BN
Ordering Information
Speed
Package
Diagram
Operating
Range
(ns)
Ordering Code
Package Type
32-Lead (400-Mil) Molded SOJ
32-Lead (300-Mil) Molded SOJ
32-Lead TSOP Type I
12
CY7C109BN-12VC
CY7C1009BN-12VC
CY7C109BN-12ZC
CY7C109BN-12ZXC
CY7C109BNL-15VC
CY7C109BN-15VC
CY7C1009BN-15VC
CY7C109BN-15ZC
CY7C109BN-15ZXC
CY7C109BN-15VI
CY7C1009BN-15VI
CY7C109BN-20VC
CY7C1009BN-20VC
CY7C109BN-20VI
CY7C109BN-20ZC
CY7C109BN-20ZXC
51-85032
51-85031
51-85056
51-85056
51-85032
51-85032
51-85031
51-85056
51-85056
51-85032
51-85031
51-85032
51-85031
51-85032
51-85056
51-85056
Commercial
32-Lead TSOP Type I (Pb-free)
32-Lead (400-Mil) Molded SOJ
32-Lead (400-Mil) Molded SOJ
32-Lead (300-Mil) Molded SOJ
32-Lead TSOP Type I
15
Commercial
32-Lead TSOP Type I (Pb-free)
32-Lead (400-Mil) Molded SOJ
32-Lead (300-Mil) Molded SOJ
32-Lead (400-Mil) Molded SOJ
32-Lead (300-Mil) Molded SOJ
32-Lead (400-Mil) Molded SOJ
32-Lead TSOP Type I
Industrial
20
Commercial
Industrial
Commercial
32-Lead TSOP Type I (Pb-free)
Please contact local sales representative regarding availability of these parts
Package Diagrams
28-Lead (400-Mil) Molded SOJ (51-85032)
PIN 1 I.D
14
1
MIN.
MAX.
DIMENSIONS IN INCHES
.435
.445
.395
.405
15
28
.720
.730
SEATING PLANE
.128
.148
.007
.013
0.004
.026
.032
.360
.380
.050
TYP.
.025 MIN.
51-85032-*B
.015
.020
Document #: 001-06430 Rev. **
Page 7 of 9
CY7C109BN
CY7C1009BN
Package Diagrams (continued)
28-Lead (300-Mil) Molded SOJ (51-85031)
NOTE :
1. JEDEC STD REF MO088
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE
MIN.
3. DIMENSIONS IN INCHES
MAX.
DETAIL
A
PIN 1 ID
EXTERNAL LEAD DESIGN
14
1
0.291
0.300
0.330
0.350
0.026
0.032
0.013
0.019
15
28
0.014
0.020
OPTION 1
OPTION 2
0.697
0.713
SEATING PLANE
0.120
0.140
0.007
0.013
0.004
A
0.262
0.272
0.050
TYP.
0.025 MIN.
51-85031-*C
32-Lead TSOP I (8x20 mm) (51-85056)
51-85056-*D
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-06430 Rev. **
Page 8 of 9
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C109BN
CY7C1009BN
Document History Page
Document Title: CY7C109BN/CY7C1009BN 128K x 8 Static RAM
Document Number: 001-06430
Issue
Date
Orig. of
REV.
ECN NO.
Change Description of Change
**
423847
See ECN
NXR
New Data Sheet
Document #: 001-06430 Rev. **
Page 9 of 9
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