CY7C1219H-100AXC [CYPRESS]
1-Mbit (32K x 36) Pipelined DCD Sync SRAM; 1兆位（ 32K ×36 ）流水线DCD同步SRAM
| 型号： | CY7C1219H-100AXC |
| 厂家： | 
CYPRESS |
| 描述： | 1-Mbit (32K x 36) Pipelined DCD Sync SRAM |
| 文件： | 总16页 (文件大小：360K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1219H
1-Mbit (32K x 36) Pipelined DCD Sync SRAM
Features
Functional Description[1]
• Registered inputs and outputs for pipelined operation
• Optimal for performance (Double-Cycle deselect)
— Depth expansion without wait state
The CY7C1219H SRAM integrates 32K x 36 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW[A:D], and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
• 32K × 36-bit common I/O architecture
• 3.3V core power supply (VDD
)
• 2.5V/3.3V I/O power supply (VDDQ
)
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel®
Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the byte write control inputs. GW active LOW
causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penal-
izing system performance.
• Asynchronous Output Enable
• Available in JEDEC-standard lead-free 100-Pin TQFP
package
• “ZZ” Sleep Mode option
The CY7C1219H operates from a +3.3V core power supply
while all outputs operate with either a +2.5V or +3.3V supply.
All
inputs
and
outputs
are
JEDEC-standard
JESD8-5-compatible.
Selection Guide
166 MHz
3.5
133 MHz
4.0
Unit
ns
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
240
225
mA
mA
40
40
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05664 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 5, 2006
CY7C1219H
Functional Block Diagram
ADDRESS
REGISTER
A0,A1,A
2
A[1:0]
MODE
Q1
ADV
CLK
BINARY
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQD,DQP
D
DQD, DQP
D
BYTE
BYTE
BW
D
WRITE REGISTER
WRITE DRIVER
DQC, DQP
BYTE
WRITE DRIVER
c
DQ
BYTE
WRITE REGISTER
c
,DQP
C
MEMORY
ARRAY
BW
C
DQs
OUTPUT
BUFFERS
OUTPUT
REGISTERS
SENSE
AMPS
DQP
DQP
DQP
DQP
A
B
C
DQ
BYTE
WRITE DRIVER
B
,DQP
B
E
DQ
BYTE
WRITE REGISTER
B
,DQP
B
BW
BW
B
A
D
DQ
BYTE
WRITE DRIVER
A
,
DQP
A
DQA , DQP
A
BYTE
WRITE REGISTER
BWE
INPUT
REGISTERS
GW
ENABLE
REGISTER
PIPELINED
ENABLE
CE
CE
CE
1
2
3
OE
SLEEP
ZZ
CONTROL
Document #: 38-05664 Rev. *B
Page 2 of 16
CY7C1219H
Pin Configurations
100-Pin TQFP
Top View
DQPc
DQc
1
2
3
4
5
6
7
8
80
79
78
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
DQc
VDDQ
VSSQ
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
VDD
NC
VSS
CY7C1219H
NC
VDD
ZZ
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
30
Document #: 38-05664 Rev. *B
Page 3 of 16
CY7C1219H
Pin Descriptions
Pin
Type
Description
A0, A1, A
Input-
Synchronous
Address Inputs used to select one of the 32K address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0]
are fed to the two-bit counter.
BWA,BWB,
BWC, BWD
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
GW
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE).
BWE
CLK
CE1
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to conduct a byte write.
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled
only when a new external address is loaded.
CE2
CE3
OE
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external
address is loaded.
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select/deselect the device. CE3 is sampled only when a new external
address is loaded.
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act
as input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
ADV
Input-
Synchronous
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst cycle.
ADSP
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A[1:0]
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
ZZ
Input-
Synchronous
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A[1:0]
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized.
Input-
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical
Asynchronous “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or
left floating. ZZ pin has an internal pull-down.
DQs
DQP[A:D]
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQP[A:D] are placed in a tri-state condition.
VDD
Power Supply Power supply inputs to the core of the device.
Ground Ground for the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
VSS
VDDQ
VSSQ
MODE
I/O Ground
Ground for the I/O circuitry.
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. Mode Pin has an internal pull-up.
NC
No Connects. Not internally connected to the die. 2M, 4M, 9M, 18M, 72M, 144M, 288M, 576M,
and 1G are address expansion pins and are not internally connected to the die.
Document #: 38-05664 Rev. *B
Page 4 of 16
CY7C1219H
then the write operation is controlled by BWE and BW[A:D]
signals. The CY7C1219H provides byte write capability that
is described in the Write Cycle Description table. Asserting the
Byte Write Enable input (BWE) with the selected Byte Write
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided
to simplify the write operations.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1219H supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Because the CY7C1219H is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQ are automatically tri-stated whenever
a write cycle is detected, regardless of the state of OE.
Accesses can
Strobe (ADSP)
be initiated with either the Processor Address
or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and (4)
the appropriate combination of the write inputs (GW, BWE,
and BW[A:D]) are asserted active to conduct a write to the
desired byte(s). ADSC triggered write accesses require a
single clock cycle to complete. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the memory core.
The ADV input is ignored during this cycle. If a global write is
conducted, the data presented to the DQX is written into the
corresponding address location in the memory core. If a byte
write is conducted, only the selected bytes are written. Bytes
not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Synchronous Chip Selects CE1, CE2, CE3 and an
asynchronous Output Enable (OE) provide for easy bank
output tri-state control.
selection and
ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the Write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corre-
sponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within tCO if OE is active LOW. The only exception
occurs when the SRAM is emerging from a deselected state
to a selected state, its outputs are always tri-stated during the
first cycle of the access. After the first cycle of the access, the
outputs are controlled by the OE signal. Consecutive single
read cycles are supported.
Because the CY7C1219H is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQX inputs. Doing so will tri-state the output drivers. As
a
safety precaution, DQX are automatically tri-stated
whenever a write cycle is detected, regardless of the state of
OE.
Burst Sequences
The CY7C1219H provides a two-bit wraparound counter, fed
by A[1:0], that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input. Both read and write burst operations
are supported.
The CY7C1219H is a double-cycle deselect part. Once the
SRAM is deselected at clock rise by the chip select and either
ADSP or ADSC signals, its output will tri-state immediately
after the next clock rise.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Single Write Accesses Initiated by ADSP
Sleep Mode
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
chip select is asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the memory core.
The write signals (GW, BWE, and BW[A:D]) and ADV inputs are
ignored during this first cycle.
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corre-
sponding address location in the memory core. If GW is HIGH,
Document #: 38-05664 Rev. *B
Page 5 of 16
CY7C1219H
Linear Burst Address Table (MODE = GND)
Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Truth Table[2, 3, 4, 5, 6]
Address
Used CE1 CE2 CE3 ZZ
Operation
ADSP ADSC ADV WRITE OE
CLK
DQ
Deselected Cycle,
Power-down
None
None
None
None
None
None
H
L
L
L
L
X
X
X
H
X
H
L
L
L
L
L
X
L
X
X
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L-H
Tri-State
Deselected Cycle,
Power-down
L
L
L-H
L-H
L-H
L-H
Tri-State
Tri-State
Tri-State
Tri-State
Deselected Cycle,
Power-down
X
L
L
Deselected Cycle,
Power-down
H
H
Deselected Cycle,
Power-down
X
ZZ Mode, Power-Down
X
L
L
L
L
L
X
X
H
H
H
H
H
X
X
L
L
L
L
L
X
H
L
L
L
L
L
L
X
L
X
X
X
L
X
X
X
X
X
X
L
X
X
X
L
X
L
X
Tri-State
Read Cycle, Begin Burst External
Read Cycle, Begin Burst External
Write Cycle, Begin Burst External
Read Cycle, Begin Burst External
Read Cycle, Begin Burst External
L-H
L-H
L-H
L-H
L-H
L-H
Q
L
H
X
L
Tri-State
H
H
H
H
D
L
H
H
H
Q
Tri-State
Q
L
H
L
Read Cycle, Continue
Burst
Next
H
Read Cycle, Continue
Burst
Next
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
X
X
H
X
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
L
H
L
L-H
L-H
L-H
L-H
L-H
L-H
Tri-State
Read Cycle, Continue
Burst
Next
Q
Read Cycle, Continue
Burst
Next
H
X
X
L
Tri-State
Write Cycle, Continue
Burst
Next
D
D
Q
Write Cycle, Continue
Burst
Next
L
Read Cycle, Suspend
Burst
Current
H
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BW , BW , BW , BW and BWE = L or GW = L. WRITE = H when all Byte write enable signals
)
D
A
B
C
(BW , BW , BW , BW BWE, GW = H.
),
A
B
C
D
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks
[A:D]
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05664 Rev. *B
Page 6 of 16
CY7C1219H
Truth Table[2, 3, 4, 5, 6] (continued)
Address
Used CE1 CE2 CE3 ZZ
Operation
ADSP ADSC ADV WRITE OE
CLK
DQ
Read Cycle, Suspend
Burst
Current
Current
Current
Current
Current
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
H
X
X
H
X
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L-H
Tri-State
Read Cycle, Suspend
Burst
L
L-H
L-H
L-H
L-H
Q
Read Cycle, Suspend
Burst
H
X
X
Tri-State
Write Cycle, Suspend
Burst
D
D
Write Cycle, Suspend
Burst
L
Truth Table for Read/Write[2, 3]
Function
Read
GW
BWE
BWA
X
BWB
X
BWC
BWD
X
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
X
X
H
H
H
L
Read
H
H
H
Write byte A - (DQA and DQPA)
Write byte B - (DQBand DQPB)
Write byte C - (DQCand DQPC)
Write byte D - (DQDand DQPD)
Write all bytes
L
H
H
H
L
H
H
H
H
H
H
H
L
L
L
L
L
Write all bytes
X
X
X
X
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
Min.
Max.
Unit
mA
ns
ZZ > VDD − 0.2V
ZZ > VDD − 0.2V
ZZ < 0.2V
40
tZZS
2tCYC
tZZREC
tZZI
2tCYC
0
ns
ZZ Active to sleep current
This parameter is sampled
This parameter is sampled
2tCYC
ns
tRZZI
ZZ inactive to exit sleep current
ns
Document #: 38-05664 Rev. *B
Page 7 of 16
CY7C1219H
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20mA
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883,Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................... –65°C to + 150°
Latch-up Current.....................................................> 200 mA
Ambient Temperature with
Power Applied............................................–55°C to + 125°C
Operating Range
Supply Voltage on VDD Relative to GND....... –0.5V to + 4.6V
Supply Voltage on VDDQ Relative to GND .....–0.5V to + VDD
Ambient
Range
Commercial
Industrial
Temperature (TA)
VDD
VDDQ
DC Voltage Applied to Outputs
in tri-state ............................................ –0.5V to VDDQ + 0.5V
0°C to +70°C
3.3V
−5%/+10%
2.5V −5%
to VDD
–40°C to +85°C
Electrical Characteristics Over the Operating Range[7, 8]
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
Max.
Unit
V
3.135
3.135
2.375
2.4
3.6
VDD
VDDQ
for 3.3V I/O
for 2.5V I/O
V
2.625
V
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[7]
Input LOW Voltage[7]
for 3.3V I/O, IOH = –4.0 mA
for 2.5V I/O, IOH = –1.0 mA
for 3.3V I/O, IOL = 8.0 mA
for 2.5V I/O, IOL = 1.0 mA
for 3.3V I/O
V
2.0
V
0.4
0.4
V
V
2.0
1.7
VDD + 0.3V
V
for 2.5V I/O
V
DD + 0.3V
V
for 3.3V I/O
–0.3
–0.3
–5
0.8
0.7
5
V
for 2.5V I/O
V
Input Leakage Current GND ≤ VI ≤ VDDQ
except ZZ and MODE
µA
Input Current of MODE Input = VSS
Input = VDD
–30
–5
µA
µA
5
Input Current of ZZ
Input = VSS
Input = VDD
µA
30
5
µA
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
VDD Operating Supply VDD = Max., IOUT = 0 mA, 6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
–5
µA
240
225
100
90
mA
mA
mA
mA
Current
f = fMAX = 1/tCYC
ISB1
ISB2
ISB3
Automatic CE
Power-down
Current—TTL Inputs
VDD=Max.,DeviceDeselected, 6-ns cycle, 166 MHz
VIN ≥ VIH or VIN ≤ VIL,
f = fMAX = 1/tCYC
7.5-ns cycle, 133 MHz
Automatic CE
Power-down
Current—CMOS Inputs f = 0
V
DD=Max.,DeviceDeselected, All speeds
40
mA
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
Automatic CE
Power-down
Current—CMOS Inputs VIN > VDDQ – 0.3V,
VDD=Max.,DeviceDeselected, 6-ns cycle, 166 MHz
or VIN ≤ 0.3V or
85
75
mA
mA
7.5-ns cycle, 133 MHz
f = fMAX = 1/tCYC
ISB4
Automatic CE
Power-down
Current—TTL Inputs
VDD=Max.,DeviceDeselected, All speeds
VIN ≥ VIH or VIN ≤ VIL, f = 0
45
mA
Notes:
7. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC)> –2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
.
8. Power-up: Assumes a linear ramp from 0v to V (min.) within 200 ms. During this time V < V and V
< V
DD
IH
DD
DDQ
DD
Document #: 38-05664 Rev. *B
Page 8 of 16
CY7C1219H
Capacitance[9]
100 TQFP
Parameter
Description
Input Capacitance
Test Conditions
Max.
Unit
pF
CIN
TA = 25°C, f = 1 MHz,
5
5
5
VDD = 3.3V
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
pF
VDDQ = 2.5V
pF
Thermal Characteristics[9]
100 TQFP
Package
Parameter
Description
Test Conditions
Test conditions follow standard test methods and proce-
Unit
ΘJA
Thermal Resistance
(Junction to Ambient) dures for measuring thermal impedance, per
30.32
°C/W
EIA/JESD51
ΘJC
Thermal Resistance
(Junction to case)
6.85
°C/W
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
R = 317Ω
3.3V
ALL INPUT PULSES
90%
VDDQ
GND
OUTPUT
90%
10%
Z = 50Ω
0
10%
R = 50Ω
L
5 pF
INCLUDING
R = 351Ω
≤ 1 ns
≤ 1 ns
V = 1.5V
T
(a)
JIG AND
SCOPE
(b)
(c)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
1 ns
5 pF
R =1538Ω
≤
≤ 1 ns
INCLUDING
V = 1.25V
T
JIG AND
SCOPE
(a)
(b)
(c)
Note:
9. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05664 Rev. *B
Page 9 of 16
CY7C1219H
[14,15]
Switching Characteristics Over the Operating Range
166 MHz
133 MHz
Min. Max.
Parameter
tPOWER
Description
VDD(Typical) to the first Access[10]
Min.
Max.
Unit
1
1
ms
Clock
tCYC
Clock Cycle Time
Clock HIGH
6.0
2.5
2.5
7.5
3.0
3.0
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCO
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[11, 12, 13]
3.5
4.0
ns
ns
ns
ns
ns
ns
ns
tDOH
1.5
0
1.5
0
tCLZ
tCHZ
Clock to High-Z[11, 12, 13]
3.5
3.5
4.0
4.0
tOEV
OE LOW to Output Valid
tOELZ
tOEHZ
Set-up Times
tAS
OE LOW to Output Low-Z[11, 12, 13]
OE HIGH to Output High-Z[11, 12, 13]
0
0
3.5
4.0
Address Set-up Before CLK Rise
ADSC, ADSP Set-up Before CLK Rise
ADV Set-up Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
tADS
tADVS
tWES
GW, BWE, BW[A:D] Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
tDS
tCES
Chip Enable Set-up Before CLK Rise
Hold Times
tAH
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tADH
ADSP, ADSC Hold After CLK Rise
ADV Hold After CLK Rise
tADVH
tWEH
GW, BWE, BW[A:D] Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
tDH
tCEH
Notes:
10. This part has a voltage regulator internally; tpower is the time that the power needs to be supplied above V minimum initially before a read or write operation
DD
can be initiated.
11. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.
OEHZ
CHZ CLZ OELZ
12. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
OEHZ
OELZ
CHZ
CLZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
13. This parameter is sampled and not 100% tested.
14. Timing reference level is 1.5V when V
= 3.3V and is 1.25 when V
= 2.5V.
DDQ
DDQ
15. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05664 Rev. *B
Page 10 of 16
CY7C1219H
Switching Waveforms
Read Timing[16]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,BW[A:D]
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
OEV
CO
t
t
CHZ
t
t
t
OELZ
OEHZ
DOH
CLZ
t
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A3)
Q(A1)
Data IOut (Q)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note:
16. On this diagram, when CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document #: 38-05664 Rev. *B
Page 11 of 16
CY7C1219H
Switching Waveforms (continued)
Write Timing[16, 17]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BW[A:D]
t
t
WEH
WES
GW
CE
t
t
CEH
CES
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
DH
DS
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
Data in (D)
t
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Note:
17. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
LOW.
[A:D]
Document #: 38-05664 Rev. *B
Page 12 of 16
CY7C1219H
Switching Waveforms (continued)
Read/Write Timing[16, 18]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE, BW[A:D]
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Back-to-Back READs
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Single WRITE
DON’T CARE
BURST READ
Back-to-Back
WRITEs
UNDEFINED
Note:
18. The data bus (Q) remains in High-Z following a WRITE cycle, unless a new read access initiated by ADSP or ADSP. GW is HIGH.
Document #: 38-05664 Rev. *B
Page 13 of 16
CY7C1219H
Switching Waveforms (continued)
ZZ Mode Timing[19, 20]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
19. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
20. DQs are in High-Z when exiting ZZ sleep mode.
Document #: 38-05664 Rev. *B
Page 14 of 16
CY7C1219H
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
100 CY7C1219H-100AXC
CY7C1219H-100AXI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Commercial
Industrial
133 CY7C1219H-133AXC
CY7C1219H-133AXI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Commercial
Industrial
Package Diagram
100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00 0.20
14.00 0.10
1.40 0.05
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
1. JEDEC STD REF MS-026
0.25
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
A
Intel and Pentium are registered trademarks, and i486 is a trademark, of Intel Corporation. PowerPC is a registered trademark
of IBM. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05664 Rev. *B
Page 15 of 16
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1219H
Document History Page
Document Title: CY7C1219H 1-Mbit (32K x 36) Pipelined DCD Sync SRAM
Document Number: 38-05664
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
343896
430678
See ECN
See ECN
PCI
New Data sheet
*A
NXR
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Added 2.5VI/O option
Changed Three-State to Tri-State
Included Maximum Ratings for VDDQ relative to GND
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Modified test condition from VIH < VDD to VIH < VDD
Replaced Package Name column with Package Diagram in the Ordering
Information table
*B
481916
See ECN
VKN
Converted from Preliminary to Final.
Updated the Ordering Information table.
Document #: 38-05664 Rev. *B
Page 16 of 16
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