CY7C1266KV18 [CYPRESS]
36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); 36兆位的DDR II + SRAM 2字突发架构（ 2.0周期读延迟）
| 型号： | CY7C1266KV18 |
| 厂家： | 
CYPRESS |
| 描述： | 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| 文件： | 总28页 (文件大小：898K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
36-Mbit DDR II+ SRAM 2-Word Burst
Architecture (2.5 Cycle Read Latency)
36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
Features
Configurations
■ 36 Mbit density (4 M × 8, 4 M × 9, 2 M × 18, 1 M × 36)
■ 550 MHz clock for high bandwidth
With Read Cycle Latency of 2.5 Cycles:
CY7C1266KV18 – 4 M × 8
CY7C1277KV18 – 4 M × 9
■ 2-word burst for reducing address bus frequency
CY7C1268KV18 – 2 M × 18
CY7C1270KV18 – 1 M × 36
■ Double data rate (DDR) interfaces
(data transferred at 1100 MHz) at 550 MHz
■ Available in 2.5 clock cycle latency
Functional Description
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
The CY7C1266KV18, CY7C1277KV18, CY7C1268KV18, and
CY7C1270KV18 are 1.8 V synchronous pipelined SRAMs
equipped with DDR II+ architecture. The DDR II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of K and K. Each address location is associated with two 8-bit
words (CY7C1266KV18), 9-bit words (CY7C1277KV18), 18-bit
words (CY7C1268KV18), or 36-bit words (CY7C1270KV18) that
burst sequentially into or out of the device.
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ Synchronous internally self-timed writes
■ DDR II+ operates with 2.5 cycle read latency when DOFF is
asserted HIGH
■ Operatessimilarto DDR Idevice with 1 cycle read latencywhen
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.
DOFF is asserted LOW
[1]
■ Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD
❐ Supports both 1.5 V and 1.8 V I/O supply
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
■ Phase-locked loop (PLL) for accurate data placement
Table 1. Selection Guide
Description
Maximum operating frequency
550 MHz
500 MHz
500
450 MHz
450
400 MHz
400
Unit
MHz
mA
550
690
690
700
890
Maximum operating current
× 8
× 9
640
590
540
640
590
540
× 18
× 36
650
600
550
830
760
690
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V
= 1.4 V to V
.
DD
DDQ
Cypress Semiconductor Corporation
Document Number: 001-57835 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 24, 2011
[+] Feedback
CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
Logic Block Diagram (CY7C1266KV18)
Write
Reg
Write
Reg
21
A
(20:0)
Address
Register
8
LD
K
K
Output
R/W
CLK
Logic
Gen.
Control
DOFF
Read Data Reg.
16
CQ
V
8
REF
8
Reg.
Reg.
Reg.
CQ
Control
Logic
R/W
8
8
NWS
DQ
[1:0]
[7:0]
8
QVLD
Logic Block Diagram (CY7C1277KV18)
Write
Reg
Write
Reg
21
A
(20:0)
Address
Register
9
LD
K
K
Output
Logic
Control
CLK
R/W
Gen.
DOFF
Read Data Reg.
18
CQ
CQ
V
9
REF
9
9
Reg.
Reg.
Reg.
Control
Logic
R/W
9
9
BWS
[0]
DQ
[8:0]
QVLD
Document Number: 001-57835 Rev. *C
Page 2 of 28
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CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
Logic Block Diagram (CY7C1268KV18)
Write
Reg
Write
Reg
20
A
(19:0)
Address
Register
18
LD
K
K
Output
R/W
CLK
Logic
Gen.
Control
DOFF
Read Data Reg.
36
18
CQ
V
REF
18
Reg.
Reg.
Reg.
CQ
Control
Logic
R/W
18
18
BWS
[1:0]
DQ
18
[17:0]
QVLD
Logic Block Diagram (CY7C1270KV18)
Write
Reg
Write
Reg
19
A
(18:0)
Address
Register
36
LD
K
K
Output
Logic
Control
CLK
R/W
Gen.
DOFF
Read Data Reg.
72
36
CQ
CQ
V
REF
36
36
Reg.
Reg.
Reg.
Control
Logic
R/W
36
36
BWS
[3:0]
DQ
[35:0]
QVLD
Document Number: 001-57835 Rev. *C
Page 3 of 28
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CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
Contents
Pin Configuration .............................................................5
165-ball FBGA (13 × 15 × 1.4 mm) pinout ..................5
Pin Definitions ..................................................................7
Functional Overview ........................................................9
Read Operations .........................................................9
Write Operations .........................................................9
Byte Write Operations .................................................9
DDR Operation ............................................................9
Depth Expansion .........................................................9
Programmable Impedance ..........................................9
Echo Clocks ................................................................9
Valid Data Indicator (QVLD) ......................................10
PLL ............................................................................10
Application Example ......................................................10
Truth Table ......................................................................11
Write Cycle Descriptions ...............................................11
Write Cycle Descriptions ...............................................12
Write Cycle Descriptions ...............................................12
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................13
Disabling the JTAG Feature ......................................13
Test Access Port—Test Clock ...................................13
Test Mode Select (TMS) ...........................................13
Test Data-In (TDI) .....................................................13
Test Data-Out (TDO) .................................................13
Performing a TAP Reset ...........................................13
TAP Registers ...........................................................13
TAP Instruction Set ...................................................13
TAP Controller State Diagram .......................................15
TAP Controller Block Diagram ......................................16
TAP Electrical Characteristics ......................................16
TAP AC Switching Characteristics ...............................17
TAP Timing and Test Conditions ..................................17
Identification Register Definitions ................................18
Scan Register Sizes .......................................................18
Instruction Codes ...........................................................18
Boundary Scan Order ....................................................19
Power Up Sequence in DDR II+ SRAM .........................20
Power Up Sequence .................................................20
PLL Constraints .........................................................20
Maximum Ratings ...........................................................21
Operating Range .............................................................21
Neutron Soft Error Immunity .........................................21
Electrical Characteristics ...............................................21
DC Electrical Characteristics .....................................21
AC Electrical Characteristics .....................................23
Capacitance ....................................................................23
Thermal Resistance ........................................................23
Switching Characteristics ..............................................24
Switching Waveforms ....................................................25
Read/Write/Deselect Sequence ................................25
Ordering Information ......................................................26
Ordering Code Definitions .........................................26
Package Diagram ............................................................27
Document History Page .................................................28
Sales, Solutions, and Legal Information ......................28
Worldwide Sales and Design Support .......................28
Products ....................................................................28
PSoC Solutions .........................................................28
Document Number: 001-57835 Rev. *C
Page 4 of 28
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CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
Pin Configuration
The pin configurations for CY7C1266KV18, CY7C1277KV18, CY7C1268KV18, and CY7C1270KV18 follow. [2]
165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1266KV18 (4 M × 8)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/72M
NC
3
A
4
5
NWS1
NC/288M
A
6
K
7
NC/144M
NWS0
A
8
9
A
10
A
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
A
B
C
D
E
F
R/W
A
LD
NC
NC
NC
DQ4
NC
DQ5
VDDQ
NC
NC
NC
NC
NC
DQ7
A
K
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
NC
NC
NC
NC
NC
VREF
DQ1
NC
NC
NC
NC
NC
TMS
NC
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
NC
NC
G
H
J
NC
VREF
NC
NC
NC
DQ0
NC
NC
NC
TDI
K
L
NC
DQ6
NC
M
N
P
R
NC
NC
A
QVLD
NC
A
TCK
A
A
A
A
CY7C1277KV18 (4 M × 9)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/72M
NC
3
A
4
5
NC
6
K
7
NC/144M
BWS0
A
8
9
A
10
A
11
CQ
DQ3
NC
A
B
C
D
E
F
R/W
A
LD
NC
NC
NC
DQ4
NC
DQ5
VDDQ
NC
NC
NC
NC
NC
DQ7
A
NC/288M
A
K
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
NC
NC
NC
NC
NC
VREF
DQ1
NC
NC
NC
NC
NC
TMS
NC
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
NC
NC
DQ2
NC
NC
G
H
J
NC
NC
VREF
NC
ZQ
NC
K
L
NC
NC
DQ6
NC
DQ0
NC
M
N
P
R
NC
NC
NC
A
QVLD
NC
A
DQ8
TDI
TCK
A
A
A
A
Note
2. NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-57835 Rev. *C
Page 5 of 28
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CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
Pin Configuration (continued)
The pin configurations for CY7C1266KV18, CY7C1277KV18, CY7C1268KV18, and CY7C1270KV18 follow. [2]
165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1268KV18 (2 M × 18)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/72M
DQ9
NC
3
4
5
BWS1
NC/288M
A
6
K
7
NC/144M
BWS0
A
8
9
A
10
A
11
CQ
A
B
C
D
E
F
A
R/W
A
LD
NC
K
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
DQ8
NC
NC
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
DQ7
NC
NC
DQ10
DQ11
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
NC
NC
NC
DQ6
DQ5
NC
DQ12
NC
NC
G
H
J
DQ13
VDDQ
NC
NC
VREF
NC
VREF
DQ4
NC
ZQ
NC
K
L
NC
DQ14
NC
DQ3
DQ2
NC
DQ15
NC
NC
M
N
P
R
NC
DQ1
NC
NC
DQ16
DQ17
A
NC
NC
A
QVLD
NC
A
NC
DQ0
TDI
TCK
A
A
A
A
TMS
CY7C1270KV18 (1 M × 36)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/144M
DQ27
NC
3
4
5
BWS2
BWS3
A
6
K
7
BWS1
BWS0
A
8
9
A
10
NC/72M
NC
11
A
B
C
D
E
F
A
R/W
A
LD
CQ
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
VDDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
A
K
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
DQ17
NC
DQ29
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
DQ15
NC
DQ30
DQ31
VREF
NC
G
H
J
NC
VREF
DQ13
DQ12
NC
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
K
L
NC
DQ33
NC
M
N
P
R
DQ11
NC
DQ35
NC
A
QVLD
NC
A
DQ9
TMS
TCK
A
A
A
A
Document Number: 001-57835 Rev. *C
Page 6 of 28
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CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
Pin Definitions
Pin Name
I/O
Pin Description
DQ[x:0]
Input output- Data input output signals. Inputs are sampled on the rising edge of K and K clocks during valid write
synchronous operations. These pins drive out the requested data when the read operation is active. Valid data is driven
out on the rising edge of both the K and K clocks during read operations. When read access is deselected,
Q[x:0] are automatically tristated.
CY7C1266KV18 DQ[7:0]
CY7C1277KV18 DQ[8:0]
CY7C1268KV18 DQ[17:0]
CY7C1270KV18 DQ[35:0]
LD
Input-
Synchronous load. Sampled on the rising edge of the K clock. This input is brought LOW when a bus
synchronous cycle sequence is defined. This definition includes address and read/write direction. All transactions
operate on a burst of 2 data. LD must meet the setup and hold times around edge of K.
Input-
Nibble write select 0, 1 active LOW (CY7C1266KV18 only). Sampled on the rising edge of the K and
NWS0,
NWS1
synchronous K clocks during write operations. Used to select which nibble is written into the device during the current
portion of the write operations. Nibbles not written remain unaltered.
NWS0 controls D[3:0] and NWS1 controls D[7:4]
.
All the nibble write selects are sampled on the same edge as the data. Deselecting a nibble write select
ignores the corresponding nibble of data and it is not written into the device.
BWS0,
BWS1,
BWS2,
BWS3
Input-
Byte write select 0, 1, 2, and 3 active LOW. Sampled on the rising edge of the K and K clocks during
synchronous write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1277KV18 BWS0 controls D[8:0]
CY7C1268KV18 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1270KV18 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls
D[35:27]
.
All the byte write selects are sampled on the same edge as the data. Deselecting a byte write select
ignores the corresponding byte of data and it is not written into the device.
A
Input-
Address inputs. Sampled on the rising edge of the K clock during active read and write operations. These
synchronous address inputs are multiplexed for both read and write operations. Internally, the device is organized as
4 M × 8 (2 arrays each of 2 M × 8) for CY7C1266KV18 and 4 M × 9 (2 arrays each of 2 M ×9) for
CY7C1277KV18, 2 M × 18 (2 arrays each of 1 M × 18) for CY7C1268KV18, and 1 M × 36 (2 arrays each
of 512 K × 36) for CY7C1270KV18.
R/W
Input-
Synchronous read or write input. When LD is LOW, this input designates the access type (read when
synchronous R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times
around edge of K.
QVLD
K
Valid output Valid output indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
indicator
Input clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device and
to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.
Input clock Negative input clock input. K is used to capture synchronous data being presented to the device and
K
to drive out data through Q[x:0]
.
CQ
Echo clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock
(K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 24.
Echo clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock
CQ
ZQ
(K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 24.
Input
Output impedance matching input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
Document Number: 001-57835 Rev. *C
Page 7 of 28
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CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
Pin Definitions (continued)
Pin Name
I/O
Pin Description
DOFF
Input
PLL turn off active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing
in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
can be connected to a pull-up through a 10 K or less pull-up resistor. The device behaves in DDR I
mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with DDR I timing.
TDO
Output
Input
Input
Input
N/A
TDO for JTAG
TCK
TCK pin for JTAG
TDI
TDI pin for JTAG
TMS
TMS pin for JTAG
NC
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
NC/72M
NC/144M
NC/288M
VREF
Input
Input
Input
Input-
Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC
reference
measurement points.
VDD
VSS
Power supply Power supply inputs to the core of the device
Ground Ground for the device
Power supply Power supply inputs for the outputs of the device
VDDQ
Document Number: 001-57835 Rev. *C
Page 8 of 28
[+] Feedback
CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
When the write access is deselected, the device ignores all
inputs after the pending write operations have been completed.
Functional Overview
The CY7C1266KV18, CY7C1277KV18, CY7C1268KV18, and
CY7C1270KV18 are synchronous pipelined burst SRAMs
equipped with a DDR interface, which operates with a read
latency of two and half cycles when DOFF pin is tied HIGH.
When DOFF pin is set LOW or connected to VSS the device
behaves in DDR I mode with a read latency of one clock cycle.
Byte Write Operations
Byte write operations are supported by the CY7C1268KV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS1, which are sampled with each set of 18-bit data words.
Asserting the appropriate byte write select input during the data
portion of a write latches the data being presented and writes it
into the device. Deasserting the byte write select input during the
data portion of a write enables the data stored in the device for
that byte to remain unaltered. This feature can be used to
simplify read, modify, or write operations to a byte write
operation.
Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input and output timing is referenced
from the rising edge of the input clocks (K and K).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the rising edge of the input clocks (K and K). All
synchronous data outputs (Q[x:0]) pass through output registers
controlled by the rising edge of the input clocks (K and K).
DDR Operation
All synchronous control (R/W, LD, NWS[X:0], BWS[X:0]) inputs
pass through input registers controlled by the rising edge of the
input clock (K).
The CY7C1268KV18 enables high performance operation
through high clock frequencies (achieved through pipelining) and
DDR mode of operation. The CY7C1268KV18 requires two No
Operation (NOP) cycle during transition from a read to a write
cycle. At higher frequencies, some applications require third
NOP cycle to avoid contention.
CY7C1268KV18 is described in the following sections. The
same basic descriptions apply to CY7C1266KV18,
CY7C1277KV18, and CY7C1270KV18.
Read Operations
If a read occurs after a write cycle, address and data for the write
are stored in registers. The write information is stored because
the SRAM cannot perform the last word write to the array without
conflicting with the read. The data stays in this register until the
next write cycle occurs. On the first write cycle after the read(s),
the stored data from the earlier write is written into the SRAM
array. This is called a posted write.
The CY7C1268KV18 is organized internally as two arrays of
1 M x 18. Accesses are completed in a burst of 2 sequential
18-bit data words. Read operations are initiated by asserting
R/W HIGH and LD LOW at the rising edge of the positive input
clock (K). The address presented to the address inputs is stored
in the read address register. Following the next two K clock rise,
the corresponding 18-bit word of data from this address location
is driven onto the Q[17:0] using K as the output timing reference.
On the subsequent rising edge of K, the next 18-bit data word is
driven onto the Q[17:0]. The requested data is valid 0.45 ns from
the rising edge of the input clock (K and K). To maintain the
internal logic, each read access must be allowed to complete.
Read accesses can be initiated on every rising edge of the
positive input clock (K).
If a read is performed on the same address on which a write is
performed in the previous cycle, the SRAM reads out the most
current data. The SRAM does this by bypassing the memory
array and reading the data from the registers.
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
When read access is deselected, the CY7C1268KV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tristates the output following the next rising
edge of the negative input clock (K). This enables for a transition
between devices without the insertion of wait states in a depth
expanded memory.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5 × the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175 and 350 , with VDDQ = 1.5 V. The
output impedance is adjusted every 1024 cycles upon power-up
to account for drifts in supply voltage and temperature.
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to address inputs is stored in the write
address register. On the following K clock rise, the data
presented to D[17:0] is latched and stored into the 18-bit write
data register, provided BWS[1:0] are both asserted active. On the
subsequent rising edge of the negative input clock (K) the
information presented to D[17:0] is also stored into the write data
register, provided BWS[1:0] are both asserted active. The 36 bits
of data are then written into the memory array at the specified
location. Write accesses can be initiated on every rising edge of
the positive input clock (K). Doing so pipelines the data flow such
that 18 bits of data can be transferred into the device on every
rising edge of the input clocks (K and K).
Echo Clocks
Echo clocks are provided on the DDR II+ to simplify data capture
on high speed systems. Two echo clocks are generated by the
DDR II+. CQ is referenced with respect to K and CQ is
referenced with respect to K. These are free-running clocks and
are synchronized to the input clock of the DDR II+. The timing for
the echo clocks is shown in the “Switching Characteristics” on
page 24.
Document Number: 001-57835 Rev. *C
Page 9 of 28
[+] Feedback
CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
20 s of stable clock. The PLL can also be reset by slowing or
stopping the input clock K and K for a minimum of 30 ns.
However, it is not necessary to reset the PLL to lock to the
desired frequency. The PLL automatically locks 20 s after a
stable clock is presented. The PLL may be disabled by applying
ground to the DOFF pin. When the PLL is turned off, the device
behaves in DDR I mode (with one cycle latency and a longer
access time). For information, refer to the application note, PLL
Considerations in QDRII/DDRII/QDRII+/DDRII+.
Valid Data Indicator (QVLD)
QVLD is provided on the DDR II+ to simplify data capture on high
speed systems. The QVLD is generated by the DDR II+ device
along with data output. This signal is also edge aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
PLL
These chips use a PLL that is designed to function between
120 MHz and the specified maximum clock frequency. During
power up, when the DOFF is tied HIGH, the PLL is locked after
Application Example
Figure 1 shows two DDR II+ used in an application.
Figure 1. Application Example
R = 250ohms
R = 250ohms
ZQ
SRAM#1
ZQ
CQ/CQ
K
K
SRAM#2
DQ
A
DQ
A
CQ/CQ
R/W BWS
LD
K
R/W BWS
K
LD
DQ
Addresses
LD
BUS
MASTER
R/W
BWS
(CPU or ASIC)
Source CLK
Source CLK
Echo Clock1/Echo Clock1
Echo Clock2/Echo Clock2
Document Number: 001-57835 Rev. *C
Page 10 of 28
[+] Feedback
CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
Truth Table
The truth table for the CY7C1266KV18, CY7C1277KV18, CY7C1268KV18, and CY7C1270KV18 follows. [3, 4, 5, 6, 7, 8]
Operation
K
LD
R/W
DQ
DQ
Write cycle:
Load address; wait one cycle;
L–H
L
L
D(A) at K(t + 1) D(A+1) at K(t + 1)
input write data on consecutive K and K rising edges.
Read cycle: (2.5 cycle Latency)
Load address; wait two and half cycles;
read data on consecutive K and K rising edges.
L–H
L
H
Q(A) at K(t + 2)
Q(A+1) at K(t + 3)
NOP: No operation
L–H
H
X
X
X
High Z
High Z
Standby: Clock stopped
Stopped
Previous state
Previous state
Write Cycle Descriptions
The write cycle description table for CY7C1266KV18 and CY7C1268KV18 follows. [3, 9]
BWS0/ BWS1/
K
Comments
K
NWS0 NWS1
L
L
L
L
L–H
–
During the data portion of a write sequence
CY7C1266KV18 both nibbles (D[7:0]) are written into the device.
CY7C1268KV18 both bytes (D[17:0]) are written into the device.
–
L–H
–
L–H During the data portion of a write sequence
CY7C1266KV18 both nibbles (D[7:0]) are written into the device.
CY7C1268KV18 both bytes (D[17:0]) are written into the device.
L
H
H
L
–
During the data portion of a write sequence
CY7C1266KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1268KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L
L–H During the data portion of a write sequence
CY7C1266KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1268KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H
H
L–H
–
–
During the data portion of a write sequence
CY7C1266KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1268KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
L
L–H During the data portion of a write sequence
CY7C1266KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1268KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
H
H
H
L–H
–
–
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
Notes
3. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
4. Device powers up deselected with the outputs in a tri-state condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the address sequence in the burst.
6. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well.
8. Ensure that when clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
9. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS , NWS , BWS , BWS , BWS , and BWS can be altered on
0
1
0
1
2
3
different portions of a write cycle, as long as the setup and hold requirements are achieved.
Document Number: 001-57835 Rev. *C
Page 11 of 28
[+] Feedback
CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
Write Cycle Descriptions
The write cycle description table for CY7C1277KV18 follows. [10, 11]
BWS0
K
L–H
–
K
Comments
During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
L
L
–
L–H During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
H
H
L–H
–
–
Write Cycle Descriptions
The write cycle description table for CY7C1270KV18 follows. [10, 11]
BWS0 BWS1 BWS2 BWS3
K
K
Comments
L
L
L
L
L–H
–
During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
–
L–H
–
L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
–
During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L
L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H
H
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H
H
H
H
H
H
H
H
L–H
–
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Notes
10. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
11. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS , NWS , BWS , BWS , BWS , and BWS can be altered on
0
1
0
1
2
3
different portions of a write cycle, as long as the setup and hold requirements are achieved.
Document Number: 001-57835 Rev. *C
Page 12 of 28
[+] Feedback
CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
Instruction Register
IEEE 1149.1 Serial Boundary Scan (JTAG)
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in TAP Controller Block Diagram on
page 16. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-2001. The TAP operates using JEDEC
standard 1.8 V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternatively be connected to VDD through a pull-up resistor. TDO
must be left unconnected. Upon power-up, the device comes up
in a reset state, which does not interfere with the operation of the
device.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information about
loading the instruction register, see the TAP Controller State
Diagram on page 15. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
The Boundary Scan Order on page 19 shows the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
Test Data-Out (TDO)
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 18.
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 18).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
TAP Instruction Set
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
SRAM and can be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a high Z state.
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 18. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
TAP Registers
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Document Number: 001-57835 Rev. *C
Page 13 of 28
[+] Feedback
CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
IDCODE
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-Reset state.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a high Z state until the next command is supplied during the
Update IR state.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
EXTEST OUTPUT BUS TRISTATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
The boundary scan register has a special bit located at bit #108.
When this scan cell, called the “extest output bus tristate,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
high Z condition.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 001-57835 Rev. *C
Page 14 of 28
[+] Feedback
CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
TAP Controller State Diagram
The state diagram for the TAP controller follows. [12]
TEST-LOGIC
1
RESET
0
1
1
1
SELECT
TEST-LOGIC/
SELECT
0
IR-SCAN
IDLE
DR-SCAN
0
0
1
1
CAPTURE-DR
0
CAPTURE-IR
0
0
1
0
1
SHIFT-DR
1
SHIFT-IR
1
EXIT1-DR
0
EXIT1-IR
0
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-IR
0
UPDATE-DR
1
1
0
Note
12. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-57835 Rev. *C
Page 15 of 28
[+] Feedback
CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
TAP Controller Block Diagram
0
Bypass Register
2
1
1
1
0
0
0
Selection
TDI
Selection
Circuitry
TDO
Instruction Register
Circuitry
31 30
29
.
.
2
Identification Register
.
108
.
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics
Over the Operating Range [13, 14, 15]
Parameter
VOH1
Description
Test Conditions
IOH =2.0 mA
IOH =100 A
IOL = 2.0 mA
Min
1.4
1.6
–
Max
–
Unit
Output HIGH voltage
Output HIGH voltage
Output LOW voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
V
V
VOH2
VOL1
VOL2
VIH
–
0.4
0.2
V
IOL = 100 A
–
V
0.65 VDD VDD + 0.3
V
VIL
–0.3
–5
0.35 VDD
5
V
IX
Input and output load current
GND VI VDD
A
Notes
13. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
14. Overshoot: V (AC) < V + 0.3 V (Pulse width less than t /2).
/2), Undershoot: V (AC) > 0.3 V (Pulse width less than t
IH
DDQ
CYC
IL
CYC
15. All voltage referenced to ground.
Document Number: 001-57835 Rev. *C
Page 16 of 28
[+] Feedback
CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
TAP AC Switching Characteristics
Over the Operating Range [16, 17]
Parameter
Description
Min
50
–
Max
–
Unit
ns
tTCYC
TCK clock cycle time
TCK clock frequency
TCK clock HIGH
tTF
20
–
MHz
ns
tTH
20
20
tTL
TCK clock LOW
–
ns
Setup Times
tTMSS
tTDIS
TMS set-up to TCK clock rise
TDI set-up to TCK clock rise
Capture set-up to TCK rise
5
5
5
–
–
–
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS hold after TCK clock rise
TDI hold after clock rise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture hold after clock rise
Output Times
tTDOV
tTDOX
TCK clock LOW to TDO valid
TCK clock LOW to TDO invalid
–
0
10
–
ns
ns
TAP Timing and Test Conditions
Figure 2 shows the TAP timing and test conditions. [17]
Figure 2. TAP Timing and Test Conditions
0.9V
ALL INPUT PULSES
1.8V
50
0.9V
TDO
0V
Z = 50
0
C = 20 pF
L
tTL
tTH
GND
(a)
Test Clock
TCK
tTCYC
tTMSH
tTMSS
Test Mode Select
TMS
tTDIS
tTDIH
Test Data In
TDI
Test Data Out
TDO
tTDOV
tTDOX
Notes
16. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
17. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.
R
F
Document Number: 001-57835 Rev. *C
Page 17 of 28
[+] Feedback
CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
Identification Register Definitions
Value
Instruction Field
Description
CY7C1266KV18
CY7C1277KV18
000
CY7C1268KV18
000
CY7C1270KV18
Revision number
(31:29)
000
000
Version number.
Cypress device ID 11010111000000111 11010111000001111 11010111000010111 11010111000100111 Defines the type of
(28:12)
SRAM.
Cypress JEDEC ID
(11:1)
00000110100
1
00000110100
1
00000110100
1
00000110100
1
Allows unique
identification of
SRAM vendor.
ID register
presence (0)
Indicates the
presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size
Instruction
Bypass
3
1
ID
32
109
Boundary scan
Instruction Codes
Instruction
EXTEST
Code
000
Description
Captures the input and output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the boundary scan register between TDI
and TDO. Forces all SRAM output drivers to a high Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the input and output ring contents. Places the boundary scan register between
TDI and TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 001-57835 Rev. *C
Page 18 of 28
[+] Feedback
CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
Boundary Scan Order
Bit #
0
Bump ID
6R
Bit #
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
Bump ID
10G
9G
Bit #
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
Bump ID
6A
5B
5A
4A
5C
4B
3A
2A
1A
2B
3B
1C
1B
3D
3C
1D
2C
3E
2D
2E
1E
2F
Bit #
84
Bump ID
1J
1
6P
85
2J
2
6N
11F
11G
9F
86
3K
3
7P
87
3J
4
7N
88
2K
5
7R
10F
11E
10E
10D
9E
89
1K
6
8R
90
2L
7
8P
91
3L
8
9R
92
1M
1L
9
11P
10P
10N
9P
93
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
10C
11D
9C
94
3N
95
3M
1N
96
10M
11N
9M
9D
97
2M
3P
11B
11C
9B
98
99
2N
9N
100
101
102
103
104
105
106
107
108
2P
11L
11M
9L
10B
11A
10A
9A
1P
3R
4R
10L
11K
10K
9J
4P
8B
5P
7C
3F
5N
6C
1G
1F
5R
9K
8A
Internal
10J
11J
11H
7A
3G
2G
1H
7B
6B
Document Number: 001-57835 Rev. *C
Page 19 of 28
[+] Feedback
CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
PLL Constraints
Power Up Sequence in DDR II+ SRAM
■ PLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var
DDR II+ SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
.
■ The PLL functions at frequencies down to 120 MHz.
Power Up Sequence
■ If the input clock is unstable and the PLL is enabled, then the
PLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 20 s of stable clock to
relock to the desired clock frequency.
■ Apply power and drive DOFF either HIGH or LOW (All other
inputs can be HIGH or LOW).
❐ Apply VDD before VDDQ
.
❐ Apply VDDQ before VREF or at the same time as VREF
.
❐ Drive DOFF HIGH.
■ Provide stable DOFF (HIGH), power and clock (K, K) for 20 s
to lock the PLL.
Figure 3. Power Up Waveforms
K
K
Unstable Clock
> 20Ps Stable clock
Stable)
DDQ
Start Normal
Operation
/
V
Clock Start (Clock Starts after V
DD
Stable (< +/- 0.1V DC per 50ns )
/
/
V
VDDQ
V
VDD
DD
DDQ
Fix HIGH (or tie to V
)
DDQ
DOFF
Document Number: 001-57835 Rev. *C
Page 20 of 28
[+] Feedback
CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
Maximum Ratings
Neutron Soft Error Immunity
Test
Conditions
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Parameter Description
Typ Max* Unit
LSBU
LMBU
SEL
Logical
single-bit
upsets
25 °C
197
216
0.01
0.1
FIT/
Mb
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with power applied . –55 °C to +125 °C
Supply voltage on VDD relative to GND........–0.5 V to +2.9 V
Supply voltage on VDDQ relative to GND....... –0.5 V to +VDD
DC applied to outputs in high Z .........–0.5 V to VDDQ + 0.3 V
DC input voltage [18] ............................–0.5 V to VDD + 0.3 V
Current into outputs (LOW) ......................................... 20 mA
Static discharge voltage (MIL-STD-883, M 3015).. > 2,001 V
Latch-up current .................................................... > 200 mA
Logical
multi-bit
upsets
25 °C
85 °C
0
FIT/
Mb
Single event
latch-up
0
FIT/
Dev
* No LMBU or SEL events occurred during testing; this column
2
represents a statistical , 95% confidence limit calculation. For
more details refer to Application Note AN 54908 “Accelerated
Neutron SER Testing and Calculation of Terrestrial Failure Rates”
Operating Range
Ambient
Temperature (TA)
[19]
[19]
Range
VDD
VDDQ
Commercial
Industrial
0 °C to +70 °C
1.8 ± 0.1 V 1.4 V to
VDD
–40 °C to +85 °C
Electrical Characteristics
DC Electrical Characteristics
Over the Operating Range [20]
Parameter
VDD
Description
Power supply voltage
I/O supply voltage
Test Conditions
Min
1.7
Typ
1.8
1.5
–
Max
Unit
V
1.9
VDDQ
VOH
1.4
VDD
VDDQ/2 + 0.12
VDDQ/2 + 0.12
VDDQ
V
Output HIGH voltage
Output LOW voltage
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Input leakage current
Output leakage current
Note 21
VDDQ/2 – 0.12
VDDQ/2 – 0.12
VDDQ – 0.2
VSS
V
VOL
Note 22
–
V
VOH(LOW)
VOL(LOW)
VIH
IOH =0.1 mA, nominal impedance
IOL = 0.1 mA, nominal impedance
–
V
–
0.2
V
VREF + 0.1
–0.15
–
VDDQ + 0.15
VREF – 0.1
2
V
VIL
–
V
IX
GND VI VDDQ
2
–
A
A
V
IOZ
GND VI VDDQ, output disabled
2
–
2
VREF
Input reference voltage [23] Typical value = 0.75 V
0.68
0.75
0.95
Notes
18. Overshoot: V (AC) < V
19. Power-up: assumes a linear ramp from 0 V to V (min) within 200 ms. During this time V < V and V
+ 0.3 V (Pulse width less than t
/2), Undershoot: V (AC) > 0.3 V (Pulse width less than t
/2).
CYC
IH
DDQ
CYC
IL
< V
.
DD
DD
IH
DD
DDQ
20. All voltage referenced to ground.
21. Outputs are impedance controlled. I = –(V
/2)/(RQ/5) for values of 175 < RQ < 350 .
OH
DDQ
22. Outputs are impedance controlled. I = (V
/2)/(RQ/5) for values of 175 < RQ < 350 .
OL
DDQ
23. V
(min) = 0.68 V or 0.46 V
, whichever is larger, V
(max) = 0.95 V or 0.54 V
, whichever is smaller.
REF
DDQ
REF
DDQ
Document Number: 001-57835 Rev. *C
Page 21 of 28
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CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
Electrical Characteristics (continued)
DC Electrical Characteristics
Over the Operating Range [20]
Parameter
Description
Test Conditions
Min
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max
690
690
700
890
640
640
650
830
590
590
600
760
540
540
550
690
360
360
360
360
340
340
340
340
330
330
330
330
310
310
310
310
Unit
[24]
VDD operating supply
VDD = Max, IOUT = 0 mA, 550 MHz (× 8)
f = fMAX = 1/tCYC
mA
IDD
(× 9)
(× 18)
(× 36)
500 MHz (× 8)
(× 9)
mA
mA
mA
mA
mA
mA
mA
(× 18)
(× 36)
450 MHz (× 8)
(× 9)
(× 18)
(× 36)
400 MHz (× 8)
(× 9)
(× 18)
(× 36)
ISB1
Automatic power-down
current
Max VDD
,
550 MHz (× 8)
(× 9)
both ports deselected,
VIN VIH or VIN VIL
f = fMAX = 1/tCYC
inputs static
,
(× 18)
(× 36)
500 MHz (× 8)
(× 9)
(× 18)
(× 36)
450 MHz (× 8)
(× 9)
(× 18)
(× 36)
400 MHz (× 8)
(× 9)
(× 18)
(× 36)
Note
24. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-57835 Rev. *C
Page 22 of 28
[+] Feedback
CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
AC Electrical Characteristics
Over the Operating Range [25]
Parameter
Description
Input HIGH voltage
Input LOW voltage
Test Conditions
Min
VREF + 0.2
–0.24
Typ
–
Max
Unit
V
VIH
VIL
VDDQ + 0.24
VREF – 0.2
–
V
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
Input capacitance
Output capacitance
Test Conditions
TA = 25 C, f = 1 MHz, VDD = 1.8 V, VDDQ = 1.5 V
Max
4
Unit
pF
CIN
CO
4
pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
165 FBGA
Package
Parameter
Description
Thermal resistance
Test Conditions
Unit
JA
Test conditions follow standard test methods and procedures
for measuring thermal impedance, in accordance with
EIA/JESD51.
13.7
°C/W
(junction to ambient)
JC
Thermal resistance
(junction to case)
3.73
°C/W
Figure 4. AC Test Loads and Waveforms
VREF = 0.75 V
0.75 V
VREF
VREF
0.75 V
R = 50
OUTPUT
[26]
ALL INPUT PULSES
1.25 V
Z = 50
0
OUTPUT
Device
Under
Test
R = 50
L
0.75 V
Device
Under
0.25 V
5 pF
VREF = 0.75 V
Slew Rate = 2 V/ns
ZQ
Test
ZQ
RQ =
RQ =
250
(b)
250
INCLUDING
JIG AND
SCOPE
(a)
Notes
25. Overshoot: V (AC) < V
+ 0.3 V (Pulse width less than t
/2), Undershoot: V (AC) > 0.3 V (Pulse width less than t
/2).
CYC
= 0.75 V, RQ = 250 , V
IH
DDQ
CYC
IL
26. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75 V, V
= 1.5 V, input pulse
DDQ
REF
levels of 0.25 V to 1.25 V, and output loading of the specified I /I and load capacitance shown in (a) of AC Test Loads and Waveforms.
OL OH
Document Number: 001-57835 Rev. *C
Page 23 of 28
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CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
Switching Characteristics
Over the Operating Range [27, 28]
550 MHz
500 MHz
450 MHz
400 MHz
Cypress Consortium
Parameter Parameter
Description
Unit
Min Max Min Max Min Max Min Max
tPOWER
tCYC
tKH
VDD(typical) to the first access [29]
K clock cycle time
1
–
1
–
1
–
1
–
ms
ns
ns
ns
ns
tKHKH
tKHKL
tKLKH
tKHKH
1.81 8.4 2.0 8.4 2.2 8.4 2.5 8.4
Input clock (K/K) HIGH
Input clock (K/K) LOW
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
tKL
tKHKH
K clock rise to K clock rise
(rising edge to rising edge)
0.77
0.85
0.94
1.06
Setup Times
tSA
tAVKH
tIVKH
tIVKH
Address set-up to K clock rise
0.23
0.23
–
–
–
0.25
0.25
0.20
–
–
–
0.275
0.275
0.22
–
–
–
0.4
0.4
–
–
–
ns
ns
ns
tSC
Control set-up to K clock rise (LD, R/W)
tSCDDR
Double data rate control set-up to clock (K/K) rise 0.18
(BWS0, BWS1, BWS2, BWS3)
0.28
tSD
tDVKH
D[X:0] set-up to clock (K/K) rise
0.18
–
0.20
–
0.22
–
0.28
–
ns
Hold Times
tHA
tKHAX
tKHIX
tKHIX
Address hold after K clock rise
0.23
0.23
0.18
–
–
–
0.25
0.25
0.20
–
–
–
0.275
0.275
0.22
–
–
–
0.4
0.4
–
–
–
ns
ns
ns
tHC
Control hold after K clock rise (LD, R/W)
tHCDDR
Double data rate control hold after clock (K/K)
rise (BWS0, BWS1, BWS2, BWS3)
0.28
tHD
tKHDX
D[X:0] hold after clock (K/K) rise
0.18
–
0.20
–
0.22
–
0.28
–
ns
Output Times
tCO
tCHQV
K/K clock rise to data valid
–
0.45
–
–
0.45
–
–
0.45
–
–
0.45
–
ns
ns
tDOH
tCHQX
Data output hold after output K/K clock rise
(active to active)
–0.45
–0.45
–0.45
–0.45
tCCQO
tCQOH
tCQD
tCHCQV
tCHCQX
tCQHQV
tCQHQX
tCQHCQL
K/K clock rise to echo clock valid
Echo clock hold after K/K clock rise
Echo clock high to data valid
–
0.45
–
–
0.45
–
–
0.45
–
–
0.45
–
ns
ns
ns
ns
ns
ns
–0.45
–
–0.45
–
–0.45
–
–0.45
–
0.15
–
0.15
–
0.15
–
0.20
–
tCQDOH
tCQH
Echo clock high to data invalid
Output clock (CQ/CQ) HIGH [30]
–0.15
0.655
0.655
–0.15
0.75
0.75
–0.15
0.85
0.85
–0.20
1.00
1.00
–
–
–
–
tCQHCQH tCQHCQH
CQ clock rise to CQ clock rise
–
–
–
–
(rising edge to rising edge) [30]
tCHZ
tCLZ
tCHQZ
Clock (K/K) rise to high Z (active to high Z) [31, 32]
Clock (K/K) rise to low Z [31, 32]
Echo clock high to QVLD valid [33]
–
0.45
–
–
0.45
–
–
0.45
–
–
0.45
–
ns
ns
ns
tCHQX1
tCQHQVLD
–0.45
–0.45
–0.45
–0.45
tQVLD
–0.15 0.15 –0.15 0.15 –0.15 0.15 –0.20 0.20
PLL Timing
tKC Var tKC Var
tKC lock tKC lock
Clock phase jitter
–
0.15
–
–
0.15
–
–
0.15
–
–
0.20
–
ns
s
ns
PLL lock time (K)
K static to PLL reset [34]
20
30
20
30
20
30
20
30
tKC Reset tKC Reset
–
–
–
–
Notes
27. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75 V, V
= 0.75 V, RQ = 250 , V
= 1.5 V, input pulse
DDQ
REF
levels of 0.25 V to 1.25 V, and output loading of the specified I /I and load capacitance shown in (a) of AC Test Loads and Waveforms.
OL OH
28. When a part with a maximum frequency above 400 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
29. This part has an internal voltage regulator; t
is the time that the power is supplied above V min initially before a read or write operation can be initiated.
DD
POWER
30. These parameters are extrapolated from the input timing parameters (t
/2 - 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
CYC
design and are not tested in production.
31. t
, t
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured 100 mV from steady-state voltage.
CHZ CLZ
32. At any voltage and temperature t
is less than t
and t
less than t
.
CHZ
CLZ
CHZ
CO
33. t
specification is applicable for both rising and falling edges of QVLD signal.
QVLD
34. Hold to >V or <V .
IH
IL
Document Number: 001-57835 Rev. *C
Page 24 of 28
[+] Feedback
CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
Switching Waveforms
Read/Write/Deselect Sequence [35, 36, 37]
Figure 5. Waveform for 2.5 Cycle Read Latency
NOP
1
READ
2
READ
3
NOP
5
NOP
6
WRITE
7
WRITE
8
NOP
11
NOP
4
READ
9
NOP
10
12
K
t
t
t
t
KH
KL
KHKH
CYC
K
LD
t
t
HC
SC
R/W
A
A2
A3
A0
A4
A1
t
QVLD
t
t
t
t
SA HA
QVLD
QVLD
QVLD
t
t
HD
HD
SD
t
t
SD
D21 D30 D31
Q00 Q01 Q10 Q11
D20
Q40
DQ
t
t
DOH
t
CHZ
CLZ
t
t
t
CO
CQD
(Read Latency = 2.5 Cycles)
t
CQDOH
CCQO
CQOH
t
CQ
CQ
t
CQH
t
CQHCQH
t
CCQO
t
CQOH
DON’T CARE
UNDEFINED
Notes
35. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
36. Outputs are disabled (high Z) one clock cycle after a NOP.
37. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document Number: 001-57835 Rev. *C
Page 25 of 28
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CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
Ordering Information
The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
400 CY7C1270KV18-400BZXI
CY7C1268KV18-400BZC
51-85180 165-ball Fine Pitch Ball Grid Array (13 × 15 × 1.4 mm) Pb-free Industrial
165-ball Fine Pitch Ball Grid Array (13 × 15 × 1.4 mm)
165-ball Fine Pitch Ball Grid Array (13 × 15 × 1.4 mm) Pb-free
165-ball Fine Pitch Ball Grid Array (13 × 15 × 1.4 mm)
165-ball Fine Pitch Ball Grid Array (13 × 15 × 1.4 mm) Pb-free
Commercial
CY7C1268KV18-400BZXC
CY7C1270KV18-400BZC
CY7C1270KV18-400BZXC
450 CY7C1268KV18-450BZXC
550 CY7C1270KV18-550BZC
CY7C1268KV18-550BZXC
51-85180 165-ball Fine Pitch Ball Grid Array (13 × 15 × 1.4 mm) Pb-free Commercial
51-85180 165-ball Fine Pitch Ball Grid Array (13 × 15 × 1.4 mm)
165-ball Fine Pitch Ball Grid Array (13 × 15 × 1.4 mm) Pb-free
Commercial
Ordering Code Definitions
CY 7C 12XX K V18 - XXX BZ
X
C
Temperature Range:
C = Commercial = 0 C to +70 C; I = Industrial = –40 C to +85 C
X = Pb-free; X Absent = Leaded
Package Type:
BZ = 165-ball FPBGA
Speed Grade: XXX = 550 MHz / 450 MHz / 400 MHz
V18 = 1.8 V VDD
Process Technology 65 nm
12XX = 1268 or 1270 = Part Identifier
Marketing Code: 7C = SRAMs
Company ID: CY = Cypress
Document Number: 001-57835 Rev. *C
Page 26 of 28
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CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
Package Diagram
Figure 6. 165-ball FBGA (13 × 15 × 1.4 mm), 51-85180
51-85180 *C
Document Number: 001-57835 Rev. *C
Page 27 of 28
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CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
Document History Page
Document Title: CY7C1266KV18/CY7C1277KV18/CY7C1268KV18/CY7C1270KV18, 36-Mbit DDR II+ SRAM 2-Word Burst
Architecture (2.5 Cycle Read Latency)
Document Number: 001-57835
Orig. of
Change
Submission
Date
Rev.
ECN
Description of Change
**
2816636
3068547
VKN/AESA
NJY
11/30/09
New data sheet
*A
10/22/2010 Converted from Preliminary to Final.
Added Ordering Code Definitions.
Updated Package Diagram.
Minor edits and updated in new template.
*B
*C
3112865
3181270
NJY
12/16/2010 Updated Ordering Information.
SHTC
02/24/2011 Added CY7C1268KV18-400BZC, CY7C1270KV18-400BZXC,
CY7C1270KV18-400BZXI in Ordering Information
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC Solutions
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-57835 Rev. *C
Revised February 24, 2011
Page 28 of 28
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung.
All products and company names mentioned in this document may be the trademarks of their respective holders.
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