CY7C1302CV25-167 [CYPRESS]
9-Mbit Burst of Two Pipelined SRAMs with QDR⑩ Architecture; 9兆位与QDR ™架构连拍两张流水线的SRAM
| 型号： | CY7C1302CV25-167 |
| 厂家： | 
CYPRESS |
| 描述： | 9-Mbit Burst of Two Pipelined SRAMs with QDR⑩ Architecture |
| 文件： | 总18页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1302CV25
PREMILINARY
9-Mbit Burst of Two Pipelined SRAMs
with QDR™ Architecture
Functional Description
Features
• Separate independent Read and Write data ports
— Supports concurrent transactions
• 167-MHz clock for high bandwidth
— 2.5 ns clock-to-Valid access time
• 2-word burst on all accesses
The CY7C1302CV25 is a 2.5V Synchronous Pipelined SRAM
equipped with QDR™ architecture. QDR architecture consists
of two separate ports to access the memory array. The Read
port has dedicated data outputs to support Read operations
and the Write Port has dedicated data inputs to support Write
operations. Access to each port is accomplished through a
common address bus. The Read address is latched on the
• Double Data Rate (DDR) interfaces on both Read and
rising edge of the K clock and the Write address is latched on
the rising edge of K clock. QDR has separate data inputs and
data outputs to completely eliminate the need to “turn-around”
the data bus required with common I/O devices. Accesses to
the CY7C1302CV25 Read and Write ports are completely
independent of one another. All accesses are initiated
synchronously on the rising edge of the positive input clock
(K). In order to maximize data throughput, both Read and
Write ports are equipped with DDR interfaces. Therefore, data
can be transferred into the device on every rising edge of both
input clocks (K and K) and out of the device on every rising
edge of the output clock (C and C, or K and K in a single clock
domain) thereby maximizing performance while simplifying
system design. Each address location is associated with two
18-bit words that burst sequentially into or out of the device.
Write ports (data transferred at 333 MHz) @ 167 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two output clocks (C and C) account for clock skew
and flight time mismatching
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 2.5V core power supply with HSTL Inputs and Outputs
• 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball
(11 x 15 matrix)
Depth expansion is accomplished with a Port Select input for
each port. Each Port Select allows each port to operate
independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• JTAG Interface
Configurations
CY7C1302CV25 – 512K x 18
Logic Block Diagram (CY7C1302CV25)
D[17:0]
18
Write
Write
Data Reg
Data Reg
Address
Register
A
(17:0)
Address
Register
A(17:0)
18
18
256Kx18 256Kx18
Memory Memory
Array
Array
K
CLK
Gen.
RPS
Control
Logic
K
C
C
Read Data Reg.
36
18
Vref
18
Reg.
Reg.
Reg.
18
18
Control
Logic
WPS
18
BWS0
Q[17:0]
BWS1
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05491 Rev. *A
Revised June 1, 2004
CY7C1302CV25
PREMILINARY
Selection Guide
CY7C1302CV25
CY7C1302CV25
CY7C1302CV25
-167
167
750
-133
133
650
-100
100
550
Unit
MHz
mA
Maximum Operating Frequency
Maximum Operating Current
Pin Configuration–CY7C1302CV25 (Top View)
1
2
3
4
5
BWS1
NC
6
K
K
A
7
NC
BWS0
A
8
RPS
A
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TDO
Gnd/144M NC/36M
WPS
A
NC/18M Gnd/72M
NC
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Q9
NC
D11
NC
Q12
D13
VREF
NC
NC
Q15
NC
D17
NC
TCK
D9
D10
Q10
Q11
D12
Q13
VDDQ
D14
Q14
D15
D16
Q16
Q17
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
Q7
NC
D6
NC
NC
VREF
Q4
D3
NC
Q1
NC
D0
TMS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
A
A
C
C
A
A
A
A
Pin Definitions
Name
D[17:0]
I/O
Input-
Synchronous operations.
Description
Data input signals, sampled on the rising edge of K and K clocks during valid Write
WPS
Input-
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted
Synchronous active, a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the
Write port will cause D[17:0] to be ignored.
BWS0, BWS1
Input-
Byte Write Select 0, 1, active LOW. Sampled on the rising edge of the K and K clocks during
Synchronous Write operations. Used to select which byte is written into the device during the current portion
of the Write operations. Bytes not written remain unaltered.
BWS0 controls D[8:0] and BWS1 controls D[17:9].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
A
Input-
Address Inputs. Sampled on the rising edge of the K (read address) and K (write address)
Synchronous clocks for active Read and Write operations. These address inputs are multiplexed for both Read
and Write operations. Internally, the device is organized as 512K x 18 (2 arrays each of 256K x
18). These inputs are ignored when the appropriate port is deselected.
Q[17:0]
RPS
Outputs-
Data Output signals. These pins drive out the requested data during a Read operation. Valid
Synchronous data is driven out on the rising edge of both the C and C clocks during Read operations or K and
K when in single clock mode. When the Read port is deselected, Q[17:0] are automatically
three-stated.
Input-
Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K). When
Synchronous active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When
deselected, the pending access is allowed to complete and the output drivers are automatically
three-stated following the next rising edge of the C clock. Each read access consists of a burst
of two sequential transfers.
C
Input-
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
Clock
Document #: 38-05491 Rev. *A
Page 2 of 18
CY7C1302CV25
PREMILINARY
Pin Definitions (continued)
Name
I/O
Description
C
K
Input-Clock Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board cack to the controller. See application example for further details.
Input-Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q[17:0] when in single clock mode. All accesses are initiated
on the rising edge of K.
K
Input-Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the
device and to drive out data through Q[17:0] when in single clock mode.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. Q[17:0] output impedance is set to 0.2 x RQ, where RQ is a resistor con-
nected between ZQ and ground. Alternately, this pin can be connected directly to VDD, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
TDO
TCK
TDI
TMS
NC/18M
Output
Input
Input
Input
N/A
TDO for JTAG.
TCK pin for JTAG.
TDI pin for JTAG.
TMS pin for JTAG.
Address expansion for 18M. This is not connected to the die and so can be tied to any voltage
level.
NC/36M
N/A
Address expansion for 36M. This is not connected to the die and so can be tied to any voltage
level.
GND/72M
GND/144M
NC
Input
Input
N/A
Address expansion for 72M. This must be tied LOW.
Address expansion for 144M. This must be tied LOW.
Not connected to the die. Can be tied to any voltage level.
VREF
Input-
Reference Voltage Input. Static input used to set the reference level for HSTL inputs and
Reference
Outputs as well as AC measurement points.
VDD
VSS
VDDQ
Power Supply Power supply inputs to the core of the device.
Ground Ground for the device.
Power Supply Power supply inputs for the outputs of the device.
All synchronous control (RPS, WPS, BWS[1:0]) inputs pass
Introduction
Functional Overview
through input registers controlled by the rising edge of input
clocks (K and K).
The CY7C1302CV25 is a synchronous pipelined Burst SRAM
equipped with both a Read port and a Write port. The Read
port is dedicated to Read operations and the Write port is
dedicated to Write operations. Data flows into the SRAM
through the Write port and out through the Read port. These
devices multiplex the address inputs in order to minimize the
number of address pins required. By having separate Read
and Write ports, the QDR-I completely eliminates the need to
“turn-around” the data bus and avoids any possible data
contention, thereby simplifying system design.
Accesses for both ports are initiated on the rising edge of the
Positive Input Clock (K). All synchronous input timing is refer-
enced from the rising edge of the input clocks (K and K) and
all output timing is referenced to the output clocks (C and C,
or K and K when in single clock mode).
Read Operations
The CY7C1302CV25 is organized internally as 2 arrays of
256K x 18. Accesses are completed in a burst of two
sequential 18-bit data words. Read operations are initiated by
asserting RPS active at the rising edge of the positive input
clock (K). The address is latched on the rising edge of the K
clock. Following the next K clock rise the corresponding lower
order 18-bit word of data is driven onto the Q[17:0] using C as
the output timing reference. On the subsequent rising edge of
C the higher order data word is driven onto the Q[17:0]. The
requested data will be valid 2.5 ns from the rising edge of the
output clock (C and C, or K and K when in single clock mode,
167-MHz device).
Synchronous internal circuitry will automatically three-state
the outputs following the next rising edge of the positive output
clock (C). This will allow for a seamless transition between
devices without the insertion of wait states in a depth
expanded memory.
All synchronous data inputs (D[17:0]) pass through input
registers controlled by the input clocks (K and K). All
synchronous data outputs (Q[17:0]) pass through output
registers controlled by the rising edge of the output clocks (C
and C, or K and K when in single clock mode).
Document #: 38-05491 Rev. *A
Page 3 of 18
CY7C1302CV25
PREMILINARY
Write Operations
power-up.This function is a strap option and not alterable
during device operation.
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the same K clock
rise the data presented to D[17:0] is latched into the lower 18-bit
Write Data register provided BWS[1:0] are both asserted
active. On the subsequent rising edge of the negative input
clock (K), the address is latched and the information presented
to D[17:0] is stored into the Write Data register provided
BWS[1:0] are both asserted active. The 36 bits of data are then
written into the memory array at the specified location.
Concurrent Transactions
The Read and Write ports on the CY7C1302CV25 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the trans-
action on the other port. Also, reads and writes can be started
in the same clock cycle. If the ports access the same location
at the same time, the SRAM will deliver the most recent infor-
mation associated with the specified address location. This
includes forwarding data from a Write cycle that was initiated
on the previous K clock rise.
When deselected, the Write port will ignore all inputs after the
pending Write operations have been completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1302CV25.
A Write operation is initiated as described in the Write
Operation section above. The bytes that are written are deter-
mined by BWS0 and BWS1 which are sampled with each set
of 18-bit data word. Asserting the appropriate Byte Write
Select input during the data portion of a write will allow the data
being presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write will allow the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
Depth Expansion
The CY7C1302CV25 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the Positive Input Clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ
=1.5V. The output impedance is adjusted every 1024 cycles to
account for drifts in supply voltage and temperature.
Single Clock Mode
The CY7C1302CV25 can be used with a single clock mode.
In this mode the device will recognize only the pair of input
clocks (K and K) that control both the input and output
registers. This operation is identical to the operation if the
device had zero skew between the K/K and C/C clocks. All
timing parameters remain the same in this mode. To use this
mode of operation, the user must tie C and C HIGH at
Application Example[1]
Note:
1. The above application shows 4 QDR-I being used.
Document #: 38-05491 Rev. *A
Page 4 of 18
CY7C1302CV25
PREMILINARY
Truth Table[2, 3, 4, 5, 6, 7]
Operation
K
RPS
WPS
DQ
DQ
Write Cycle:
L-H
X
L
D(A+0)at
D(A+1) at
Load address on the rising edge of K clock; input write
data on K and K rising edges.
K(t) ↑
K(t) ↑
Read Cycle:
L-H
L
X
Q(A+0) at
Q(A+1) at
Load address on the rising edge of K clock; wait one
cycle; read data on 2 consecutive C and C rising edges.
C(t+1)↑
C(t+1) ↑
NOP: No Operation
L-H
H
X
H
X
D = X
D = X
Q = High-Z Q = High-Z
Standby: Clock Stopped
Stopped
Previous
State
Previous
State
Write Cycle Descriptions[2,8]
BWS0
BWS1
L
L
K
L-H
–
K
–
Comments
L
L
L
During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device.
L-H During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device.
–
H
L-H
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the
device. D[17:9] remains unaltered.
L
H
L
L
–
L-H
–
L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the
device. D[17:9] remains unaltered.
H
H
H
–
During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device.
[8:0] remains unaltered.
D
L-H During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device.
[8:0] remains unaltered.
D
H
H
L-H
–
–
No data is written into the device during this portion of a Write operation.
H
L-H No data is written into the device during this portion of a Write operation.
Notes:
2. X = Don't Care, H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
3. Device will power-up deselected and the outputs in a three-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A+0, A+1 represent the addresses sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t+1 is the first clock cycle succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS , BWS can be altered on different portions of a Write cycle, as long
0
1
as the set-up and hold requirements are achieved.
Document #: 38-05491 Rev. *A
Page 5 of 18
CY7C1302CV25
PREMILINARY
Static Discharge Voltage........................................... >2001V
Maximum Ratings
(Above which the useful life may be impaired.)
Storage Temperature ..................................–65°C to +150°C
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
[10]
[10]
Range Temperature (TA)
Com’l
VDD
2.5 ± 0.1V
VDDQ
1.4V to 1.9V
Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V
DC Applied to Outputs in High-Z......... –0.5V to VDDQ + 0.5V
DC Input Voltage[9 .............................. –0.5V to VDDQ + 0.5V
Current into Outputs (LOW).........................................20 mA
0°C to +70°C
Electrical Characteristics Over the Operating Range[11]
DC Electrical Characteristics Over the Operating Range
Parameter
VDD
VDDQ
VOH
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
2.4
1.4
Typ.
2.5
1.5
Max.
2.6
1.9
Unit
V
V
V
V
V
V
V
V
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[9]
Input LOW Voltage[9, 14]
Clock Input Voltage
Input Load Current
Note 12
Note 13
VDDQ/2 – 0.12
VDDQ/2 – 0.12
VDDQ/2 + 0.12
VDDQ/2 + 0.12
VOL
VOH(LOW)
VOL(LOW)
VIH
VIL
VIN
IX
IOZ
VREF
IDD
IOH = –0.1 mA, Nominal Impedance VDDQ – 0.2
IOL = 0.1 mA, Nominal Impedance
VDDQ
0.2
VDDQ + 0.3
VREF –0.1
VDDQ+0.3
5
VSS
VREF + 0.1
–0.3
–0.3
–5
–5
0.68
V
GND ≤ VI ≤ VDDQ
GND ≤ VI ≤ VDDQ, Output Disabled
µA
µA
V
mA
mA
mA
mA
mA
mA
Output Leakage Current
5
0.95
750
650
550
470
450
430
Input Reference Voltage[15] Typical value = 0.75V
0.75
VDD Operating Supply
VDD = Max.,
167 MHz
133 MHz
100 MHz
167 MHz
133 MHz
100 MHz
IOUT = 0 mA,
f = fMAX = 1/tCYC
ISB1
Automatic
Power-Down
Current
Max. VDD, Both Ports
Deselected, VIN ≥ VIH or
V
IN ≤ VIL, f =
f
MAX = 1/tCYC,
Inputs Static
AC Input Requirements Over the Operating Range
Parameter
VIH
VIL
Description
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Test Conditions
Min.
VREF + 0.2
–
Typ.
Max.
–
VREF – 0.2
Unit
V
V
Notes:
9. Overshoot: V (AC) < V
+0.85V (Pulse width less than t
/2), Undershoot: V AC) > –1.5V (Pulse width less than t
/2).
IH
DDQ
CYC
IL(
CYC
10. Power-up: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
.
DD
IH
DD
DDQ
DD
11. All voltage referenced to Ground.
12. Output are impedance controlled. I = –(V
/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.
DDQ
OH
OL
13. Output are impedance controlled. I = (V
/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.
DDQ
14. This spec is for all inputs except C and C Clock. For C and C Clock, V (Max.) = V
– 0.2V.
IL
REF
DDQ
15. V
(Min.) = 0.68V or 0.46V
, whichever is larger, V
(Max.) = 0.95V or 0.54V
, whichever is smaller.
REF
DDQ
REF
Document #: 38-05491 Rev. *A
Page 6 of 18
CY7C1302CV25
PREMILINARY
Thermal Resistance[16]
Parameter
Description
Test Conditions
165 FBGA Package Unit
ΘJA
ΘJC
Thermal Resistance (Junction to Ambient) Test conditions follow standard test
16.7
2.5
°C/W
°C/W
methods and procedures for measuring
Thermal Resistance (Junction to Case)
thermal impedance, per EIA/JESD51.
Capacitance[16]
Parameter
Description
Input Capacitance
Clock Input Capacitance
Output Capacitance
Test Conditions
Max.
Unit
pF
pF
CIN
CCLK
CO
TA = 25°C, f = 1 MHz,
5
6
7
V
DD = 2.5V.
VDDQ = 1.5V
pF
AC Test Loads and Waveforms
V
DDQ/2
V
DDQ/2
VREF
OUTPUT
VREF
VDDQ/2
R = 50Ω
[17]
ALL INPUT PULSES
Z = 50Ω
0
OUTPUT
1.25V
Device
Under
Test
R = 50Ω
L
0.75V
Device
Under
0.25V
5 pF
VREF = 0.75V
ZQ
Test
ZQ
RQ =
RQ =
250Ω
250Ω
(a)
INCLUDING
JIG AND
SCOPE
(b)
Switching Characteristics Over the Operating Range [17]
-167
-133
-100
Cypress
Consortium
Parameter
Parameter
Description
VCC (typical) to the First Access Read or Write
Min. Max. Min. Max. Min. Max. Unit
[18]
tPower
10
10
10
µs
Cycle Time
tCYC
tKH
tKL
tKHKH
tKHKH
tKHKL
tKLKH
tKHKH
K Clock and C Clock Cycle Time
Input Clock (K/K and C/C) HIGH
Input Clock (K/K and C/C) LOW
6.0
2.4
2.4
7.5
3.2
3.2
3.4
10.0
3.5
3.5
4.4
ns
ns
ns
ns
K/K Clock Rise to K/K Clock Rise and C/C to C/C 2.7
3.3
2.0
4.1
2.5
5.4
3.0
Rise (rising edge to rising edge)
tKHCH
tKHCH
K/K Clock Rise to C/C Clock Rise (rising edge to 0.0
rising edge)
0.0
0.0
ns
Set-up Times
tSA
tSC
tSA
tSC
Address Set-up to Clock (K and K) Rise
0.7
0.7
0.8
0.8
1.0
1.0
ns
ns
Control Set-up to Clock (K and K) Rise (RPS,
WPS, BWS0, BWS1)
tSD
tSD
D[17:0] Set-up to Clock (K and K) Rise
0.7
0.8
1.0
ns
Notes:
16. Tested initially and after any design or process change that may affect these parameters.
17. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V,Vref = 0.75V, RQ = 250W, V
= 1.5V, input
DDQ
pulse levels of 0.25V to 1.25V, and output loading of the specified I /I and load capacitance shown in (a) of AC test loads.
OL OH
18. This part has a voltage regulator that steps down the voltage internally; t
or write operation can be initiated.
is the time power needs to be supplied above V minimum initially before a read
DD
Power
Document #: 38-05491 Rev. *A
Page 7 of 18
CY7C1302CV25
PREMILINARY
Switching Characteristics Over the Operating Range (continued)[17]
-167
-133
-100
Cypress
Consortium
Parameter
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
Hold Times
tHA
tHC
tHA
tHC
Address Hold after Clock (K and K) Rise
0.7
0.8
0.8
1.0
1.0
ns
ns
Control Signals Hold after Clock (K and K) Rise 0.7
(RPS, WPS, BWS0, BWS1)
tHD
tHD
D[17:0] Hold after Clock (K and K) Rise
0.7
0.8
1.0
ns
Output Times
tCO
tCHQV
C/C Clock Rise (or K/K in single clock mode) to
Data Valid
2.5
2.5
3.0
3.0
3.0
3.0
ns
ns
tDOH
tCHZ
tCHQX
Data Output Hold after Output C/C Clock Rise
1.2
1.2
1.2
1.2
1.2
1.2
(Active to Active)
tCHZ
tCLZ
Clock(CandC)RisetoHigh-Z(ActivetoHigh-Z)[19, 20]
Clock (C and C) Rise to Low-Z[19, 20]
ns
ns
tCLZ
Notes:
19. t
, t
, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
CHZ CLZ
20. At any given voltage and temperature t
is less than t
and, t
less than t
.
CHZ
CLZ
CHZ
CO
Document #: 38-05491 Rev. *A
Page 8 of 18
CY7C1302CV25
PREMILINARY
Switching Waveforms[21, 22, 23]
READ
1
WRITE
2
READ
3
WRITE
READ
5
WRITE
NOP
7
WRITE
8
NOP
9
6
4
10
K
t
t
t
t
KHKH
KH
KL
CYC
K
RPS
tSC
tHC
WPS
A
A5
A6
A0
A1
A2
A3
A4
t
t
t
t
SA HA
SA HA
D
Q
D10
D11
D30
D31
D50
D51
D60
D61
t
t
HD
t
SD
HD
t
SD
Q00
Q01
Q20
Q21
Q40
Q41
t
CHZ
t
t
t
DOH
DOH
CLZ
t
t
t
t
CO
KHCH
KHCH
CO
C
C
t
t
t
KHKH
tCYC
KH
KL
DON’T CARE
UNDEFINED
Notes:
21. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0 i.e., A0+1.
22. Outputs are disabled (High-Z) one clock cycle after a NOP.
23. In this example, if address A2=A1 then data Q20=D10 and Q21=D11. Write data is forwarded immediately as read results.This note applies to the whole diagram.
Document #: 38-05491 Rev. *A
Page 9 of 18
CY7C1302CV25
PREMILINARY
TDI and TDO pins as shown in TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant
with IEEE Standard #1149.1-1900. The TAP operates using
JEDEC standard 2.5V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
Test Mode Select
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.
TAP Instruction Set
Performing a TAP Reset
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
Document #: 38-05491 Rev. *A
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CY7C1302CV25
PREMILINARY
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
SAMPLE Z
BYPASS
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
EXTEST Output Bus Three-state
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a three-state mode.
The boundary scan register has a special bit located at bit #47.
When this scan cell, called the “extest output bus three-state”,
is latched into the preload register during the “Update-DR”
state in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 38-05491 Rev. *A
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CY7C1302CV25
PREMILINARY
TAP Controller State Diagram[24]
TEST-LOGIC
RESET
1
0
0
1
1
1
TEST-LOGIC/
IDLE
SELECT
SELECT
DR-SCAN
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note:
24. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05491 Rev. *A
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CY7C1302CV25
PREMILINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
TDI
Selection
Circuitry
2
1
0
0
0
TDO
Circuitry
Instruction Register
29
31 30
.
.
2
1
Identification Register
.
106 .
.
.
2
1
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range [11, 9, 25]
Parameter
VOH1
Description
Output HIGH Voltage
Test Conditions
IOH = −2.0 mA
Min.
1.7
Max.
Unit
V
VOH2
VOL1
VOL2
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input and Output Load Current
IOH = −100 µA
IOL = 2.0 mA
IOL = 100 µA
2.1
V
V
V
V
V
µA
0.7
0.2
VDD + 0.3
1.7
–0.3
–5
0.7
5
GND ≤ VI ≤ VDDQ
[26, 27]
TAP AC Switching Characteristics Over the Operating Range
Parameter
tTCYC
tTF
tTH
Description
Min.
100
Max.
Unit
ns
MHz
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
10
40
40
tTL
TCK Clock LOW
ns
Set-up Times
tTMSS
tTDIS
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
10
10
10
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
10
10
10
ns
ns
ns
tCH
Notes:
25. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.
26. T and T refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
27. Test conditions are specified using the load in TAP AC test conditions. Tr/Tf = 1 ns.
Document #: 38-05491 Rev. *A
Page 13 of 18
CY7C1302CV25
PREMILINARY
TAP AC Switching Characteristics Over the Operating Range (continued) [26, 27]
Parameter
Output Times
tTDOV
Description
Min.
Max.
Unit
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
20
ns
ns
tTDOX
0
TAP Timing and Test Conditions[27]
1.25V
50Ω
ALL INPUT PULSES
1.25V
TDO
2.5V
Z = 50Ω
0
C = 20 pF
L
0V
(a)
GND
tTL
tTH
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
tTDOV
Identification Register Definitions
Value
CY7C1302CV25
001
Instruction Field
Revision Number (31:29)
Cypress Device ID (28:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
Description
Version number.
01011010010010110
Defines the type of SRAM.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
00000110100
1
Document #: 38-05491 Rev. *A
Page 14 of 18
CY7C1302CV25
PREMILINARY
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
107
Boundary Scan
Instruction Codes
Instruction
EXTEST
Code
000
Description
Captures the Input/Output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
SAMPLE/PRELOAD
011
100
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register between TDI
and TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Boundary Scan Order (continued)
Boundary Scan Order
Bit #
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Bump ID
Bit #
0
1
2
3
4
5
6
Bump ID
6R
9J
9K
6P
6N
7P
7N
7R
8R
8P
9R
11P
10P
10N
9P
10M
11N
9M
10J
11J
11H
10G
9G
11F
11G
9F
10F
11E
10E
10D
9E
10C
11D
9C
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
9N
11L
11M
9L
10L
11K
10K
9D
11B
11C
9B
10B
11A
Document #: 38-05491 Rev. *A
Page 15 of 18
CY7C1302CV25
PREMILINARY
Boundary Scan Order (continued)
Boundary Scan Order (continued)
Bit #
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Bump ID
Bit #
91
92
93
94
95
96
97
Bump ID
1M
1L
Internal
9A
8B
7C
6C
8A
7A
7B
6B
6A
5B
5A
4A
5C
4B
3A
1H
1A
2B
3B
1C
1B
3D
3C
1D
2C
3E
2D
2E
1E
2F
3F
1G
1F
3G
2G
1J
3N
3M
1N
2M
3P
2N
2P
1P
3R
4R
98
99
100
101
102
103
104
105
106
4P
5P
5N
5R
2J
3K
3J
2K
1K
2L
3L
Document #: 38-05491 Rev. *A
Page 16 of 18
PREMILINARY
CY7C1302CV25
Ordering Information
Speed
Package
Operating
Range
Commercial
(MHz)
167
Ordering Code
Name
Package Type
13 x 15 x 1.4 mm FBGA
13 x 15 x 1.4 mm FBGA
13 x 15 x 1.4 mm FBGA
CY7C1302CV25-167BZC
CY7C1302CV25-133BZC
CY7C1302CV25-100BZC
BB165D
BB165D
BB165D
133
100
Package Diagram
165 FBGA 13 x 15 x 1.40 mm BB165D
51-85180-**
Quad Data Rate SRAM and QDR SRAM comprise a new family of products developed by Cypress, IDT, NEC and Samsung.
All product and company names mentioned in this document are trademarks of their respective holders.
Document #: 38-05491 Rev. *A
Page 17 of 18
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1302CV25
PREMILINARY
Document History Page
Document Title:CY7C1302CV25 9-Mb Burst of 2 Pipelined SRAM with QDR™ Architecture
Document Number: 38-05491
Orig. of
REV.
**
*A
ECN NO.
208401
230396
Issue Date
see ECN
see ECN
Change
DIM
Description of Change
New Data Sheet
VBL
Upload datasheet to the internet
Document #: 38-05491 Rev. *A
Page 18 of 18
相关型号：
CY7C1302DV25-100BZC
QDR SRAM, 512KX18, 3ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165
CYPRESS
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