CY7C1303CV25-167BZC [CYPRESS]
18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture; 18兆位突发的2流水线SRAM与QDR架构
| 型号： | CY7C1303CV25-167BZC |
| 厂家： | 
CYPRESS |
| 描述： | 18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture |
| 文件： | 总21页 (文件大小：522K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1303CV25
CY7C1306CV25
PRELIMINARY
18-Mbit Burst of 2 Pipelined SRAM with
QDR™ Architecture
Features
Functional Description
■
Separate independent read and write data ports
Supports concurrent transactions
167 MHz clock for high bandwidth
2.5 ns Clock-to-Valid access time
2-word burst on all accesses
The CY7C1303CV25 and CY7C1306CV25 are 2.5V
Synchronous Pipelined SRAMs, equipped with QDR™
architecture. QDR architecture consists of two separate ports:
the read port and the write port to access the memory array. The
read port has data outputs to support read operations and the
write port has data inputs to support write operations. QDR
architecture has separate data inputs and data outputs to
completely eliminate the need to “turn-around” the data bus
required with common I/O devices. Access to each port is
accomplished through a common address bus. The read
address is latched on the rising edge of the K clock and the write
address is latched on the rising edge of the K clock. Accesses to
the QDR read and write ports are completely independent of one
another. All accesses are initiated synchronously on the rising
edge of the positive input clock (K). To maximize data
throughput, both read and write ports are provided with DDR
interfaces. Therefore, data can be transferred into the device on
every rising edge of both input clocks (K and K) and out of the
device on every rising edge of the output clock (C and C, or K
and K when in single clock mode) thereby maximizing
performance while simplifying system design. Each address
location is associated with two 18-bit words (CY7C1303CV25),
or 36-bit words (CY7C1306CV25) that burst sequentially into or
out of the device.
❐
■
❐
■
■
DoubleDataRate(DDR)interfacesonbothreadandwriteports
(data transferred at 333 MHz) at 167 MHz
■
■
■
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Single multiplexed address input bus latches address inputs
for both read and write ports
■
■
■
■
■
■
■
■
Separate port selects for depth expansion
Synchronous internally self-timed writes
2.5V core power supply with HSTL inputs and outputs
Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
Variable drive HSTL output buffers
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
Expanded HSTL output voltage (1.4V–1.9V)
JTAG interface
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K/K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Variable Impedance HSTL
Configurations
CY7C1303CV25 – 1M x 18
CY7C1306CV25 – 512K x 36
Selection Guide
Description
167 MHz
167
Unit
MHz
mA
Maximum Operating Frequency
Maximum Operating Current
500
Cypress Semiconductor Corporation
Document #: 001-44701 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 31, 2009
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CY7C1303CV25
CY7C1306CV25
PRELIMINARY
Logic Block Diagram (CY7C1303CV25)
18
D
[17:0]
Write
Reg
Write
Reg
19
Address
Register
A
(18:0)
19
Address
Register
A
(18:0)
RPS
K
K
Control
Logic
CLK
Gen.
C
C
Read Data Reg.
36
18
V
REF
18
18
Reg.
Reg.
Reg.
Control
Logic
WPS
BWS
18
Q
18
[17:0]
[1:0]
Logic Block Diagram (CY7C1306CV25)
36
D
[35:0]
Write
Reg
Write
Reg
18
Address
Register
A
(17:0)
18
Address
Register
A
(17:0)
RPS
K
K
Control
Logic
CLK
Gen.
C
C
Read Data Reg.
72
36
V
REF
36
36
Reg.
Reg.
Reg.
Control
Logic
WPS
BWS
36
36
Q
[35:0]
[3:0]
Document #: 001-44701 Rev. *B
Page 2 of 21
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CY7C1303CV25
CY7C1306CV25
PRELIMINARY
Pin Configuration
The pin configurations for CY7C1303CV25 and CY7C1306CV25 follow.
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1303CV25 (1M x 18)
1
2
3
NC/36M
D9
4
5
BWS1
NC
A
6
7
NC
BWS0
A
8
9
A
10
11
NC
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
GND/144M
GND/72M
A
B
C
D
E
F
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TDO
WPS
A
K
RPS
A
Q9
NC
K
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
Q7
D10
Q10
Q11
D12
Q13
VDDQ
D14
Q14
D15
D16
Q16
Q17
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
D11
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
NC
D6
Q12
D13
VREF
NC
NC
NC
VREF
Q4
G
H
J
K
L
NC
D3
Q15
NC
NC
Q1
M
N
P
R
D17
NC
NC
D0
A
C
A
TCK
A
A
C
A
A
TMS
CY7C1306CV25 (512K x 36)
1
2
3
NC/72M
D18
D19
Q19
Q20
D21
Q22
VDDQ
D23
Q23
D24
D25
Q25
Q26
A
4
5
BWS2
BWS3
A
6
7
BWS1
BWS0
A
8
9
NC/36M
D17
D16
Q16
Q15
D14
Q13
VDDQ
D12
Q12
D11
D10
Q10
Q9
10
11
NC
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
GND/288M
GND/144M
A
B
C
D
E
F
NC
WPS
A
K
RPS
A
Q27
D27
D28
Q29
Q30
D30
NC
Q18
Q28
D20
D29
Q21
D22
VREF
Q31
D32
Q24
Q34
D26
D35
TCK
K
Q17
Q7
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
D15
D6
Q14
D13
VREF
Q4
G
H
J
D31
Q32
Q33
D33
D34
Q35
TDO
K
L
D3
Q11
Q1
M
N
P
R
D9
A
C
A
D0
A
A
C
A
A
A
TMS
Document #: 001-44701 Rev. *B
Page 3 of 21
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CY7C1303CV25
CY7C1306CV25
PRELIMINARY
Pin Definitions
Pin Name
I/O
Pin Description
D[x:0]
Input-
Synchronous
Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.
CY7C1303CV25 - D[17:0]
CY7C1306CV25 - D[35:0]
WPS
Input-
Synchronous
Write Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0]
.
BWS0,
BWS1,
BWS2,
BWS3
Input-
Synchronous
Byte Write Select 0, 1, 2 and 3 − Active LOW. Sampled on the rising edge of the K and K clocks
during write operations. Used to select which byte is written into the device during the current portion
of the write operations.
CY7C1303CV25 − BWS0 controls D[8:0], BWS1 controls D[17:9]
.
CY7C1306CV25 − BWS0 controls D[8:0], BWS1 controls D[17:9],BWS2 controls D[26:18] and BWS3
controls D[35:27].
Bytes not written remain unaltered. Deselecting a Byte Write Select ignores the corresponding byte of
data and it is not written into the device.
A
Input-
Synchronous
Address Inputs. Sampled on the rising edge of the K clock during active Read operations and on the
rising edge of K for Write operations. These address inputs are multiplexed for both read and write
operations. Internally, the device is organized as 1M x 18 (2 arrays each of 512K x 18) for
CY7C1303CV25 and 512K x 36 (2 arrays each of 256K x 36) for CY7C1306CV25. Therefore, only 19
address inputs are needed to access the entire memory array of CY7C1303CV25 and 18 address
inputs for CY7C1306CV25. These inputs are ignored when the appropriate port is deselected.
Q[x:0]
Outputs-
Synchronous
Data Output Signals. These pins drive out the requested data during a read operation. Valid data is
driven out on the rising edge of both the C and C clocks during read operations, or K and K when in
single clock mode. When the read port is deselected, Q[x:0] are automatically tri-stated.
CY7C1303CV25 − Q[17:0]
CY7C1306CV25 − Q[35:0]
RPS
C
Input-
Synchronous
Read Port Select − Active LOW. Sampled on the rising edge of positive input clock (K). When active,
a read operation is initiated. Deasserting deselects the read port. When deselected, the pending access
is allowed to complete and the output drivers are automatically tri-stated following the next rising edge
of the C clock. Each read access consists of a burst of two sequential transfers.
Input Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board
back to the controller. See Application Example on page 7 for further details.
C
K
Input Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board
back to the controller. See Application Example on page 7 for further details.
Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising
edge of K.
K
Input Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device
and to drive out data through Q[x:0] when in single clock mode.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data
bus impedance. Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between
ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the minimum
impedance mode. This pin cannot be connected directly to GND or left unconnected.
Document #: 001-44701 Rev. *B
Page 4 of 21
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CY7C1303CV25
CY7C1306CV25
PRELIMINARY
Pin Definitions (continued)
Pin Name
TDO
I/O
Output
Input
Input
Input
N/A
Pin Description
TDO for JTAG.
TCK
TCK Pin for JTAG.
TDI Pin for JTAG.
TMS Pin for JTAG.
TDI
TMS
NC
Not Connected to the Die. Can be tied to any voltage level.
Not Connected to the Die. Can be tied to any voltage level.
NC/36M
GND/72M
NC/72M
GND/144M
GND/288M
VREF
N/A
Input
N/A
Address expansion for 72M. This pin must be tied to GND on CY7C1303CV25.
Address expansion for 72M. This pin can be tied to any voltage level on CY7C1306CV25.
Address expansion for 144M. This pin must be tied to GND on CY7C1303CV25/CY7C1306CV25.
Address expansion for 288M. This pin must be tied to GND on CY7C1306CV25.
Input
Input
Input-
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, Outputs, and
AC measurement points.
Reference
VDD
VSS
Power Supply Power Supply Inputs to the Core of the Device.
Ground Ground for the Device.
Power Supply Power Supply Inputs for the Outputs of the Device.
VDDQ
Document #: 001-44701 Rev. *B
Page 5 of 21
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CY7C1303CV25
CY7C1306CV25
PRELIMINARY
BWS[1:0] are both asserted active. The 36 bits of data are then
written into the memory array at the specified location. When
deselected, the write port ignores all inputs after completion of
pending write operations.
Functional Overview
The CY7C1303CV25 and CY7C1306CV25 are synchronous
pipelined Burst SRAMs equipped with a read port and a write
port. The read port is dedicated to read operations and the write
port is dedicated to write operations. Data flows into the SRAM
through the write port and flows out through the read port. These
devices multiplex the address inputs to minimize the number of
address pins required. By having separate read and write ports,
the QDR completely eliminates the need to “turn-around” the
data bus and avoids any possible data contention, thereby
simplifying system design. Each access consists of two 18-bit
data transfers in the case of CY7C1303CV25, and two 36-bit
data transfers in the case of CY7C1306CV25 in one clock cycle.
Byte Write Operations
Byte write operations are supported by the CY7C1303CV25. A
write operation is initiated as described in the section Write
Operations on page 6. The bytes that are written are determined
by BWS0 and BWS1, which are sampled with each 18-bit data
word. Asserting the appropriate Byte Write Select input during
the data portion of a write latches the data being presented and
writes it into the device. Deasserting the Byte Write Select input
during the data portion of a write allows the data stored in the
device for that byte to remain unaltered. This feature can be used
to simplify read, modify, or write operations to a byte write
operation.
Accesses for both ports are initiated on the rising edge of the
positive input clock (K). All synchronous input timing is
referenced from the rising edge of the input clocks (K and K) and
all output timing is referenced to the rising edge of the output
clocks (C and C, or K and K when in single clock mode).
Single Clock Mode
The CY7C1303CV25 can be used with a single clock that
controls both the input and output registers. In this mode, the
device recognizes only a single pair of input clocks (K and K) that
control both the input and output registers. This operation is
identical to the operation if the device had zero skew between
the K/K and C/C clocks. All timing parameters remain the same
in this mode. To use this mode of operation, the user must tie C
and C HIGH at power on. This function is a strap option and not
alterable during device operation.
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q[x:0]) pass through output registers controlled by the
rising edge of the output clocks (C and C or K and K when in
single clock mode).
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the input
clocks (K and K).
CY7C1303CV25 is described in the following sections. The
same basic descriptions apply to CY7C1306CV25.
Concurrent Transactions
The read and write ports on the CY7C1303CV25 operate
independently of one another. As each port latches the address
inputs on different clock edges, the user can read or write to any
location, regardless of the transaction on the other port. The user
can start reads and writes in the same clock cycle. If the ports
access the same location at the same time, the SRAM delivers
the most recent information associated with the specified
address location. This includes forwarding data from a write
cycle that was initiated on the previous K clock rise.
Read Operations
The CY7C1303CV25 is organized internally as two arrays of
512K x 18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the positive input clock (K). The
address is latched on the rising edge of the K clock. The address
presented to the address inputs is stored in the read address
register. Following the next K clock rise the corresponding lowest
order 18-bit word of data is driven onto the Q[17:0] using C as the
output timing reference. On the subsequent rising edge of C, the
next 18-bit data word is driven onto the Q[17:0]. The requested
data is valid 2.5 ns from the rising edge of the output clock (C
and C or K and K when in single clock mode).
Depth Expansion
The CY7C1303CV25 has a port select input for each port. This
enables for easy depth expansion. Both port selects are sampled
on the rising edge of the positive input clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed before the device is deselected.
Synchronous internal circuitry automatically tri-states the outputs
following the next rising edge of the positive output clock (C).
This allows a seamless transition between devices without the
insertion of wait states in a depth expanded memory.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5x the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V. The
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the same K clock
rise, the data presented to D[17:0] is latched and stored into the
lower 18-bit write data register, provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the negative
input clock (K), the address is latched and the information
presented to D[17:0] is stored into the write data register, provided
Document #: 001-44701 Rev. *B
Page 6 of 21
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CY7C1303CV25
CY7C1306CV25
PRELIMINARY
Application Example
Figure 1 shows four QDR-I used in an application.
Figure 1. Application Example
SRAM #1
SRAM #4
ZQ
ZQ
R W
R
B
W
S
W
P
B
W
S
Vt
P
S
#
P
S
#
P
S
#
R = 250ohms
R = 250ohms
D
A
Q
K#
D
A
Q
K#
S
R
C
C#
K
C
C#
K
#
#
#
DATA IN
DATA OUT
Address
RPS#
Vt
Vt
R
BUS
MASTER
(CPU
or
WPS#
BWS#
Source K
Source K#
ASIC)
Delayed K
Delayed K#
R
R = 50ohms
Vt = Vddq/2
Truth Table
The truth table for CY7C1303CV25 and CY7C1306CV25 follows. [1, 2, 3, 4, 5, 6]
Operation
K
RPS WPS
DQ
DQ
Write Cycle:
Load address on the rising edge of K;
input write data on K and K rising edges.
L-H
X
L
L
D(A + 0) at K(t) ↑
D(A + 1) at K(t) ↑
Read Cycle:
L-H
X
Q(A + 0) at C(t + 1) ↑ Q(A + 1) at C(t + 1) ↑
Load address on the rising edge of K;
wait one cycle; read data on C and C rising edges.
NOP: No Operation
L-H
H
X
H
X
D = X
Q = High-Z
D = X
Q = High-Z
Standby: Clock Stopped
Stopped
Previous State
Previous State
Notes
1. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
2. Device powers up deselected with the outputs in a tri-state condition.
↑
represents rising edge.
3. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.
4. “t” represents the cycle at which a Read/Write operation is started. t + 1 is the first clock cycle succeeding the “t” clock cycle.
5. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
6. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
Document #: 001-44701 Rev. *B
Page 7 of 21
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CY7C1303CV25
CY7C1306CV25
PRELIMINARY
Write Cycle Descriptions
The write cycle description table for CY7C1303CV25 follows. [1, 7]
BWS0 BWS1
K
L–H
–
Comments
During the data portion of a write sequence, both bytes (D[17:0]) are written into the device.
K
L
L
L
L
L
–
L-H During the data portion of a write sequence, both bytes (D[17:0]) are written into the device.
During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device,
H
L–H
–
D[17:9] remains unaltered.
L
H
H
H
L
L
–
L–H
–
L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device,
D[17:9] remains unaltered.
–
During the data portion of a write sequence, only the upper byte (D[17:9]) is written into the device,
D[8:0] remains unaltered.
L–H During the data portion of a write sequence, only the upper byte (D[17:9]) is written into the device,
D
[8:0] remains unaltered.
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
H
H
H
H
L–H
–
–
Write Cycle Descriptions
The write cycle description table for CY7C1306CV25 follows. [1, 7]
BWS0 BWS1 BWS2 BWS3
K
K
Comments
L
L
L
L
L–H
–
During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
–
L–H
–
L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
–
During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L
L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H
H
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H
H
H
H
H
H
H
H
L–H
–
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Note
7. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. BWS , BWS , BWS and BWS can be altered on different portions
0
1
2,
3
of a write cycle, as long as the setup and hold requirements are achieved.
Document #: 001-44701 Rev. *B
Page 8 of 21
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CY7C1303CV25
CY7C1306CV25
PRELIMINARY
Instruction Register
IEEE 1149.1 Serial Boundary Scan (JTAG)
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in TAP Controller Block Diagram on
page 12. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
These SRAMs incorporate a serial boundary scan Test Access
Port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-1900. The TAP operates using JEDEC
standard 2.5V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternatively be connected to VDD through a pull up resistor. TDO
must be left unconnected. Upon power up, the device comes up
in a reset state, which does not interfere with the operation of the
device.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow the
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see the TAP Controller State
Diagram on page 11. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
The Boundary Scan Order on page 15 shows the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
Test Data-Out (TDO)
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 14.
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 14).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
TAP Instruction Set
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
SRAM and can be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a High-Z state.
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 14. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
TAP Registers
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Document #: 001-44701 Rev. *B
Page 9 of 21
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CY7C1303CV25
CY7C1306CV25
PRELIMINARY
IDCODE
BYPASS
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-Reset state.
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High-Z state until the next command is supplied during the
Update IR state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
SAMPLE/PRELOAD
The boundary scan register has a special bit located at bit #47.
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High-Z condition.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is pre-set HIGH to enable
the output when the device is powered up, and also when the
TAP controller is in the Test-Logic-Reset state.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
Document #: 001-44701 Rev. *B
Page 10 of 21
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CY7C1303CV25
CY7C1306CV25
PRELIMINARY
TAP Controller State Diagram
The state diagram for the TAP controller follows. [8]
TEST-LOGIC
1
RESET
0
1
1
1
SELECT
TEST-LOGIC/
SELECT
0
IR-SCAN
IDLE
DR-SCAN
0
0
1
1
CAPTURE-DR
0
CAPTURE-IR
0
0
0
SHIFT-DR
1
SHIFT-IR
1
1
0
1
EXIT1-DR
0
EXIT1-IR
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-IR
0
UPDATE-DR
1
1
0
Note
8. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 001-44701 Rev. *B
Page 11 of 21
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CY7C1303CV25
CY7C1306CV25
PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
2
1
1
1
0
0
0
Selection
TDI
Selection
TDO
Instruction Register
31 30
Identification Register
Circuitry
Circuitry
29
.
.
2
.
106
.
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics
Over the Operating Range [9, 10, 11]
Parameter
VOH1
Description
Output HIGH Voltage
Test Conditions
IOH = −2.0 mA
Min
1.7
2.1
Max
Unit
V
V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
IOH = −100 μA
IOL = 2.0 mA
IOL = 100 μA
0.7
0.2
V
V
1.7
–0.3
–5
VDD + 0.3
0.7
V
VIL
Input LOW Voltage
V
IX
Input and Output Load Current
GND ≤ VI ≤ VDD
5
μA
Notes
9. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.
10. Overshoot: V (AC) < V + 0.85V (Pulse width less than t /2), Undershoot: V (AC) > 1.5V (Pulse width less than t /2).
−
IH
DDQ
CYC
IL
CYC
11. All Voltage referenced to Ground.
Document #: 001-44701 Rev. *B
Page 12 of 21
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CY7C1303CV25
CY7C1306CV25
PRELIMINARY
TAP AC Switching Characteristics
Over the Operating Range [12, 13]
Parameter
Description
Min
Max
Unit
ns
tTCYC
TCK Clock Cycle Time
50
tTF
TCK Clock Frequency
TCK Clock HIGH
TCK Clock LOW
20
MHz
ns
tTH
20
20
tTL
ns
Setup Times
tTMSS
tTDIS
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
10
10
10
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
10
10
10
ns
ns
ns
tCH
Capture Hold after Clock Rise
Output Times
tTDOV
tTDOX
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
20
ns
ns
0
TAP Timing and Test Conditions
Figure 2 shows the TAP timing and test conditions. [13]
Figure 2. TAP Timing and Test Conditions
1.25V
50
ALL INPUT PULSES
2.5V
Ω
1.25V
TDO
0V
Z = 50
Ω
0
C = 20 pF
L
t
t
TH
TL
GND
(a)
Test Clock
TCK
t
TCYC
t
TMSH
t
TMSS
Test Mode Select
TMS
t
TDIS
t
TDIH
Test Data In
TDI
Test Data Out
TDO
t
TDOV
t
TDOX
Notes
12. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
13. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.
R
F
Document #: 001-44701 Rev. *B
Page 13 of 21
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CY7C1303CV25
CY7C1306CV25
PRELIMINARY
Identification Register Definitions
Value
Instruction Field
Description
CY7C1303CV25
000
CY7C1306CV25
000
Revision Number (31:29)
Cypress Device ID (28:12)
Cypress JEDEC ID (11:1)
Version number.
01011011010010101
00000110100
01011011010100101
00000110100
Defines the type of SRAM.
Allows unique identification of
SRAM vendor.
ID Register Presence (0)
1
1
Indicates the presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size
Instruction
Bypass
3
1
ID
32
107
Boundary Scan
Instruction Codes
Instruction
EXTEST
Code
000
Description
Captures the input and output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the input and output ring contents. Places the boundary scan register between TDI
and TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document #: 001-44701 Rev. *B
Page 14 of 21
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CY7C1303CV25
CY7C1306CV25
PRELIMINARY
Boundary Scan Order
Bit #
0
Bump ID
6R
Bit #
Bump ID
11H
10G
9G
Bit #
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Bump ID
7B
6B
6A
5B
5A
4A
5C
4B
3A
1H
1A
2B
3B
1C
1B
3D
3C
1D
2C
3E
2D
2E
1E
2F
Bit #
81
Bump ID
3G
2G
1J
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
1
6P
82
2
6N
83
3
7P
11F
11G
9F
84
2J
4
7N
85
3K
3J
5
7R
86
6
8R
10F
11E
10E
10D
9E
87
2K
1K
2L
7
8P
88
8
9R
89
9
11P
10P
10N
9P
90
3L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
91
1M
1L
10C
11D
9C
92
93
3N
3M
1N
2M
3P
2N
2P
1P
3R
4R
4P
5P
5N
5R
10M
11N
9M
94
9D
95
11B
11C
9B
96
9N
97
11L
11M
9L
98
10B
11A
Internal
9A
99
100
101
102
103
104
105
106
10L
11K
10K
9J
8B
7C
9K
6C
3F
10J
11J
8A
1G
1F
7A
Document #: 001-44701 Rev. *B
Page 15 of 21
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CY7C1303CV25
CY7C1306CV25
PRELIMINARY
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V
Latch-up Current ................................................... > 200 mA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with Power Applied.. –55°C to +125°C
Supply Voltage on VDD Relative to GND........–0.5V to +3.6V
Supply Voltage on VDDQ Relative to GND.......–0.5V to +VDD
DC Applied to Outputs in High-Z ........ –0.5V to VDDQ + 0.5V
DC Input Voltage [10].............................. –0.5V to VDD + 0.5V
Operating Range
Ambient
[14]
[14]
Range
VDD
VDDQ
Temperature (TA)
Commercial
Industrial
0°C to +70°C
2.5 ± 0.1V
1.4V to
1.9V
–40°C to +85°C
Electrical Characteristics
DC Electrical Characteristics
Over the Operating Range [11]
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min
2.4
Typ
Max
Unit
2.5
1.5
2.6
V
V
VDDQ
VOH
1.4
1.9
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage [10]
Input LOW Voltage [10, 17]
Note 15
Note 16
VDDQ/2 – 0.12
VDDQ/2 – 0.12
VDDQ – 0.2
VSS
VDDQ/2 + 0.12
V
VOL
VDDQ/2 + 0.12
V
VOH(LOW)
VOL(LOW)
VIH
IOH = −0.1 mA, Nominal Impedance
VDDQ
V
IOL = 0.1 mA, Nominal Impedance
0.2
V
VREF + 0.1
–0.3
VDDQ + 0.3
V
VIL
VREF – 0.1
V
VREF
IX
Input Reference Voltage [18] Typical Value = 0.75V
0.68
0.75
0.95
5
V
Input Leakage Current
Output Leakage Current
VDD Operating Supply
GND ≤ VI ≤ VDDQ
−5
μA
μA
mA
mA
IOZ
GND ≤ VI ≤ VDDQ, Output Disabled
VDD = Max, IOUT = 0 mA, f = fMAX = 1/tCYC
−5
5
[19]
IDD
500
240
ISB1
Automatic Power Down
Current
Max VDD, Both Ports Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC, Inputs Static
AC Electrical Characteristics
Over the Operating Range
Parameter
Description
Input HIGH Voltage
Input LOW Voltage
Test Conditions
Min
VREF + 0.2
–
Typ
–
Max
–
Unit
V
VIH
VIL
–
VREF – 0.2
V
Notes
14. Power up: Assumes a linear ramp from 0V to V (min) within 200 ms. During this time V < V and V
< V
.
DD
DD
IH
DD
DDQ
15. Output are impedance controlled. I
=
−
(V
/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.
/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.
OH
DDQ
16. Output are impedance controlled. I = (V
OL
DDQ
17. This spec is for all inputs except C and C Clock. For C and C Clock, V (Max.) = V
– 0.2V
REF
IL
18. V
(min) = 0.68V or 0.46V
, whichever is larger, V
(max) = 0.95V or 0.54V
, whichever is smaller.
REF
DDQ
REF
DDQ
19. The operation current is calculated with 50% read cycle and 50% write cycle.
Document #: 001-44701 Rev. *B
Page 16 of 21
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CY7C1303CV25
CY7C1306CV25
PRELIMINARY
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
CIN
Description
Input Capacitance
Test Conditions
Max
Unit
pF
TA = 25°C, f = 1 MHz, VDD = 2.5V, VDDQ
=
5
6
7
1.5V
CCLK
Clock Input Capacitance
Output Capacitance
pF
CO
pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
Test Conditions
165 FBGA Package
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, in accordance with
EIA/JESD51.
16.7
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
6.5
°C/W
Figure 3. AC Test Loads and Waveforms
V
REF = 0.75V
0.75V
VREF
VREF
0.75V
R = 50Ω
OUTPUT
[20]
ALL INPUT PULSES
1.25V
Z = 50Ω
0
OUTPUT
Device
Under
Test
R = 50Ω
L
0.75V
Device
Under
0.25V
5 pF
VREF = 0.75V
Slew Rate = 2 V/ns
ZQ
Test
ZQ
RQ =
RQ =
250Ω
250Ω
INCLUDING
JIG AND
SCOPE
(a)
(b)
Note
20. Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75V, V
= 0.75V, RQ = 250Ω, V
= 1.5V, input
REF
DDQ
pulse levels of 0.25V to 1.25V, and output loading of the specified I /I and load capacitance shown in (a) of AC Test Loads and Waveforms.
OL OH
Document #: 001-44701 Rev. *B
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CY7C1303CV25
CY7C1306CV25
PRELIMINARY
Switching Characteristics
Over the Operating Range [20]
167 MHz
Unit
Min Max
Cypress Consortium
Parameter Parameter
Description
tPOWER
VDD(Typical) to the First Access Read or Write [21]
10
μs
Cycle Time
tCYC
tKH
tKHKH
K Clock and C Clock Cycle Time
6.0
2.4
2.4
ns
ns
ns
ns
ns
tKHKL
tKLKH
tKHKH
tKHCH
Input Clock (K/K and C/C) HIGH
–
–
tKL
Input Clock (K/K and C/C) LOW
tKHKH
tKHCH
K Clock Rise to K Clock Rise and C to C Rise (rising edge to rising edge)
K/K Clock Rise to C/C Clock Rise (rising edge to rising edge)
2.7 3.3
0
2.0
Setup Times
tSA
tSC
tSD
tSA
tSC
tSD
Address Setup to Clock (K/K) Rise
0.7
0.7
0.7
–
–
–
ns
ns
ns
Control Setup to Clock (K/K) Rise (RPS, WPS, BWS0, BWS1)
D[X:0] Setup to Clock (K/K) Rise
Hold Times
tHA
tHC
tHD
tHA
tHC
tHD
Address Hold after Clock (K/K) Rise
0.7
0.7
0.7
–
–
–
ns
ns
ns
Control Hold after Clock (K/K) Rise (RPS, WPS, BWS0, BWS1)
D[X:0] Hold after Clock (K/K) Rise
Output Times
tCO
tCHQV
C/C Clock Rise (or K/K in Single Clock Mode) to Data Valid
Data Output Hold after Output C/C Clock Rise (Active to Active)
Clock (C/C) Rise to High-Z (Active to High-Z) [22, 23]
Clock (C/C) Rise to Low-Z [22, 23]
–
1.2
–
2.5
–
ns
ns
ns
ns
tDOH
tCHZ
tCLZ
tCHQX
tCHZ
tCLZ
2.5
–
1.2
Notes
21. This part has a voltage regulator that steps down the voltage internally; t
is the time that the power is supplied above V minimum initially before a read or write
DD
POWER
operation is initiated.
22. t
, t
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ± 100 mV from steady state voltage.
CHZ CLZ
23. At any voltage and temperature t
is less than t
and t
less than t
.
CHZ
CLZ
CHZ
CO
Document #: 001-44701 Rev. *B
Page 18 of 21
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CY7C1303CV25
CY7C1306CV25
PRELIMINARY
Switching Waveforms
Figure 4. Switching Waveforms[24, 25, 26]
READ
1
W RITE
2
READ
3
WRITE
4
READ
5
WRITE
6
NOP
7
W RITE
NOP
9
8
10
K
t
t
t
t
KHKH
KH
KL
CYC
K
RPS
tSC
tHC
W PS
A
A5
A6
A0
A1
A2
A3
A4
t
t
t
t
SA HA
SA HA
D
Q
D10
D11
D30
D31
D50
D51
D60
D61
t
t
HD
t
SD
HD
t
SD
Q00
Q01
Q20
Q21
Q40
Q41
t
CHZ
t
t
t
DOH
DOH
CLZ
t
t
t
t
CO
KHCH
KHCH
CO
C
C
t
t
t
KHKH
tCYC
KH
KL
DON’T CARE
UNDEFINED
Notes
24. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.
25. Outputs are disabled (High-Z) one clock cycle after a NOP.
26. In this example, if address A0 = A1, then data Q00 = D10 and Q01 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document #: 001-44701 Rev. *B
Page 19 of 21
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CY7C1303CV25
CY7C1306CV25
PRELIMINARY
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
167 CY7C1303CV25-167BZC
CY7C1306CV25-167BZC
CY7C1303CV25-167BZXC
CY7C1306CV25-167BZXC
CY7C1303CV25-167BZI
CY7C1306CV25-167BZI
CY7C1303CV25-167BZXI
CY7C1306CV25-167BZXI
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
Commercial
Industrial
Package Diagram
Figure 5. 165-Ball FBGA (13 x 15 x 1.4 mm)
BOTTOM VIEW
PIN 1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
PIN 1 CORNER
-0.06
Ø0.50 (165X)
+0.14
1
2
3
4
5
6
7
8
9
10
11
11 10
9
8
7
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
A
1.00
5.00
10.00
13.00 0.10
B
13.00 0.10
B
0.15(4X)
NOTES :
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g
JEDEC REFERENCE : MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
SEATING PLANE
C
51-85180 *A
Document #: 001-44701 Rev. *B
Page 20 of 21
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CY7C1303CV25
CY7C1306CV25
PRELIMINARY
Document History Page
Document Title: CY7C1303CV25/CY7C1306CV25, 18-Mbit Burst of 2 Pipelined SRAM with QDR™ Architecture
Document Number: 001-44701
Submission
Date
Orig. of
Change
Rev. ECN No.
** 2192568
Description of Change
See ECN
See ECN
07/31/09
VKN/PYRS New datasheet
*A 2507779
*B 2746930
VKN/PYRS Corrected JTAG ID code
NJY
Post to external web site
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
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© Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-44701 Rev. *B
Revised July 31, 2009
Page 21 of 21
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, NEC, and Samsung. All product and company names mentioned in this document are
the trademarks of their respective holders.
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