CY7C1304V25-167BZC [CYPRESS]
QDR SRAM, 128KX72, 2.5ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, 1 MM PITCH, FBGA-165;
| 型号： | CY7C1304V25-167BZC |
| 厂家： | 
CYPRESS |
| 描述： | QDR SRAM, 128KX72, 2.5ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, 1 MM PITCH, FBGA-165 时钟 静态存储器 内存集成电路 |
| 文件： | 总24页 (文件大小：406K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1304V25
9-Mb Pipelined SRAM with QDR™ Architecture
Features
Functional Description
• Separate independent Read and Write data ports
— Supports concurrent transactions
The CY7C1304V25 is a 2.5V Synchronous Pipelined SRAM
equipped with QDR architecture. QDR architecture consists of
two separate ports to access the memory array. The Read port
has dedicated Data Outputs to support Read operations and
the Write Port has dedicated Data Inputs to support Write op-
erations. QDR architecture has separate data inputs and data
outputs to completely eliminate the need to “turn-around” the
data bus required with common I/O devices. Access to each
port is accomplished through a common address bus. Ad-
dresses for Read and Write addresses are latched on alter-
nate rising edges of the input (K)[1] clock. Accesses to the
CY7C1304V25 Read and Write ports are completely indepen-
dent of one another. In order to maximize data throughput,
both Read and Write ports are equipped with Double Data
Rate (DDR) interfaces. Each address location is associated
with 4 18-bit words that burst sequentially into or out of the
device. Since data can be transferred into and out of the de-
vice on every rising edge of both input clocks (K/K[1] and C/C)
memory bandwidth is maximized while simplifying system de-
sign by eliminating bus “turn-arounds”.
• 167 MHz Clock for high bandwidth
— 2.5 ns Clock-to-Valid access time
• 4-Word burst for reducing address bus frequency
• DoubleDataRate(DDR)interfacesonbothRead&Write
Ports (data transferred at 333 MHz) @167 MHz
• Two input clocks (K and K)[1] for precise DDR timing
— SRAM uses rising edges only
• Two output clocks (C and C) accounts for clock skew
and flight time mis-matches
• Single multiplexed address input bus latches address
inputs for both READ and WRITE ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 2.5VcorepowersupplywithHSTLInputsandOutputs[1]
• 13x15 mm 1.0 mm pitch fBGA package, 165 ball (11x15
matrix)
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V-1.9V)
• JTAG Interface
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K[1] input clocks. Data outputs pass through output
registers controlled by the C or C input clocks. Writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Logic Block Diagram
D
[17:0]
18
Write Write Write
Write
Reg Reg Reg Reg
Address
Register
A
Address
Register
(16:0)
A
(16:0)
17
17
[1]
[1]
K
K
CLK
Gen.
RPS
Control
Logic
C
C
Read Data Reg.
72
36
Vref
Reg.
Reg.
Reg.
18
WPS
BWS
Control
Logic
36
[0:1]
Q
[17:0]
18
Selection Guide
7C1304V25-167
7C1304V25-133
7C1304V25-100
Maximum Operating Frequency (MHz)
167
450
133
350
100
230
Maximum Operating Current (mA)
Note:
1. K and K inputs require VIH to be greater than VREF + 0.5V and VIL to be less than VREF - 0.5. This is a subset of JEDEC standards for HSTL I/Os.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05167 Rev. *A
Revised August 15, 2002
CY7C1304V25
Pin Configuration
CY7C1304V25
(Top View)
1
2
3
4
5
6
7
8
9
10
11
A
NC
Gnd/
144M
NC/
36M
WPS
BWS1
K[1]
NC
RPS
NC/
18M
Gnd/
72M
NC
B
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TDO
Q9
D9
A
NC
K[1]
NC
BWS0
A
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
Q7
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
C
D
E
NC
D10
Q10
Q11
D12
Q13
VDDQ
D14
Q14
D15
D16
Q16
Q17
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
D11
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
NC
D6
F
Q12
D13
VREF
NC
NC
NC
VREF
Q4
G
H
J
K[1]
L
NC
D3
Q15
NC
NC
Q1
M
N
P
D17
NC
NC
D0
A
C
A
R
TCK
A
A
C
A
A
TMS
Document #: 38-05167 Rev. *A
Page 2 of 24
CY7C1304V25
Pin Definitions
Name
I/O
Description
D[17:0]
Input-
Synchronous
Data input signals, sampled on the rising edge of K and K[1] clocks during valid write
operations.
WPS
Input-
Synchronous
Write Port Select, active LOW. Sampled on the rising edge of the K[1] clock. When
asserted active, a write operation is initiated. Deasserting will deselect the Write port.
Deselecting the Write port will cause D[17:0] to be ignored.
BWS0, BWS1
Input-
Synchronous
Byte Write Select 0 and 1, active LOW. Sampled on the rising edge of the K and K[1]
clocks during write operations. Used to select which byte is written into the device during
the current portion of the write operations. Bytes not written remain unaltered.BWS0
controls D[8:0] while BWS1 controls D[17:9]. BWS0 and BWS1 are sampled on the same
edge as D[17:0]. Deselecting a Byte Write Select will cause the corresponding byte of
data to be ignored and not written into the device.
A
Input-
Synchronous
Address Inputs. Sampled on the rising edge of the K[1] clock during active read and
write operations. These address inputs are multiplexed for both Read and Write oper-
ations. Internally, the device is organized 128K x 72. Therefore, only 17 address inputs
are needed to access the entire memory array.These inputs are ignored when the ap-
propriate port is deselected.
Q[17:0]
Outputs-
Synchronous
Data Output signals. These pins drive out the requested data during a Read operation.
Valid data is driven out on the rising edge of both the C and C clocks during Read
operations or K and K[1]. when in single clock mode. When the Read port is deselected,
Q[17:0] are automatically three-stated.
RPS
Input-
Synchronous
Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock
(K)[1]. When active, a Read operation is initiated. Deasserting will cause the Read port
to be deselected. When deselected, the pending access is allowed to complete and the
output drivers are automatically three-stated following the next rising edge of the C
clock. The CY7C1304V25 is organized internally as 128K x 72. Each read access con-
sists of a burst of four sequential 18-bit transfers.
C
Input-Clock
Input-Clock
Input-Clock
Positive Output Clock Input. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See application example for further details.
C
Negative Output Clock Input. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See application example for further details.
K[1]
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs
to the device and to drive out data through Q[17:0] when in single clock mode. All ac-
cesses are initiated on the rising edge of K.
K[1]
ZQ
Input-Clock
Input
Negative Input Clock Input. K[1] is used to capture synchronous inputs being present-
ed to the device and to drive out data through Q[17:0] when in single clock mode.
Output Impedance Matching Input. This input is used to tune the device outputs to
the system data bus impedance. Q[17:0] output impedance are set to 0.2 x RQ, where
RQ is a resistor connected between ZQ and ground. Alternately, this pin can be con-
nected directly to VDD, which enables the minimum impedance mode. This pin cannot
be connected directly to GND or left unconnected.
TDO
Output
Input
Input
Input
Input
Input
Input
Input
TDO for JTAG.
TCK
TCK pin for JTAG.
TDI
TDI pin for JTAG.
TMS
TMS pin for JTAG.
NC/18M
NC/36M
GND/72M
GND/144M
Address expansion for 18M. This is not connected to the die.
Address expansion for 36M. This is not connected to the die.
Address expansion for 72M. This should be tied LOW on the CY7C1304V25
Address expansion for 144M. This should be tied LOW on the CY7C1304V25
Document #: 38-05167 Rev. *A
Page 3 of 24
CY7C1304V25
Pin Definitions (continued)
Name
I/O
Description
VREF
VDD
VSS
Input-
Reference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs[1]
and Outputs as well as A/C measurement points.
Power Supply
Power supply inputs to the core of the device. Should be connected to 2.5V power
supply.
Ground
Ground for the device. Should be connected to ground of the system.
VDDQ
Power Supply
Power supply inputs for the outputs of the device. Should be connected to 1.5V
power supply.
NC
NC
No connect
so will pipeline the data flow such that data is transferred out
of the device on every rising edge of the output clocks (C and
C or K and K[1] when in single clock mode).
Introduction
Functional Overview
The CY7C1304V25 is a synchronous pipelined Burst SRAM
equipped with both a Read Port and a Write Port. The Read
port is dedicated to Read operations and the Write Port is ded-
icated to Write operations. Data flows into the SRAM through
the Write port and out through the Read Port. The
CY7C1304V25 multiplexes the address inputs in order to min-
imize the number of address pins required. By having separate
Read and Write ports, the CY7C1304V25 completely elimi-
nates the need to “turn-around” the data bus and avoids any
possible data contention, thereby simplifying system design.
Each access consists of 4 18-bit data transfers in two clock
cycles.
When the read port is deselected, the CY7C1304V25 will first
complete the pending read transactions. Synchronous internal
circuitry will automatically three-state the outputs following the
next rising edge of the Negative Output Clock (C). This will
allow for a seamless transition between devices without the
insertion of wait states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the Positive Input Clock (K)[1]. On the following
K[1] clock rise the data presented to D[17:0] is latched and
stored into the lower 18-bit Write Data register provided
BWS[1:0] are both asserted active. On the subsequent rising
edge of the Negative Input Clock (K)[1] the information pre-
sented to D[17:0] is also stored into the Write Data Register
provided BWS[1:0] are both asserted active. This process con-
tinues for one more cycle until 4 18-bit words (a total of 72 bits)
of data are stored in the SRAM. The 72 bits of data are then
written into the memory array at the specified location. There-
fore, Write accesses to the device can not be initiated on two
consecutive K[1] clock rises. The internal logic of the device will
ignore the second Write request. Write accesses can be initi-
ated on every other rising edge of the Positive Input Clock
(K)[1]. Doing so will pipeline the data flow such that 18-bits of
data can be transferred into the device on every rising edge of
Accesses for both ports are initiated on the Positive Input
Clock (K)[1]. All synchronous input timing is referenced from
the rising edge of the input clocks (K and K)[1] and all output
timing is referenced to the output clocks (C and C or K and K[1]
when in single clock mode).
All synchronous data inputs (D[17:0]) inputs pass through input
registers controlled by the input clocks (K and K)[1]. All syn-
chronous data outputs (Q[17:0]) outputs pass through output
registers controlled by the rising edge of the output clocks (C
and C or K and K[1] when in single clock mode).
All synchronous control (RPS, WPS, BWS0, BWS1) inputs
pass through input registers controlled by the rising edge of
the input clocks (K and K[1], C and C).
the input clocks (K and K)[1]
.
When deselected, the write port will ignore all inputs after the
pending Write operations have been completed.
Read Operations
The CY7C1304V25 is organized internally as a 128Kx72
SRAM. Accesses are completed in a burst of four sequential
18-bit data words. Read operations are initiated by asserting
Byte Write Operations
Byte Write operations are supported by the CY7C1304V25. A
write operation is initiated as described in the Write Operation
section above. The bytes that are written are determined by
BWS0 and BWS1 which are sampled with each set of 18-bit
data word. Asserting the appropriate Byte Write Select input
during the data portion of a write will allow the data being pre-
sented to be latched and written into the device. De-asserting
the Byte Write Select input during the data portion of a write
will allow the data stored in the device for that byte to remain
unaltered. This feature can be used to simplify READ/MODI-
FY/WRITE operations to a Byte Write operation.
RPS active at the rising edge of the Positive Input Clock (K)[1]
.
The address presented to Address inputs are stored in the
Read address register. Following the next K[1] clock rise the
corresponding lowest order 18-bit word of data is driven onto
the Q[17:0] using C as the output timing reference. On the sub-
sequent rising edge of C the next 18-bit data word is driven
onto the Q[17:0]. This process continues until all four 18-bit data
words have been driven out onto Q[17:0]. The requested data
will be valid 2.5ns from the rising edge of the output clock (C
or C, 167MHz device). In order to maintain the internal logic,
each read access must be allowed to complete. Each Read
access consists of 4 18-bit data words and takes 2 clock cycles
to complete. Therefore, Read accesses to the device can not
be initiated on two consecutive K[1] clock rises. The internal
logic of the device will ignore the second Read request. Read
accesses can be initiated on every other K[1] clock rise. Doing
Single Clock Mode
The CY7C1304V25 can be used with a single clock that con-
trols both the input and output registers. In this mode the de-
vice will recognize only a single pair of input clocks (K and K)[1]
that control both the input and output registers. This operation
Document #: 38-05167 Rev. *A
Page 4 of 24
CY7C1304V25
is identical to the operation if the device had zero skew be-
tween the K/K[1] and C/C clocks. All timing parameters remain
the same in this mode. To use this mode of operation, the user
must tie C and C HIGH at power on. This function is a strap
option and not alterable during device operation.
consecutive cycles). Therefore, asserting both port selects ac-
tive from a deselected state will result in alternating
Read/Write operations being initiated, with the first access be-
ing a Read.
Depth Expansion
Concurrent Transactions
The CY7C1304V25 has a Port Select input for each port. This
allows for easy depth expansion. Both Port Selects are sam-
pled on the rising edge of the Positive Input Clock only (K)[1].
Each port select input can deselect the specified port. Dese-
lecting a port will not affect the other port. All pending transac-
tions (Read and Write) will be completed prior to the device
being deselected.
The Read and Write ports on the CY7C1304V25 operate com-
pletely independently of one another. Since each port latches
the address inputs on different clock edges, the user can Read
or Write to any location, regardless of the transaction on the
other port. If the ports access the same location at the same
time, the SRAM will deliver the most recent information asso-
ciated with the specified address location. This includes for-
warding data from a Write cycle that was initiated on the pre-
vious K[1] clock rise.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±10% is between 175Ω and 350Ω, with
VDDQ=1.5V. The output impedance is adjusted every 1024 cy-
cles to adjust for drifts in supply voltage and temperature.
Read accesses and Write access must be schedule such that
one transaction is initiated on any clock cycle. If both ports are
selected on the same K[1] clock rise, the arbitration depends
on the previous state of the SRAM. If both ports were dese-
lected, the Read port will take priority. If a Read was initiated
on the previous cycle, the Write port will assume priority (since
Read operations can not be initiated on consecutive cycles).
If a Write was initiated on the previous cycle, the Read port will
assume priority (since Write operations can not be initiated on
Document #: 38-05167 Rev. *A
Page 5 of 24
CY7C1304V25
Application Example
VTERM = VREF/2
SRAM #1
SRAM #4
Q
D
Q
D
18
18
18
R = 50Ω
Memory
18
Controller
72
Q
17
17
Din
Add.
Cntr.
72
2
2
CLK/CLK (input)
CLK/CLK (output)
R = 50Ω
VT = VREF/2
Document #: 38-05167 Rev. *A
Page 6 of 24
CY7C1304V25
Truth Table[2, 3, 4, 5, 6]
Operation
K[1]
RPS
WPS
DQ
DQ
DQ
DQ
Write Cycle:
L-H
H[7]
L[8]
D(A+00)at
K(t+1) ↑
D(A+01) at
K(t+1) ↑
D(A+10) at
K(t+2) ↑
D(A+11) at
K(t+2) ↑
Load address, input write
data on 2 consecutive K[1]
and K[1] rising edges.
Read Cycle:
L-H
L[8]
X
Q(A+00) at
Q(A+01) at
Q(A+10) at
Q(A+11) at
Load address, read data
on 2 consecutive C and C
rising edges.
C(t+1) ↑
C(t+1) ↑
C(t+2) ↑
C(t+2) ↑
NOP: No Operation
L-H
H
X
H
X
High-Z
High-Z
High-Z)
High-Z
Standby: Clock Stopped
Stopped
Previous
State
Previous
State
Previous
State
Previous
State
Note:
2. X=Don’t Care”, H=Logic HIGH, L=Logic LOW ↑represents rising edge.
3. Device will power-up deselected and the outputs in a three-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A+00, A+01, A+10 and A+11 represents the addresses sequence in
the burst.
[1]
5. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
[1]
6. It is recommended that K = K# and C = C# when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
7. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
[1]
[1]
8. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device
will ignore the second Read request.
Document #: 38-05167 Rev. *A
Page 7 of 24
CY7C1304V25
Write Cycle Descriptions[2, 9]
BWS0
BWS1
K[1]
L-H
K[1]
Comments
L
L
-
During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the
device.
L
L
L
H
H
L
-
L-H
-
During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the
device.
L-H
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into
the device. D[17:9] will remain unaltered.
L
-
L-H
-
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into
the device. D[17:9] will remain unaltered.
H
H
H
L-H
-
During the Data portion of a Write sequence, only the upper byte (D[17:9]) is written into
the device. D[8:0] will remain unaltered.
L
L-H
During the Data portion of a Write sequence, only the upper byte (D[17:9]) is written into
the device. D[8:0] will remain unaltered.
H
H
L-H
-
-
No data is written into the device during this portion of a write operation.
No data is written into the device during this portion of a write operation.
H
L-H
Note:
9. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0 and BWS1 can be altered on different portions of a write cycle,
as long as the set-up and hold requirements are achieved.
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
IEEE 1149.1 Serial Boundary Scan (JTAG -
FBGA Only)
Test Data-In (TDI)
The CY7C1340 incorporates a serial boundary scan test ac-
cess port (TAP) in the FBGA package only. The TQFP pack-
age does not offer this functionality. This port operates in ac-
cordance with IEEE Standard 1149.1-1900, but does not have
the set of functions required for full 1149.1 compliance. These
functions from the IEEE specification are excluded because
their inclusion places an added delay in the critical speed path
of the SRAM. Note that the TAP controller functions in a man-
ner that does not conflict with the operation of other devices
using 1149.1 fully compliant TAPs. The TAP operates using
JEDEC standard 2.5V I/O logic levels.
The TDI pin is used to serially input information into the regis-
ters and can be connected to the input of any of the registers.
The register between TDI and TDO is chosen by the instruc-
tion that is loaded into the TAP instruction register. For infor-
mation on loading the instruction register, see the TAP Con-
troller State Diagram. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Test Data Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (See Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.
Disabling the JTAP Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(Vss) to prevent clocking of the device. TDI and TMS are in-
ternally pulled up and may be unconnected. They may alter-
nately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the oper-
ation of the device.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is oper-
ating. At power-up, the TAP is reset internally to ensure that
TDO comes up in a high-Z state.
Test Access Port (TAP)—Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test circuit-
ry. Only one register can be selected at a time through the
instruction registers. Data is serially loaded into the TDI pin on
the rising edge of TCK. Data is output on the TDO pin on the
falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
Document #: 38-05167 Rev. *A
Page 8 of 24
CY7C1304V25
Instruction Register
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP control-
ler needs to be moved into the Update-IR state.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the ID-
CODE instruction. It is also loaded with the IDCODE instruc-
tion if the controller is placed in a reset state as described in
the previous section.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be ex-
ecuted whenever the instruction register is loaded with all 0s.
EXTEST is not implemented in the CY7C1304V25 TAP con-
troller, and therefore this device is not compliant to the 1149.1
standard.
When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Bypass Register
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE / PRELOAD instruction
has been loaded.
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or when-
ever the TAP controller is given a test logic reset state.
Boundary Scan Register
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state.
SAMPLE/PRELOAD
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the CY7C1304V25 TAP controller is not fully 1149.1 compliant.
When the SAMPLE/PRELOAD instructions loaded into the in-
struction register and the TAP controller in the Capture-DR
state, a snapshot of data on the inputs and output pins is cap-
tured in the boundary scan register.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register Defi-
nitions table.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possi-
ble that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
TAP Instruction Set
Eight different instructions are possible with the three-bit in-
struction register. All combinations are listed in the Instruction
Code table. Three of these instructions are listed as RE-
SERVED and should not be used. The other five instructions
are described in detail below.
To guarantee that the boundary scan register will capture the
correct value of a signal, he SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus
hold times (TCS and TCH). The SRAM clock inputs might not
be captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE / PRELOAD instruction. If
this is an issue, it is still possible to capture all other signals
and simply ignore the value of the K, K[1], C and C captured in
the boundary scan register.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller can-
not be used to load address, data or control signals into the
SRAM and cannot preload the Input or output buffers. The
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE / PRELOAD;
rather it performs a capture of the Inputs and Output ring when
these instructions are executed.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the bound-
ary scan register between the TDI and TDO pins.
Document #: 38-05167 Rev. *A
Page 9 of 24
CY7C1304V25
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the Up-
date-DR state while performing a SAMPLE / PRELOAD in-
struction will have the same effect as the Pause-DR com-
mand.
tage of the BYPASS instruction is that it shortens the boundary
scan path when multiple devices are connected together on a
board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Bypass
When the BYPASS instruction is loaded in the instruction reg-
ister and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The advan-
Document #: 38-05167 Rev. *A
Page 10 of 24
CY7C1304V25
TAP Controller State Diagram[10]
TEST-LOGIC
1
RESET
0
1
1
1
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note:
10. The 0/1 next to each state represents the value at TMS at the rising edge
of TCK.
Document #: 38-05167 Rev. *A
Page 11 of 24
CY7C1304V25
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
2
1
1
0
TDO
TDI
Instruction Register
29
31 30
.
.
2
0
0
Identification Register
.
68 .
.
.
2
1
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[11, 12, 13]
Parameter
VOH1
VOH2
VOL1
VOL2
VIH
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
IOH = −2.0 mA
Min.
1.7
Max.
Unit
V
V
IOH = −100 µA
IOL = 2.0 mA
IOL = 100 µA
2.1
0.7
0.2
V
V
1.7
–0.3
−5
VDD+0.3
0.7
V
VIL
Input LOW Voltage
V
IX
Input and OutputLoad Current
GND < VI < VDDQ
5
µA
11. All Voltage referenced to Ground.
12. Overshoot: VIH(AC)<VDD+1.5V for t<tTCYC/2, Undershoot VIL(AC)<0.5V for t<tTCYC/2, Power-up: VIH<2.6V and VDD<2.4V and VDDQ<1.4V for t<200ms.
13. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
Document #: 38-05167 Rev. *A
Page 12 of 24
CY7C1304V25
TAP AC Switching Characteristics Over the Operating Range[14, 15]
Param
tTCYC
tTF
Description
Min.
Max
Unit
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
100
10
MHz
ns
tTH
40
40
tTL
TCK Clock LOW
ns
Set-up Times
tTMSS
tTDIS
tCS
TMS set-up to TCK clock rise
10
10
10
ns
ns
ns
TDI set-up to TCK clock rise
Capture set-up to TCK rise
Hold Times
tTMSH
tTDIH
tCH
TMS Hold after TCK clock rise
10
10
10
ns
ns
ns
TDI Hold after clock rise
Capture Hold after clock rise
Output Times
tTDOV
TCK Clock LOW to TDO valid
TCK Clock LOW to TDO invalid
20
ns
ns
tTDOX
0
Notes:
14.
tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
15. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document #: 38-05167 Rev. *A
Page 13 of 24
CY7C1304V25
TAP Timing and Test Conditions[15]
1.25V
50Ω
ALL INPUT PULSES
TDO
2.5V
Z =50Ω
0
1.25V
C = 20 pF
L
0V
GND
(a)
tTL
tTH
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
tTDOX
Document #: 38-05167 Rev. *A
Page 14 of 24
CY7C1304V25
Identification Register Definitions
Value
CY7C1304V25
000
Instruction Field
Description
Revision Number
(31:29)
Version number.
Cypress Device ID
(28:12)
01011010011010110
Defines the type of SRAM.
Cypress JEDEC ID
(11:1)
00000110100
1
Allows unique identification of SRAM
vendor.
ID Register Presence
(0)
Indicate the presence of an ID register.
Scan Register Sizes
Register Name
Instruction
Bit Size
3
1
Bypass
ID
32
69
Boundary Scan
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output ring contents. Places the boundary scan register
between the TDI and TDO. This instruction is not 1149.1 compliant. The
EXTEST command implemented by the CY7C1304V25 device will NOT
place the output buffers into a HIGH-Z condition. If the output buffers
need to be HIGH-Z condition, this can be accomplished by deselecting
the Read port.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register be-
tween TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z
Captures the Input/Output contents. Places the boundary scan register be-
tween TDI and TDO. The SAMPLE Z command implemented by the
CY7C1304V25 device will place the output buffers into a HIGH-Z con-
dition.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect theSRAM operation. This instruction
does not implement 1149.1 preload function and is therefore not 1149.1
compliant.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
Document #: 38-05167 Rev. *A
Page 15 of 24
CY7C1304V25
Boundary Scan Order
Boundary Scan Order
Bit #
Signal Name
Bump ID
Bit #
Signal Name
Bump ID
1
C
6R
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
K
6B
2
C
6P
K[1]
6A
3
A
6N
BWS1
WPS
A
5A
4
A
7P
4A
5
A
7N
5C
6
A
7R
A
4B
7
A
8R
NC/36M(1)
GND/144M
Reserved
D9
3A
8
A
8P
2A
9
A
9R
1A (Don’t Care)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
10P
11P
11N
10M
11M
11L
10K
11K
11J
11H
10J
11G
11F
10E
11E
11D
10C
11C
11B
3B
2B
3C
3D
2D
3E
3F
2F
2G
3G
3J
Q9
D10
Q10
D11
Q11
D12
Q12
D13
Q13
D14
Q14
D15
Q15
D16
Q16
D17
Q17
A
ZQ
Q4
D5
3K
3L
Q5
D6
2L
Q6
3M
3N
2N
3P
3R
4R
4P
5P
5N
5R
D7
Q7
D8
Q8
Reserved
GND/72M
NC/18M(1)
A
12A (Don’t Care)
A
10A
9A
8B
7C
6C
8A
7B
A
A
A
A
A
NC (0)
RPS
BWS0
Document #: 38-05167 Rev. *A
Page 16 of 24
CY7C1304V25
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
Supply Voltage on VDD Relative to GND ....... –0.5V to +3.6V
Range Temperature[17]
VDD
VDDQ
DC Voltage Applied to Outputs
in High Z State[16]................................ –0.5V to VDDQ + 0.5V
Com’l
0°C to +70°C
2.5±100 mV
1.4V to 1.9V
DC Input Voltage[16]............................ –0.5V to VDDQ + 0.5V
Electrical Characteristics Over the Operating Range
Parameter
VDD
Description
Test Conditions
Min.
Max.
Unit
V
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
2.4
1.4
2.6
1.9
VDDQ
VOH
V
IOH = −2.0 mA, Nominal Impedance
VDDQ/2 + 0.3
VSS
VDDQ
V
VOL
IOL = 2.0 mA, Nominal Impedance
VDDQ/2 –
V
0.3
VIH
VIL
IX
Input HIGH Voltage
Input LOW Voltage[16]
Input Load Current
VREF + 0.1
VDDQ + 0.3
V
V
–0.3
−5
VREF – 0.1
GND < VI < VDDQ
5
5
µA
µA
IOZ
Output Leakage
Current
GND < VI < VDDQ, Output Disabled
−5
VREF
IDD
Input Reference Volt-
age
Typical Value = 0.75V
0.68
1.0
V
VDD Operating Supply VDD = Max., IOUT = 0 mA, 6.0-ns cycle, 167 MHz
450
350
230
100
80
mA
mA
mA
mA
mA
mA
f = fMAX = 1/tCYC
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
ISB1
Automatic
Power-Down
Current
Max. VDD, Both Ports De- 6.0-ns cycle, 167 MHz
selected, VIN > VIH or VIN
< VIL f = fMAX = 1/tCYC, In-
7.5-ns cycle, 133 MHz
puts Static
10-ns cycle, 100 MHz
60
Note:
16. Minimum voltage equals -2.0V for pulse duration less than 20 ns.
17. TA is the “instant on” case temperature.
Document #: 38-05167 Rev. *A
Page 17 of 24
CY7C1304V25
Capacitance[18]
Parameter
CIN
Description
Input Capacitance
Test Conditions
Max.
5
Unit
pF
TA = 25°C, f = 1 MHz,
VDD = 2.5V
VDDQ = 1.5V
CCLK
Clock Input Capacitance
Output Capacitance
6.5
4
pF
CO
pF
Note:
18. Tested initially and after any design or process change that may affect these parameters.
AC Test Loads and Waveforms
V
/2
DDQ
V
/2
DDQ
V
REF
V
V
/2
REF
R = 50Ω
[19]
DDQ
OUTPUT
ALL INPUT PULSES
1.25V
Z = 50Ω
0
OUTPUT
Device
Device
Under
Test
R = 50Ω
L
0.75V
0.25V
5 pF
Under
V
= 0.75V
REF
ZQ
ZQ
Test
RQ =
250
RQ =
250Ω
Ω
(a)
INCLUDING
JIG AND
SCOPE
(b)
Document #: 38-05167 Rev. *A
Page 18 of 24
CY7C1304V25
Switching Characteristics Over the Operating Range[20]
-167
-133
-100
Param
tCYC
tKH
Description
K[1] Clock and C Clock Cycle Time
Min. Max Min. Max Min. Max Unit
6.0
2.4
2.4
2.7
7.5
3.2
3.2
3.4
10.0
3.5
3.5
4.4
ns
ns
ns
ns
Input Clock (K/K[1] and C/C) HIGH
Input Clock (K/K[1] and C/C) LOW
tKL
tKHKH
K/K[1] Clock rise to K/K[1] Clock rise and C/C to C/C rise
(rising edge to rising edge)
3.3
4.1
5.4
tKHCH
tCO
K/K[1] Clock rise to C/C clock rise (rising edge to rising edge)
C/C Clock rise (or K/K[1] in single clock mode) to Data Valid[19]
Data Output Hold After Output C/C clock Rise (Active to Active)
0.0
1.2
2.0
2.5
0.0
1.2
2.5
3.0
0.0
1.2
3.0
3.0
ns
ns
ns
tDOH
Set-up Times
tSA
Address set-up to K[1] clock rise
tSC
0.7
0.7
0.8
0.8
1.0
1.0
ns
ns
Control set-up to clock (K, K[1], C, C) rise (RPS, WPS, BWS0,
BWS1)
tSD
D[17:0] set-up to clock (K and K)[1] rise
0.7
0.8
1.0
ns
Hold Times
tHA
Address Hold after clock (K and K)[1] rise
tHC
0.7
0.7
0.8
0.8
1.0
1.0
ns
ns
Control Hold after clock (K and K)[1] rise (RPS, WPS, BWS0,
BWS1)
tHD
D[17:0] Hold after clock (K and K)[1] rise
0.7
0.8
1.0
ns
Output Times
tCHZ
Clock (C and C) rise to High-Z (Active to High-Z)[20, 21]
tCLZ
Clock (C and C) rise to Low-Z[20, 21]
2.5
3.0
3.0
ns
ns
1.2
1.2
1.2
Note:
19. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref=0.75V, RQ=250Ω, VDDQ=1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads.
20. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
21. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO
.
Document #: 38-05167 Rev. *A
Page 19 of 24
CY7C1304V25
Switching Waveforms
Read/Deselect Sequence[22]
tCYC
tKHKH
tKL
tKHKH
K[1]
tKH
tKL
K[1]
tKH
tSA
tHA
A(16:0)
A
B
tSC
tHC
Deselect
RPS
tCLZ
Q(A+1)
Q(A+3)
Q(B+1)
Q(B+2) Q(B+3)
Q(A)
Q(A+2)
Q(B)
Data Out
tCO
tKHCH
tCHZ
C
C
tDOH
tCO
tDOH
tDOH
= UNDEFINED
= DON’T CARE
Note:
22. Device originally deselected.
Document #: 38-05167 Rev. *A
Page 20 of 24
CY7C1304V25
Switching Waveforms (continued)
Write/Deselect Sequence[23]
tCYC
tKL
K[1]
tKH
tKL
K[1]
tSD
tHD
A
A
B
tH
tSC
tHC
WPS
tHC
tSC
BWSx
D(A+3)
D(B)
D(B+1)
D(B+2)
D(B+3)
D(A)
D(A+2)
D(A+1)
Data In
tHD
tSD
= UNDEFINED
= DON’T CARE
Note:
23. C and C reference to Data Outputs and do not affect Write operations.BWSx LOW=Valid, Byte writes allowed, see Byte write table for details.
Document #: 38-05167 Rev. *A
Page 21 of 24
CY7C1304V25
Switching Waveforms (continued)
Read/Write/Deselect Sequence[24]
K[1]
K[1]
A
A
B
C
D
WPS
RPS
D[17:0]
D(B+1)
Q(A+2)
D(B+2)
Q(A+3)
D(B+3)
Q(C)
D(B)
D(D)
D(D+1)
Q(C+2)
D(D+2)
Q(C+3)
D(D+3)
Q(A+1)
Q[17:0]
Q(A)
Q(Q(C+1)
C
C
= UNDEFINED
= DON’T CARE
Note:
24. Read Port previously deselected. BWSx assumed active.
Document #: 38-05167 Rev. *A
Page 22 of 24
CY7C1304V25
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
Ordering Code
Package Type
13 x 15 mm FBGA
167
CY7C1304V25-167BZC/
CY7C1304V25-133BZC/
CY7C1304V25-100BZC/
BB165A
Commercial
133
100
Package Diagram
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*B
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC,
and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05167 Rev. *A
Page 23 of 24
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1304V25
Document Title: CY7C1304V25 9-Mb Pipelined SRAM with QDR™ Architecture
Document Number: 38-05167
Issue
Date
Orig. of
REV.
**
ECN NO.
110207
115923
Change Description of Change
10/03/01
08/19/02
SZV
RCS
Change from Spec number: 38-00925 to 38-05167
*A
Changed status from Advanced to Final.
Highlighted K and K VIH and VIL requirements.
Document #: 38-05167 Rev. *A
Page 24 of 24
相关型号：
CY7C1305AV25-167BZCT
QDR SRAM, 1MX18, 2.5ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, 1 MM PITCH, FBGA-165
CYPRESS
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