CY7C1308DV25C-250BZC [CYPRESS]
9 Mbit DDR I SRAM 4-Word Burst Architecture;
| 型号： | CY7C1308DV25C-250BZC |
| 厂家： | 
CYPRESS |
| 描述： | 9 Mbit DDR I SRAM 4-Word Burst Architecture 双倍数据速率 静态存储器 |
| 文件： | 总18页 (文件大小：675K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
CY7C1308DV25C
9 Mbit DDR I SRAM 4-Word
Burst Architecture
Features
Functional Description
■
■
■
■
9 Mbit Density (256 Kbit x 36)
The CY7C1308DV25C is a 2.5V Synchronous Pipelined SRAM
equipped with DDR I (Double Data Rate) architecture. The
DDR I architecture consists of an SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst counter.
Addresses for Read and Write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of C and C if provided, or on the rising edge of K and K if C/C are
not provided. Every Read or Write operation is associated with
four words that burst sequentially into or out of the device. The
burst counter takes in the least two significant bits of the external
address and bursts four 36-bit words. Depth expansion is
accomplished with Port Selects for each port. Port Selects allow
each port to operate independently.
250 MHz Clock for High Bandwidth
4-Word Burst to Reduce Address Bus Frequency
Double Data Rate (DDR) Interfaces
(data transferred at 500 MHz at 250 MHz)
■
■
Two Input Clocks (K and K) for Precise DDR Timing—SRAM
uses rising edges only
Two Input Clocks (C and C) Account for Clock Skew and Flight
Time Mismatching
■
■
■
■
■
■
Separate Port Selects for Depth Expansion
Synchronous Internally Self-timed Writes
2.5V Core Power Supply with HSTL Inputs and Outputs
Variable Drive HSTL Output Buffers
Asynchronous inputs include impedance match (ZQ).
Synchronous data outputs (Q, sharing the same physical pins as
the data inputs D) are tightly matched to the two output echo
clocks CQ/CQ, eliminating the need for separately capturing
data from each individual DDR SRAM in the system design.
Output data clocks (C/C) are also provided for maximum system
clocking and data synchronization flexibility.
Expanded HSTL Output Voltage (1.4V to 1.9V)
13 x 15 x 1.4 mm 1.0 mm pitch fBGA package, 165 ball (11 x
15 matrix)
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self timed write circuitry.
■
JTAG 1149.1 Compatible Test Access Port
Configuration
CY7C1308DV25C – 256K x 36
Logic Block Diagram
Burst
A
Logic
(1:0)
16
Write Write Write Write
18
Reg
Reg Reg
Reg
A
Address
Register
(17:0)
A
(17:2)
LD
36
256K x 36 Array
K
K
Output
Logic
Control
CLK
Gen.
C
C
Read Data Reg.
144
CQ
CQ
72
Vref
R/W
Reg.
Reg.
Reg.
36
Control
Logic
72
DQ
[35:0]
36
Cypress Semiconductor Corporation
Document #: 001-04310 Rev. *A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 04, 2009
[+] Feedback
CY7C1308DV25C
PRELIMINARY
Selection Guide
Parameter
250 MHz
250
200 MHz
200
167 MHz
Unit
MHz
mA
Maximum Operating Frequency
167
600
Maximum Operating Current
850
700
Shaded areas contain advance information.
Pin Configuration
CY7C1308DV25C (256K × 36) – 11 × 15 FBGA
1
2
3
4
R/W
5
NC
6
K
7
8
LD
9
10
11
CQ
CQ
NC
NC
NC
GND/144M NC/36M
NC
NC
A1
NC/18M GND/72M
A
B
C
D
DQ27
NC
DQ18
DQ28
DQ19
A
NC
A
K
A
NC
NC
NC
NC
DQ17
NC
DQ8
DQ7
DQ16
VSS
VSS
A0
VSS
VSS
DQ29
VSS
VSS
VSS
NC
NC
DQ30
DQ31
VREF
NC
DQ20
DQ21
DQ22
VDDQ
DQ32
DQ23
DQ24
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
DQ15
NC
DQ6
E
F
NC
NC
NC
NC
NC
NC
VDD
VDD
VDD
VDD
VDD
VSS
DQ5
DQ14
ZQ
NC
NC
G
H
J
VDDQ
NC
VREF
DQ13
DQ12
NC
DQ4
DQ3
DQ2
NC
NC
K
L
DQ33
NC
NC
NC
NC
NC
DQ35
NC
DQ34
DQ25
DQ26
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
DQ11
NC
DQ1
DQ10
DQ0
M
N
P
A
C
A
DQ9
A
A
A
A
A
A
TDO
TCK
A
C
A
TMS
TDI
R
Pin Definitions
Name
I/O
Description
DQ[35:0]
Input/Output
Synchronous
Data Input/Output Signals. Inputs are sampled on the rising edge of K and K clocks
during valid Write operations. These pins drive out the requested data during a Read
operation. Valid data is driven out on the rising edge of both the C and C clocks during
Read operationsor K and K when in single clock mode. When Read access isdeselected,
Q[35:0] are automatically tristated.
Input
Synchronous
Synchronous Load. This input is brought LOW when a bus cycle sequence is to be
defined. This definition includes address and Read/Write direction. All transactions
operate on a burst of 4 data (two clock periods of bus activity).
LD
A, A0, A1
Input
Synchronous
Address Inputs. These address inputs are multiplexed for both Read and Write opera-
tions. A0 and A1 are the inputs to the burst counter. These are incremented in a linear
fashion internally. Eighteen address inputs are needed to access the entire memory
array. All the address inputs are ignored when the part is deselected.
Input
Synchronous
Synchronous Read/Write Input. When LD is LOW, this input designates the access
type (Read when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must
meet the setup and hold times around edge of K.
R/W
C
Input Clock
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See Figure 1 on page 5 for further details.
Document #: 001-04310 Rev. *A
Page 2 of 18
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CY7C1308DV25C
PRELIMINARY
Pin Definitions (continued)
Name
I/O
Description
C
K
Input Clock
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See Figure 1 on page 5 for further details.
Input Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs
to the device and to drive out data through Q[35:0] when in single clock mode. All accesses
are initiated on the rising edge of K.
K
Input Clock
Echo Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented
to the device and to drive out data through Q[35:0] when in single clock mode.
CQ
CQ is Referenced with Respect to C. This is a free running clock and is synchronized
to the output clock (C) of the DDR I. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC timing table.
Echo Clock
Input
CQ is Referenced with Respect to C. This is a free running clock and is synchronized
to the output clock (C) of the DDR I. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC timing table.
CQ
ZQ
Output Impedance Matching Input. This input is used to tune the device outputs to the
system data bus impedance. CQ, CQ and Q[35:0] output impedance are set to 0.2 x RQ,
where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be
connected directly to VDD, which enables the minimum impedance mode. This pin cannot
be connected directly to GND or left unconnected.
TDO
TCK
TDI
Output
Input
Input
Input
N/A
TDO for JTAG.
TCK pin for JTAG.
TDI pin for JTAG.
TMS
NC
TMS pin for JTAG.
Not Connected to the Die. Can be tied to any voltage level.
Address Expansion for 18M. This is not connected to the die.
Address Expansion for 36M. This is not connected to the die.
Address Expansion for 72M. This should be tied LOW.
Address Expansion for 144M. This should be tied LOW.
NC/18M
NC/36M
GND/72M
GND/144M
VREF
N/A
N/A
Input
Input
Input-
Reference Voltage Input. Static input used to set the reference level for HSTL inputs
Reference
and outputs as well as AC measurement points.
VDD
VSS
Power Supply
Ground
Power supply inputs to the core of the device.
Ground for the device.
VDDQ
Power Supply
Power supply inputs for the outputs of the device.
All synchronous control (R/W, LD) inputs pass through input
registers controlled by the rising edge of the input clocks (K and
K).
Introduction
Functional Overview
The CY7C1308DV25C is a synchronous pipelined Burst SRAM
equipped with DDR interface.
Read Operations
The CY7C1308DV25C is organized internally as an array of
256K x 36. Accesses are completed in a burst of four sequential
36-bit data words. Read operations are initiated by asserting
R/W HIGH and LD LOW at the rising edge of the Positive Input
Clock (K). The address presented to Address inputs are stored
in the Read address register and the least two significant bits of
the address are presented to the burst counter. The burst
counter increments the address in a linear fashion. Following the
next K clock rise the corresponding 36-bit word of data from this
address location is driven onto the Q[35:0] using C as the output
timing reference. On the subsequent rising edge of C the next
36-bit data word from the address location generated by the
burst counter is driven onto the Q[35:0]. This process continues
Accesses are initiated on the positive input clock (K). All
synchronous input timing is referenced from the rising edge of
the input clocks (K and K) and all output timing is referenced to
the rising edge of output clocks (C and C or K and K when in
single clock mode).
All synchronous data inputs (D[35:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q[35:0]) pass through output registers controlled by the
rising edge of the output clocks (C and C or K and K when in
single clock mode).
Document #: 001-04310 Rev. *A
Page 3 of 18
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CY7C1308DV25C
PRELIMINARY
until all four 36-bit data words are driven out onto Q[35:0]. The
requested data is valid 3 ns from the rising edge of the output
clock (C or C, 250 MHz device). To maintain the internal logic,
each Read access must be allowed to complete. Each Read
access consists of four 36-bit data words and takes two clock
cycles to complete. Therefore, Read accesses to the device
cannot be initiated on two consecutive K clock rises. The internal
logic of the device ignores the second Read request. Read
accesses can be initiated on every other K clock rise. Doing so
pipelines the data flow such that data is transferred out of the
device on every rising edge of the output clocks (C and C or K
and K when in single clock mode).
identical to the operation if the device had zero skew between
the K/K and C/C clocks. All timing parameters remain the same
in this mode. To use this mode of operation, the user must tie C
and C HIGH at power-on. This function is a strap option and not
alterable during device operation.
DDR Operation
The CY7C1308DV25C enables high performance operation
through high clock frequencies (achieved through pipelining) and
double data rate mode of operation. At slower frequencies, the
CY7C1308DV25C requires a single No Operation (NOP) cycle
when transitioning from a Read to a Write cycle. At higher
frequencies, a second NOP cycle may be required to prevent
bus contention.
When the read port is deselected, the CY7C1308DV25C first
completes the pending read transactions. Synchronous internal
circuitry automatically tristates the outputs following the next
rising edge of the positive output clock (C). This allows for a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
If a Read occurs after a Write cycle, address and data for the
Write are stored in registers. The Write information must be
stored because the SRAM can not perform the last word Write
to the array without conflicting with the Read. The data stays in
this register until the next Write cycle occurs. On the first Write
cycle after the Read(s), the stored data from the earlier Write is
written into the SRAM array. This is called a Posted Write.
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to Address inputs are stored in the Write
address register and the least two significant bits of the address
are presented to the burst counter. The burst counter increments
the address in a linear fashion. On the following K clock rise, the
data presented to D[35:0] is latched and stored into the 36-bit
Write Data register. On the subsequent rising edge of the
Negative Input Clock (K) the information presented to D[35:0] is
also stored into the Write Data Register.This process continues
for one more cycle until four 36-bit words (a total of 144 bits) of
data are stored in the SRAM. The 144 bits of data are then written
into the memory array at the specified location. Therefore, Write
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device ignores the second
Write request. Write accesses can be initiated on every other
rising edge of the positive input clock (K). Doing so pipelines the
data flow such that 36-bits of data can be transferred into the
device on every rising edge of the input clocks (K and K).
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
Echo Clocks
Echo clocks are provided on the DDR I to simplify data capture
on high-speed systems. Two echo clocks are generated by the
DDR I. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free-running clocks and are
synchronized to the output clock of the DDR I. In the single clock
mode, CQ is generated with respect to K and CQ is generated
with respect to K. The timings for the echo clocks are shown in
the AC Timing table.
Programmable Impedance
An external resistor, RQ must be connected between the ZQ pin
on the SRAM and VSS to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5X the value of the
intended line impedance driven by the SRAM, The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175Ω and 350Ω, with VDDQ=1.5V. The
output impedance is adjusted every 1024 cycles to adjust for
drifts in supply voltage and temperature.
When deselected, the Write port ignores all inputs after the
pending Write operations are completed.
Single Clock Mode
The CY7C1308DV25C can be used with a single clock that
controls both the input and output registers. In this mode, the
device recognizes only a single pair of input clocks (K and K) that
control both the input and output registers. This operation is
Document #: 001-04310 Rev. *A
Page 4 of 18
[+] Feedback
CY7C1308DV25C
PRELIMINARY
Figure 1. Application Example[1]
ZQ
SRAM#1
ZQ
SRAM#2
LD# R/W#
DQ
CQ/CQ#
DQ
CQ/CQ#
R = 250ohms
R = 250ohms
A
LD# R/W#
C
C#
K
K#
A
C C# K
K#
DQ
Addresses
Cycle Start#
R/W#
BUS
MASTER
(CPU
Return CLK
Source CLK
Return CLK#
Source CLK#
or
ASIC)
Vterm = 0.75V
R = 50ohms
Vterm = 0.75V
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
Truth Table[2, 3, 4, 5, 6, 7]
Operation
K
LD
R/W
L[8]
DQ
D(A1)at
DQ
DQ
DQ
Write Cycle:
L-H
L
D(A2) at
D(A3) at
D(A4) at
Load address; wait one cycle; input
write data on 2 consecutive K and
K rising edges.
K(t+1)↑
K(t+1)↑
K(t+2) ↑
K(t+2) ↑
Read Cycle:
L-H
L
H[9]
Q(A1) at
C(t+1)↑
Q(A2) at
C(t+1) ↑
Q(A3) at
C(t+2)↑
Q(A4) at
C(t+2) ↑
Load address; wait one cycle; read
data on 2 consecutive C and C
rising edges.
NOP: No Operation
L-H
H
X
X
X
High-Z
High-Z
High-Z)
High-Z
Standby: Clock Stopped
Stopped
Previous State Previous State Previous State Previous State
Linear Burst Address Table
First Address (External)
Second Address (Internal)
Third Address (Internal)
Fourth Address (Internal)
X..X00
X..X01
X..X10
X..X11
X..X01
X..X10
X..X11
X..X00
X..X10
X..X11
X..X00
X..X01
X..X11
X..X00
X..X01
X..X10
Notes
1. The above application shows 2 DDR I being used.
2. X = “Don't Care“, H = Logic HIGH, L = Logic LOW,
3. Device powers up deselected and the outputs are in a tristate condition.
↑
represents rising edge.
4. “A1” represents address location latched by the devices when transaction was initiated. A2, A3, and A4 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t+1 and t+2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. This signal was HIGH on previous K clock rise. Initiating consecutive Write operations on consecutive K clock rises is not permitted. The device ignores the second
Write request.
9. This signal was LOW on previous K clock rise. Initiating consecutive Read operations on consecutive K clock rises is not permitted.The device ignores the second
Read request.
Document #: 001-04310 Rev. *A
Page 5 of 18
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CY7C1308DV25C
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested
Latch Up Current ................................................... > 200 mA
Storage Temperature ..................................... −65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Ambient
[11]
[11]
Range
VDD
VDDQ
Temperature (TA)
Supply Voltage on VDD Relative to GND.........−0.5V to +3.6V
DC Applied to Outputs in High-Z...........−0.5V to VDDQ + 0.5V
DC Input Voltage[10] ................................−0.5V to VDDQ + 0.5V
Com’l
0°C to +70°C
2.5 ± 0.1V
1.4V to 1.9V
Electrical Characteristics Over the Operating Range [12]
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min
2.4
Typ
2.5
1.5
Max
Unit
V
2.6
1.9
VDDQ
VOH
1.4
V
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[10]
Input LOW Voltage[10, 13]
Input Load Current
Note 14
Note 15
VDDQ/2–0.12
VDDQ/2–0.12
VDDQ/2+0.12
V
VOL
VDDQ/2+0.12
V
VOH(LOW)
VOL(LOW)
VIH
IOH = –0.1 mA, Nominal Impedance
IOL = 0.1 mA, Nominal Impedance
VDDQ–0.2
VSS
VDDQ
0.2
V
V
VREF+0.1
–0.3
VDDQ+0.3
VREF – 0.1
5
V
VIL
V
IX
GND ≤ VI ≤ VDDQ
–5
μA
μA
V
IOZ
Output Leakage Current
Input Reference Voltage[16]
VDD Operating Supply
GND ≤ VI ≤ VDDQ, Output Disabled
Typical Value = 0.75V
–5
5
VREF
IDD
0.68
0.75
0.95
600
VDD = Max., IOUT = 0 mA, 167 MHz
f = fMAX = 1/tCYC
mA
mA
mA
mA
mA
mA
200 MHz
700
250 MHz
850
ISB1
Automatic Power-Down
Max. VDD, Both Ports
Deselected, VIN ≥ VIH or
VIN ≤ VIL f = fMAX = 1/tCYC,
Inputs Static
167 MHz
200 MHz
250 MHz
250
300
350
Shaded areas contain advance information.
AC Input Requirements
Parameter
Description
Test Conditions
Min
VREF + 0.2
–
Typ
–
Max
–
Unit
V
VIH
VIL
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
–
VREF – 0.2
V
Notes
10. Overshoot: V (AC) < V
+ 0.85V (Pulse width less than t
2). Undershoot: V (AC) > –1.5V (Pulse width less than t
2).
IH
DDQ
CYC/
IL
CYC/
11. Power-up: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
.
DD
IH
DD
DDQ
DD
12. All voltage referenced to ground.
13. This spec is for all inputs except C and C Clock. For C and C Clock, V (Max.) = V
– 0.2V.
REF
IL
14. Output are impedance controlled. I = –(V
/2)/(RQ/5) for values of 175
Ω
<= RQ <= 350
<= RQ <= 350
(Max.) = 0.95V or 0.54V , whichever is smaller.
Ω.
OH
DDQ
15. Output are impedance controlled. I = (V
/2)/(RQ/5) for values of 175
Ω
Ω.
OL
DDQ
16. V
(Min.) = 0.68V or 0.46V
, whichever is larger, V
REF
DDQ
REF
DDQ
Document #: 001-04310 Rev. *A
Page 6 of 18
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CY7C1308DV25C
PRELIMINARY
Thermal Resistance[17]
Parameter
ΘJA
Description
Test Conditions
165 FBGA
16.7
Unit
°C/W
°C/W
Thermal Resistance (Junction to Ambient) Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
ΘJC
Thermal Resistance (Junction to Case)
2.5
Capacitance[17]
Parameter
Description
Input Capacitance
Test Conditions
Max
Unit
pF
CIN
TA = 25°C, f = 1 MHz,
DD = 2.5V
DDQ = 1.5V
5
6
7
V
V
CCLK
CO
Clock Input Capacitance
Output Capacitance
pF
pF
AC Test Loads and Waveforms
V
/2
DDQ
V
/2
DDQ
V
REF
V
V
/2
REF
R = 50Ω
DDQ
OUTPUT
[18]
ALL INPUT PULSES
1.25V
Z = 50Ω
0
OUTPUT
Device
Device
Under
Test
R = 50Ω
L
0.75V
0.25V
5 pF
Under
V
= 0.75V
REF
ZQ
ZQ
(a)
Test
RQ =
250Ω
RQ =
250Ω
INCLUDING
JIG AND
SCOPE
(b)
Document #: 001-04310 Rev. *A
Page 7 of 18
[+] Feedback
CY7C1308DV25C
PRELIMINARY
Switching Characteristics Over the Operating Range [18]
250 MHz
200 MHz
167 MHz
Cypress Consortium
Parameter Parameter
Description
Unit
Min Max Min Max Min Max
[19]
tPower
VCC (typical) to the First Access Read or Write
10
10
10
μs
Cycle Time
tCYC
tKH
tKHKH
tKHKL
tKLKH
tKHKH
K Clock and C Clock Cycle Time
Input Clock (K/K and C/C) HIGH
Input Clock (K/K and C/C) LOW
4.0
1.6
1.6
–
–
5.0
2.0
2.0
–
–
–
6.0
2.4
2.4
ns
ns
ns
ns
tKL
–
tKHKH
K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise 1.8
(rising edge to rising edge)
2.5
2.2 2.75 2.8
3.2
2.0
tKHCH
tKHCH
K/K Clock Rise to C/C Clock Rise (rising edge to rising 0.0
edge)
1.6
0.0
1.8
0.0
ns
Setup Times
tSA
tSA
tSC
tSD
Address Setup to Clock (K and K) Rise
Control Setup to Clock (K and K) Rise (LD, R/W)
D[35:0] Setup to Clock (K and K) Rise
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
ns
ns
ns
tSC
tSD
Hold Times
tHA
tHC
tHA
tHC
Address Hold after Clock (K and K) Rise
0.7
0.7
0.7
0.7
0.7
0.7
ns
ns
Control Signals Hold after Clock (K and K) Rise (
,
LD
)
R/W
tHD
tHD
D[35:0] Hold after Clock (K and K) Rise
0.7
0.7
0.7
ns
Output Times
tCO
tCHQV
C/C Clock Rise (or K/K in single clock mode) to Data
Valid
3.0
3.0
3.0
3.0
3.0
ns
ns
tDOH
tCHQX
Data Output Hold after Output C/C Clock Rise (Active
to Active)
0.8
0.8
0.8
tCHZ
tCHZ
Clock (C and C) Rise to High-Z (Active to High-Z)[20, 21]
Clock (C and C) Rise to Low-Z[20, 21]
C/C Clock Rise to Echo Clock Valid
Echo Clock High to Data Valid
3.0
3.2
ns
ns
ns
tCLZ
tCLZ
0.8
0.8
0.8
0.8
0.8
0.8
tCCQO
tCQD
tCQDOH
tCQHZ
tCHCQV
tCQHQV
tCQHQX
tCHZ
2.4
2.6
0.40
0.40
0.40 ns
ns
Echo Clock High to Data Invalid
–0.30
–0.30
–0.35
–0.35
–0.40
–0.40
Clock (CQ and CQ) Rise to High-Z (Active to High-Z)[20,
0.40
0.40
0.40 ns
21]
tCQLZ
tCLZ
Clock (CQ and CQ) Rise to Low-Z[20, 21]
ns
Shaded areas contain advance information.
Notes
17. Tested initially and after any design or process change that may affect these parameters.
18. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, V
= 1.5V, input pulse
DDQ
levels of 0.25V to 1.25V, and output loading of the specified I /I and load capacitance shown in (a) of AC test loads.
OL OH
Document #: 001-04310 Rev. *A
Page 8 of 18
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CY7C1308DV25C
PRELIMINARY
Switching Waveforms[22, 23, 24]
Notes
19. This part has a voltage regulator that steps down the voltage internally; t
is the time power needs to be supplied above V minimum initially before a Read
DD
Power
or Write operation can be initiated.
20. t
, t
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
CHZ CLZ
21. At any given voltage and temperature t
is less than t
and, t
less than t
.
CO
CHZ
CLZ
CHZ
22. Q01 refers to output from address A0. Q02 refers to output from the next internal burst address following A0, i.e., A0+1.
23. Outputs are disabled (High-Z) one clock cycle after a NOP.
24. In this example, if address A4 = A3, then data Q41 = D31, Q42 = D32, Q43 = D33, and Q44 = D34. Write data is forwarded immediately as Read results.This
note applies to the whole diagram.
Document #: 001-04310 Rev. *A
Page 9 of 18
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CY7C1308DV25C
PRELIMINARY
Instruction Register
IEEE 1149.1 Serial Boundary Scan (JTAG)
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins as shown in TAP Controller Block Diagram. Upon
power-up, the instruction register is loaded with the IDCODE
instruction. It is also loaded with the IDCODE instruction if the
controller is placed in a reset state as described in the previous
section.
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-1900. The TAP operates using JEDEC
standard 2.5V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. On power-up, the device comes up in a reset
state which does not interfere with the operation of the device.
When the TAP controller is in the Capture IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Boundary Scan Register
Test Mode Select
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this pin unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can
be used to capture the contents of the Input and Output ring.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see the TAP Controller State
Diagram. TDI is internally pulled up and can be unconnected if
the TAP is unused in an application. TDI is connected to the most
significant bit (MSB) on any register.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
Identification (ID) Register
Test Data-Out (TDO)
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions
table.
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine (see Instruction codes). The output
changes on the falling edge of TCK. TDO is connected to the
least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating. At
power-up, the TAP is reset internally to ensure that TDO comes
up in a high-Z state.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the Instruction
Code table. Three of these instructions are listed as RESERVED
and should not be used. The other five instructions are described
in detail below.
TAP Registers
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction registers. Data is serially loaded into the TDI pin on
the rising edge of TCK. Data is output on the TDO pin on the
falling edge of TCK.
Document #: 001-04310 Rev. *A
Page 10 of 18
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CY7C1308DV25C
PRELIMINARY
IDCODE
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction is
loaded into the instruction register upon power-up or whenever
the TAP controller is given a test logic reset state.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required—that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is given
during the “Update IR” state.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
EXTEST Output Bus Three-state
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a three-state mode.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
The boundary scan register has a special bit located at bit #47.
When this scan cell, called the “extest output bus three-state”, is
latched into the preload register during the “Update-DR” state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High-Z condition.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture Setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell latches into the preload
register. When the EXTEST instruction is entered, this bit directly
controls the output Q-bus pins. Note that this bit is pre-set HIGH
to enable the output when the device is powered-up, and also
when the TAP controller is in the “Test-Logic-Reset” state.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 001-04310 Rev. *A
Page 11 of 18
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CY7C1308DV25C
PRELIMINARY
TAP Controller State Diagram[25]
TEST-LOGIC
1
RESET
0
1
1
1
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note
25. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 001-04310 Rev. *A
Page 12 of 18
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CY7C1308DV25C
PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
Selection
Circuitry
TDI
2
1
1
1
0
0
0
TDO
Circuitry
Instruction Register
29
31 30
.
.
2
Identification Register
.
106 .
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range [10, 12, 26]
Parameter
VOH1
Description
Output HIGH Voltage
Test Conditions
IOH = −2.0 mA
Min
1.7
2.1
Max
Unit
V
V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
IOH = −100 μA
IOL = 2.0 mA
IOL = 100 μA
0.7
0.2
V
V
1.7
–0.3
–5
VDD + 0.3
0.7
V
VIL
Input LOW Voltage
V
IX
Input and Output Load Current
GND ≤ VI ≤ VDDQ
5
μA
TAP AC Switching Characteristics Over the Operating Range[27, 28]
Parameter
tTCYC
Description
Min
Max
10
Unit
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
100
tTF
MHz
ns
tTH
40
40
tTL
TCK Clock LOW
ns
Setup Times
tTMSS
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
10
10
10
ns
ns
ns
tTDIS
tCS
Notes
26. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.
27. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
28. Test conditions are specified using the load in TAP AC test conditions. t /t = 1 ns.
R
F
Document #: 001-04310 Rev. *A
Page 13 of 18
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CY7C1308DV25C
PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range[27, 28] (continued)
Parameter
Hold Times
tTMSH
Description
Min
Max
Unit
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
10
10
10
ns
ns
ns
tTDIH
tCH
Capture Hold after Clock Rise
Output Times
tTDOV
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
20
ns
ns
tTDOX
0
TAP Timing and Test Conditions[28]
1.25V
ALL INPUT PULSES
1.25V
2.5V
50Ω
TDO
0V
Z = 50Ω
0
C = 20 pF
L
(a)
GND
tTL
tTH
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
tTDOV
Document #: 001-04310 Rev. *A
Page 14 of 18
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CY7C1308DV25C
PRELIMINARY
Identification Register Definitions
Value
Instruction Field
Description
CY7C1308DV25C
Revision Number (31:29)
Cypress Device ID (28:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
000
01011111011100110
00000110100
1
Version number.
Defines the type of SRAM.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Scan Register Sizes
Register Name
Instruction
Bypass
Bit Size
3
1
ID
32
107
Boundary Scan
Instruction Codes
Instruction
EXTEST
Code
Description
000 Captures the Input/Output ring contents.
IDCODE
001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011 Do not use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100 Captures the Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101 Do not use: This instruction is reserved for future use.
110 Do not use: This instruction is reserved for future use.
111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
Boundary Scan Order (continued)
Boundary Scan Order
Bit #
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Bump ID
Bit #
0
Bump ID
6R
11N
9M
9N
1
6P
2
6N
11L
11M
9L
3
7P
4
7N
5
7R
10L
11K
10K
9J
6
8R
7
8P
8
9R
9
11P
10P
10N
9P
9K
10
11
12
13
10J
11J
11H
10M
Document #: 001-04310 Rev. *A
Page 15 of 18
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CY7C1308DV25C
PRELIMINARY
Boundary Scan Order (continued)
Boundary Scan Order (continued)
Bit #
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
Bump ID
Bit #
70
Bump ID
3C
1D
2C
3E
2D
2E
1E
2F
10G
9G
11F
11G
9F
71
72
73
74
10F
11E
10E
10D
9E
75
76
77
78
3F
79
1G
1F
10C
11D
9C
80
81
3G
2G
1J
82
9D
83
11B
11C
9B
84
2J
85
3K
3J
86
10B
11A
Internal
9A
87
2K
1K
2L
88
89
90
3L
8B
91
1M
1L
7C
92
6C
93
3N
3M
1N
2M
3P
2N
2P
1P
3R
4R
4P
5P
5N
5R
8A
94
7A
95
7B
96
6B
97
6A
98
5B
99
5A
100
101
102
103
104
105
106
4A
5C
4B
3A
1H
1A
2B
3B
1C
1B
3D
Document #: 001-04310 Rev. *A
Page 16 of 18
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CY7C1308DV25C
PRELIMINARY
Ordering Information
Speed
Operating
Range
Ordering Code
Package Name
Package Type
13 x 15 x 1.4 mm FBGA
(MHz)
250
CY7C1308DV25C-250BZC
CY7C1308DV25C-200BZC
CY7C1308DV25C-167BZC
BB165D
BB165D
BB165D
Commercial
Commercial
Commercial
200
13 x 15 x 1.4 mm FBGA
13 x 15 x 1.4 mm FBGA
167
Shaded areas contain advance information. Contact your local Cypress sales representative for availability of these parts.
Package Diagram
Figure 2. 165 FBGA 13 x 15 x 1.40 mm BB165D
51-85180 *B
Document #: 001-04310 Rev. *A
Page 17 of 18
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PRELIMINARY
CY7C1308DV25C
Document History Page
Document Title: CY7C1308DV25C 9 Mbit DDR I SRAM 4-Word Burst Architecture
Document Number: 001-04310
Orig. of
Change
Rev.
ECN No.
Submission Date
Description of Change
**
397842
See ECN
08/04/09
SYT
New Data Sheet
*A
2748172
NJY/PYRS Updated template
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© Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-04310 Rev. *A
Revised August 04, 2009
Page 18 of 18
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