CY7C131-45JIT [CYPRESS]
Dual-Port SRAM, 1KX8, 45ns, CMOS, PQCC52, PLASTIC, LCC-52;
| 型号： | CY7C131-45JIT |
| 厂家： | 
CYPRESS |
| 描述： | Dual-Port SRAM, 1KX8, 45ns, CMOS, PQCC52, PLASTIC, LCC-52 静态存储器 内存集成电路 |
| 文件： | 总19页 (文件大小：602K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C130/CY7C131
CY7C140/CY7C141
1K x 8 Dual-Port Static RAM
Features
Functional Description
• True Dual-Ported memory cells which allow simulta-
neous reads of the same memory location
The CY7C130/CY7C131/CY7C140 and CY7C141 are
high-speed CMOS 1K by 8 dual-port static RAMs. Two ports
are provided permitting independent access to any location in
memory. The CY7C130/ CY7C131 can be utilized as either a
standalone 8-bit dual-port static RAM or as a master dual-port
RAM in conjunction with the CY7C140/CY7C141 slave
dual-port device in systems requiring 16-bit or greater word
widths. It is the solution to applications requiring shared or
buffered data, such as cache memory for DSP, bit-slice, or
multiprocessor designs.
• 1K x 8 organization
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: ICC = 110 mA (max.)
• Fully asynchronous operation
• Automatic power-down
Each port has independent control pins; chip enable (CE),
write enable (R/W), and output enable (OE). Two flags are
provided on each port, BUSY and INT. BUSY signals that the
port is trying to access the same location currently being
accessed by the other port. INT is an interrupt flag indicating
that data has been placed in a unique location (3FF for the left
port and 3FE for the right port). An automatic power-down
feature is controlled independently on each port by the chip
enable (CE) pins.
• Master CY7C130/CY7C131 easily expands data bus
width to 16 or more bits using slave CY7C140/CY7C141
• BUSY output flag on CY7C130/CY7C131; BUSY input
on CY7C140/CY7C141
• INT flag for port-to-port communication
• Available in 48-pin DIP (CY7C130/140), 52-pin PLCC,
52-Pin TQFP.
• Pb-Free packages available
The CY7C130 and CY7C140 are available in 48-pin DIP. The
CY7C131 and CY7C141 are available in 52-pin PLCC, 52-pin
Pb-free PLCC, 52-pin PQFP and 52-pin Pb-free PQFP.
Logic Block Diagram
Pin Configurations
R/W
L
R/W
R
CE
L
CE
R
DIP
Top View
OE
L
OE
R
V
48
CE
R/W
BUSY
CC
CE
1
L
L
L
47
46
45
44
R
R
2
3
4
5
6
R/W
BUSY
INT
I/O
I/O
I/O
7L
7R
I/O
CONTROL
I/O
CONTROL
INT
L
OE
A
0L
R
R
L
I/O
0L
0R
OE
A
43
42
R
0R
[1]
A
BUSY
BUSY
1L
L
R
7
8
9
10
11
12
A
A
A
41
40
2L
1R
2R
A
3L
A
A
A
9L
0L
9R
0R
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
DECODER
A
A
39
38
37
36
35
34
3R
4L
A
A
A
5L
4R
5R
A
A
6L
7C130
A
A
13 7C140
6R
7L
A
8L
A
9L
A
A
14
15
16
17
18
7R
8R
I/O
A
9R
I/O
33
32
31
30
29
28
27
26
25
0L
I/O
1L
ARBITRATION
LOGIC
7R
I/O
2L
I/O
3L
I/O
4L
I/O
6R
I/O
(7C130/7C131 ONLY)
AND
19
20
21
22
23
24
5R
CE
L
CE
R
I/O
4R
I/O
INTERRUPT LOGIC
OE
L
OE
R
I/O
3R
I/O
5L
I/O
6L
I/O
7L
GND
2R
R/W
R/W
R
L
I/O
1R
I/O
[2]
0R
[2]
INT
INT
R
L
Note:
1. CY7C130/CY7C131 (Master): BUSY is open drain output and requires pull-up resistor
CY7C140/CY7C141 (Slave): BUSY is input.
2. Open drain outputs: pull-up resistor required.
Cypress Semiconductor Corporation
Document #: 38-06002 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 29, 2005
[+] Feedback
CY7C130/CY7C131
CY7C140/CY7C141
Pin Configuration (continued)
PLCC
Top View
PQFP
Top View
7
6
5
4
3
2
1
52 51 50 49 48 47
46
A
A
OE
1L
2L
3L
4L
5L
6L
7L
8L
9L
0L
1L
8
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
9
45
44
43
42
41
40
39
38
37
36
35
34
A
52 5150 49 48 47 4645 44 43 42 41 40
10
11
12
13
14
15
16
17
18
19
20
A
A
A
A
A
A
A
OE
R
1L
2L
3L
4L
5L
6L
1
39
38
37
36
35
34
33
32
31
30
29
28
27
A
0R
A
1R
A
2
A
3
7C131
7C141
A
2R
A
3R
A
4R
A
5R
A
4
A
5
A
6R
A
7R
A
8R
A
9R
A
6
7C131
7C141
A
7L
A
8L
I/O
I/O
7
A
6R
A
7R
A
8R
A
9R
8
A
I/O
I/O
9L
0L
1L
I/O
I/O
9
2L
NC
I/O
10
11
12
13
3L
7R
2122 23 24 25 26 27 28 29 30 31 32 33
I/O
I/O
NC
I/O
2L
3L
7R
1415 16 17 18 19 20 21 22 23 24 25 26
Pin Definitions
Left Port
CEL
Right Port
Description
CER
Chip Enable
R/WL
R/WR
OER
Read/Write Enable
Output Enable
Address
OEL
A0L–A11/12L
I/O0L–I/O15/17L
INTL
A0R–A11/12R
I/O0R–I/O15/17R
INTR
Data Bus Input/Output
Interrupt Flag
Busy Flag
BUSYL
VCC
BUSYR
Power
GND
Ground
Selection Guide
7C130-30
7C131-30
7C140-30
7C141-30
7C130-35
7C131-35
7C140-35
7C141-35
7C130-45
7C131-45
7C140-45
7C141-45
7C130-55
7C131-55
7C140-55
7C141-55
7C131-15[3] 7C131-25[3]
7C141-15
7C141-25
Unit
ns
Maximum Access Time
15
25
30
35
120
170
45
45
120
170
45
55
110
120
35
Maximum Operating Com’l/Ind
190
170
170
mA
Current
Military
Maximum Standby
Current
Com’l/Ind
Military
75
65
65
mA
65
65
45
Shaded areas contain preliminary information.
Note:
3. 15 and 25-ns version available only in PLCC/PQFP packages.
Document #: 38-06002 Rev. *D
Page 2 of 19
[+] Feedback
CY7C130/CY7C131
CY7C140/CY7C141
Maximum Ratings[4]
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Operating Range
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Range
Commercial
Industrial
Temperature
VCC
Supply Voltage to Ground Potential
(Pin 48 to Pin 24) ........................................... –0.5V to +7.0V
0°C to +70°C
5V ± 10%
5V ± 10%
5V ± 10%
–40°C to +85°C
–55°C to +125°C
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
Military[5]
DC Input Voltage............................................ –3.5V to +7.0V
Output Current into Outputs (LOW) .............................20 mA
Electrical Characteristics Over the Operating Range[6]
7C130-30[3] 7C130-35,45 7C130-55
7C131-25,30 7C131-35,45 7C131-55
7C131-15[3]
7C141-15
7C140-30
7C140-35,45 7C140-55
7C141-25,30 7C141-35,45 7C141-55
Parameter
Description
Test Conditions
Min. Max. Min. Max. Min. Max. Min. Max. Unit
VOH
Output HIGH
Voltage
VCC = Min., IOH = –4.0 mA 2.4
2.4
2.4
2.4
V
VOL
Output LOW
Voltage
IOL = 4.0 mA
IOL = 16.0 mA[7]
2.2
0.4
0.5
0.4
0.5
0.4
0.5
0.4
0.5
V
VIH
VIL
IIX
Input HIGH Voltage
Input LOW Voltage
2.2
2.2
2.2
V
V
0.8
+5
0.8
+5
0.8
+5
0.8
+5
Input Leakage
Current
GND < VI < VCC
–5
–5
–5
–5
–5
–5
–5
–5
µA
IOZ
IOS
ICC
Output Leakage
Current
GND < VO < VCC
Output Disabled
,
+5
+5
+5
+5
µA
Output Short
VCC = Max.,
–350
190
–350
170
–350
–350 mA
Circuit Current[8, 9] VOUT = GND
VCC Operating
Supply Current
CE = VIL,
Com’l
Mil
120
170
110 mA
120
Outputs Open,
[10]
f = fMAX
ISB1
Standby Current
Both Ports,
TTL Inputs
CEL and CER >
VIH, f = fMAX
Com’l
Mil
75
65
45
65
35
45
mA
[10]
ISB2
Standby Current
One Port,
TTL Inputs
CEL or CER > VIH, Com’l
135
115
90
75
90
mA
ActivePortOutputs
Mil
115
Open,
[10]
f = fMAX
ISB3
Standby Current
Both Ports,
CMOS Inputs
BothPortsCEL and Com’l
15
15
15
15
15
15
mA
CER >
Mil
VCC – 0.2V,
VIN > VCC – 0.2V
or VIN < 0.2V, f = 0
Shaded areas contain preliminary information.
Note:
4. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
5. T is the “instant on” case temperature
A
6. See the last page of this specification for Group A subgroup testing information.
7. BUSY and INT pins only.
8. Duration of the short circuit should not exceed 30 seconds.
9. This parameter is guaranteed but not tested.
10. At f = f
, address and data inputs are cycling at the maximum frequency of read cycle of 1/t and using AC Test Waveforms input levels of GND to 3V.
MAX
RC
Document #: 38-06002 Rev. *D
Page 3 of 19
[+] Feedback
CY7C130/CY7C131
CY7C140/CY7C141
Electrical Characteristics Over the Operating Range[6] (continued)
7C130-30[3] 7C130-35,45 7C130-55
7C131-25,30 7C131-35,45 7C131-55
7C131-15[3]
7C141-15
7C140-30
7C140-35,45 7C140-55
7C141-25,30 7C141-35,45 7C141-55
Parameter
Description
Test Conditions
One Port CEL or Com’l
Min. Max. Min. Max. Min. Max. Min. Max. Unit
ISB4
Standby Current
One Port,
CMOS Inputs
125
105
85
70
85
mA
CER > VCC – 0.2V,
VIN > VCC – 0.2V
or VIN < 0.2V,
Active Port Outputs
Open,
Mil
105
[10]
f = fMAX
Capacitance[9]
Parameter
Description
Test Conditions
Max.
15
Unit
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
pF
pF
VCC = 5.0V
COUT
10
AC Test Loads and Waveforms
5V
R1 893Ω
R1 893Ω
5V
5V
OUTPUT
OUTPUT
281Ω
BUSY
R2
347Ω
R2
347Ω
OR
INT
30 pF
5 pF
INCLUDING
30
pF
INCLUDING
JIGAND
JIGAND
SCOPE
(a)
(b)
3.0V
SCOPE
BUSY Output Load
(CY7C130/CY7C131 ONLY)
ALL INPUT PULSES
90%
Equivalent to:
THÉVENIN EQUIVALENT
90%
10%
10%
250Ω
GND
OUTPUT
1.40V
≤5ns
≤ 5ns
Document #: 38-06002 Rev. *D
Page 4 of 19
[+] Feedback
CY7C130/CY7C131
CY7C140/CY7C141
Switching Characteristics Over the Operating Range[6, 11]
7C130-25[3]
7C131-25
7C140-25
7C141-25
7C130-30
7C131-30
7C140-30
7C141-30
7C131-15[3]
7C141-15
Parameter
Description
Min.
15
0
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
25
0
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid[12]
Data Hold from Address Change
CE LOW to Data Valid[12]
OE LOW to Data Valid[12]
OE LOW to Low Z[9, 13, 14]
OE HIGH to High Z[9, 13, 14]
CE LOW to Low Z[9, 13, 14]
CE HIGH to High Z[9, 13, 14]
CE LOW to Power-Up[9]
15
25
30
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
15
10
25
15
30
20
3
3
0
3
5
0
3
5
0
10
10
15
15
15
25
15
15
25
tPD
CE HIGH to Power-Down[9]
WRITE CYCLE[15]
tWC Write Cycle Time
tSCE
tAW
15
12
12
2
25
20
20
2
30
25
25
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
R/W Pulse Width
tHA
tSA
0
0
0
tPWE
tSD
12
10
0
15
15
0
25
15
0
Data Set-Up to Write End
Data Hold from Write End
R/W LOW to High Z[14]
tHD
tHZWE
tLZWE
10
15
15
R/W HIGH to Low Z[14]
0
0
0
Shaded areas contain preliminary information.
Note:
11. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
I
/I and 30-pF load capacitance.
OL OH,
12. AC Test Conditions use V = 1.6V and V = 1.4V.
OH
OL
13. At any given temperature and voltage condition for any given device, t
is less than t
and t
is less than t
.
HZCE
LZCE
HZOE
LZOE
14. t
, t
, t
, t
, t
and t
are tested with C = 5pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
LZCE LZWE HZOE LZOE HZCE
HZWE L
15. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can
terminate a write by going high. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-06002 Rev. *D
Page 5 of 19
[+] Feedback
CY7C130/CY7C131
CY7C140/CY7C141
Switching Characteristics Over the Operating Range[6, 11] (continued)
7C130-25[3]
7C131-25
7C140-25
7C141-25
7C130-30
7C131-30
7C140-30
7C141-30
7C131-15[3]
7C141-15
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY/INTERRUPT TIMING
tBLA
tBHA
tBLC
tBHC
tPS
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch[16]
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH[16]
Port Set Up for Priority
15
15
15
15
20
20
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
5
0
5
0
5
0
[17]
tWB
R/W LOW after BUSY LOW
tWH
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
13
20
30
tBDD
tDDD
tWDD
15
25
30
Write Data Valid to Read Data Valid
Write Pulse to Data Delay
Note 18
Note 18
Note 18
Note 18
Note 18 ns
Note 18 ns
INTERRUPT TIMING
tWINS
tEINS
tINS
R/W to INTERRUPT Set Time
15
15
15
15
15
15
25
25
25
25
25
25
25
25
25
25
25
25
ns
ns
ns
ns
ns
ns
CE to INTERRUPT Set Time
Address to INTERRUPT Set Time
OE to INTERRUPT Reset Time[16]
CE to INTERRUPT Reset Time[16]
Address to INTERRUPT Reset Time[16]
tOINR
tEINR
tINR
Shaded areas contain preliminary information.
Note:
16. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
17. CY7C140/CY7C141 only.
18. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address is toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
Switching Characteristics Over the Operating Range[6,11]
7C130-35
7C131-35
7C140-35
7C141-35
7C130-45
7C131-45
7C140-45
7C141-45
7C130-55
7C131-55
7C140-55
7C141-55
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
35
0
45
0
55
0
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid[12]
Data Hold from Address Change
CE LOW to Data Valid[12]
OE LOW to Data Valid[12]
OE LOW to Low Z[9, 13, 14]
OE HIGH to High Z[9, 13, 14]
CE LOW to Low Z[9, 13, 14]
35
45
55
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
35
20
45
25
55
25
3
5
3
5
3
5
20
20
25
Document #: 38-06002 Rev. *D
Page 6 of 19
[+] Feedback
CY7C130/CY7C131
CY7C140/CY7C141
Switching Characteristics Over the Operating Range[6,11] (continued)
7C130-35
7C131-35
7C140-35
7C141-35
7C130-45
7C130-55
7C131-55
7C140-55
7C141-55
7C131-45
7C140-45
7C141-45
Parameter
tHZCE
Description
CE HIGH to High Z[9, 13, 14]
CE LOW to Power-Up[9]
Min.
Max.
Min.
Max.
Min.
Max.
Unit
ns
20
20
25
tPU
0
0
0
ns
tPD
CE HIGH to Power-Down[9]
35
35
35
ns
WRITE CYCLE[15]
tWC Write Cycle Time
tSCE
tAW
35
30
30
2
45
35
35
2
55
40
40
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
R/W Pulse Width
tHA
tSA
0
0
0
tPWE
tSD
25
15
0
30
20
0
30
20
0
Data Set-Up to Write End
Data Hold from Write End
R/W LOW to High Z[14]
tHD
tHZWE
tLZWE
20
20
25
R/W HIGH to Low Z[14]
0
0
0
BUSY/INTERRUPT TIMING
tBLA BUSY LOW from Address Match
20
20
20
20
25
25
25
25
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBHA
tBLC
tBHC
tPS
BUSY HIGH from Address Mismatch[16]
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH[16]
Port Set Up for Priority
5
0
5
0
5
0
[17]
tWB
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
tWH
30
35
35
tBDD
tDDD
35
45
45
Write Data Valid to Read Data Valid
Note
18
Note
18
Note
18
tWDD
Write Pulse to Data Delay
Note
18
Note
18
Note
18
ns
INTERRUPT TIMING
tWINS
tEINS
tINS
R/W to INTERRUPT Set Time
25
25
25
25
25
25
35
35
35
35
35
35
45
45
45
45
45
45
ns
ns
ns
ns
ns
ns
CE to INTERRUPT Set Time
Address to INTERRUPT Set Time
OE to INTERRUPT Reset Time[16]
CE to INTERRUPT Reset Time[16]
Address to INTERRUPT Reset Time[16]
tOINR
tEINR
tINR
Document #: 38-06002 Rev. *D
Page 7 of 19
[+] Feedback
CY7C130/CY7C131
CY7C140/CY7C141
Switching Waveforms
Read Cycle No. 1[19, 20]
Either Port Address Access
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATAVALID
DATA VALID
Read Cycle No. 2[19, 21]
Either Port CE/OE Access
CE
OE
t
HZCE
t
ACE
t
HZOE
t
DOE
t
LZOE
t
LZCE
DATA VALID
DATA OUT
t
PU
t
PD
I
CC
I
SB
Read Cycle No. 3[20]
Read with BUSY, Master: CY7C130 and CY7C131
t
RC
ADDRESS
ADDRESS MATCH
R
t
PWE
R/W
R
t
HD
D
INR
VALID
ADDRESS MATCH
ADDRESS
L
t
PS
t
BHA
BUSY
L
t
BLA
t
BDD
DOUT
VALID
L
t
DDD
t
WDD
Notes:
19. R/W is HIGH for read cycle.
20. Device is continuously selected, CE = V and OE = V .
IL
IL
21. Address valid prior to or coincident with CE transition LOW.
Document #: 38-06002 Rev. *D
Page 8 of 19
[+] Feedback
CY7C130/CY7C131
CY7C140/CY7C141
Switching Waveforms (continued)
Write Cycle No. 1 (OE Three-States Data I/Os—Either Port[15, 22]
Either Port
t
WC
ADDRESS
CE
t
SCE
t
t
AW
HA
t
SA
t
PWE
R/W
t
t
SD
HD
DATAIN
OE
DATA VALID
t
HZOE
HIGH IMPEDANCE
D
OUT
Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)[16, 23]
t
WC
ADDRESS
CE
t
t
HA
SCE
t
AW
t
SA
t
PWE
R/W
t
t
HD
SD
DATAIN
DATA VALID
t
LZWE
t
HZWE
HIGH IMPEDANCE
DATAOUT
Notes:
22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
or t
+ t to allow the data I/O pins to enter high impedance
PWE
HZWE SD
and for data to be placed on the bus for the required t
.
SD
23. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Document #: 38-06002 Rev. *D
Page 9 of 19
[+] Feedback
CY7C130/CY7C131
CY7C140/CY7C141
Switching Waveforms (continued)
Busy Timing Diagram No. 1 (CE Arbitration)
CEL Valid First:
ADDRESS LR,
ADDRESS MATCH
CE
L
t
PS
CE
R
t
t
BHC
BLC
BUSY
R
CER Valid First:
ADDRESSL,R
ADDRESS MATCH
CE
R
t
PS
CE
L
t
t
BHC
BLC
BUSY
L
Busy Timing Diagram No. 2 (Address Arbitration)
Left Address Valid First:
t
or t
WC
RC
ADDRESS MATCH
ADDRESS MISMATCH
ADDRESS
L
t
PS
ADDRESS
R
t
t
BHA
BLA
BUSY
R
Right Address Valid First:
t
or t
WC
RC
ADDRESS MATCH
ADDRESS MISMATCH
ADDRESS
R
t
PS
ADDRESS
L
t
t
BHA
BLA
BUSY
L
Document #: 38-06002 Rev. *D
Page 10 of 19
[+] Feedback
CY7C130/CY7C131
CY7C140/CY7C141
Switching Waveforms (continued)
Busy Timing Diagram No. 3
Write with BUSY (Slave:CY7C140/CY7C141)
CE
t
PWE
R/W
t
t
WH
WB
BUSY
Document #: 38-06002 Rev. *D
Page 11 of 19
[+] Feedback
CY7C130/CY7C131
CY7C140/CY7C141
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR
t
WC
ADDR
WRITE 3FF
L
t
t
HA
INS
CE
L
t
EINS
R/W
L
t
SA
t
WINS
INT
R
Right Side Clears INTR
t
RC
ADDR
READ 3FF
R
t
t
INT
HA
CE
R
t
EINR
R/W
R
OE
R
t
OINR
INT
R
Right Side Sets INTL
t
WC
ADDR
WRITE 3FE
R
t
t
HA
INS
CE
R
t
EINS
R/W
R
t
SA
t
WINS
INT
L
Left Side Clears INTL
t
RC
ADDR
READ 3FE
R
t
t
INR
HA
CE
L
t
EINR
R/W
L
OE
L
t
OINR
INT
L
Document #: 38-06002 Rev. *D
Page 12 of 19
[+] Feedback
CY7C130/CY7C131
CY7C140/CY7C141
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
120
100
80
1.4
1.2
1.0
ICC
1.2
ICC
1.0
0.8
0.8
0.6
0.4
60
VCC = 5.0V
TA = 25°C
VCC = 5.0V
VIN = 5.0V
0.6
0.4
40
I SB3
0.2
0.6
20
0
I SB3
0.2
0.0
–55
25
125
0
1.0
2.0
3.0
4.0
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
1.1
100
80
1.2
1.0
60
TA = 25°C
V
CC = 5.0V
1.0
40
0.8
V
CC = 5.0V
20
0
0.9
0.8
TA = 25°C
0.6
–55
0.0
1.0
2.0
3.0
4.0
25
125
4.0
4.5
5.0
5.5
6.0
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED ICC vs. CYCLE TIME
1.25
30.0
25.0
3.0
2.5
VCC = 4.5V
TA = 25°C
VIN = 0.5V
1.0
2.0
20.0
15.0
10.0
1.5
1.0
0.75
VCC = 4.5V
TA = 25°C
0.5
0.0
5.0
0
0.50
10
20
30
40
0
1.0
2.0
3.0
4.0 5.0
0
200 400 600 800 1000
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
SUPPLY VOLTAGE (V)
Document #: 38-06002 Rev. *D
Page 13 of 19
[+] Feedback
CY7C130/CY7C131
CY7C140/CY7C141
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Sidebraze DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Sidebraze DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Sidebraze DIP
30
CY7C130-30PC
CY7C130-30PI
CY7C130-35PC
CY7C130-35PI
CY7C130-35DMB
CY7C130-45PC
CY7C130-45PI
CY7C130-45DMB
CY7C130-55PC
CY7C130-55PI
CY7C130-55DMB
CY7C131-15JC
CY7C131-15JXC
CY7C131-15NC
CY7C131-15JI
CY7C131-15JXI
CY7C131-25JC
CY7C131-25JXC
CY7C131-25NC
CY7C131-25NXC
CY7C131-25JI
CY7C131-25NI
CY7C131-30JC
CY7C131-30NC
CY7C131-30JI
CY7C131-35JC
CY7C131-35NC
CY7C131-35JI
CY7C131-35NI
CY7C131-45JC
CY7C131-45NC
CY7C131-45JI
CY7C131-45NI
CY7C131-55JC
CY7C131-55JXC
CY7C131-55NC
CY7C131-55NXC
CY7C131-55JI
CY7C131-55JXI
CY7C131-55NI
P25
P25
P25
P25
D26
P25
P25
D26
P25
P25
D26
J69
J69
N52
J69
J69
J69
J69
N52
N52
J69
N52
J69
N52
J69
J69
N52
J69
N52
J69
N52
J69
N52
J69
J69
N52
N52
J69
J69
N52
Commercial
Industrial
Commercial
Industrial
Military
35
45
55
15
Commercial
Industrial
Military
Commercial
Industrial
Military
52-Lead Plastic Leaded Chip Carrier
52-Lead Pb-Free Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Commercial
52-Lead Plastic Leaded Chip Carrier
52-Lead Pb-Free Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Lead Pb-Free Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Industrial
25
Commercial
52-Pin Pb-Free Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Industrial
30
35
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Commercial
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Industrial
Commercial
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Industrial
45
55
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Commercial
Industrial
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier
52-Lead Pb-Free Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Commercial
52-Pin Pb-Free Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier
52-Lead Pb-Free Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Industrial
Document #: 38-06002 Rev. *D
Page 14 of 19
[+] Feedback
CY7C130/CY7C131
CY7C140/CY7C141
Ordering Information (continued)
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C140-30PC
Package Type
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Sidebraze DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Sidebraze DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Sidebraze DIP
30
P25
P25
P25
P25
D26
P25
P25
D26
P25
P25
D26
J69
N52
J69
J69
N52
J69
N52
J69
N52
J69
J69
N52
J69
N52
J69
N52
J69
N52
J69
N52
J69
N52
Commercial
Industrial
Commercial
Industrial
Military
CY7C140-30PI
CY7C140-35PC
CY7C140-35PI
CY7C140-35DMB
CY7C140-45PC
CY7C140-45PI
CY7C140-45DMB
CY7C140-55PC
CY7C140-55PI
CY7C140-55DMB
CY7C141-15JC
CY7C141-15NC
CY7C141-25JC
CY7C141-25JXC
CY7C141-25NC
CY7C141-25JI
CY7C141-25NI
CY7C141-30JC
CY7C141-30NC
CY7C141-30JI
CY7C141-35JC
CY7C141-35NC
CY7C141-35JI
CY7C141-35NI
CY7C141-45JC
CY7C141-45NC
CY7C141-45JI
CY7C141-45NI
CY7C141-55JC
CY7C141-55NC
CY7C141-55JI
CY7C141-55NI
35
45
55
Commercial
Industrial
Military
Commercial
Industrial
Military
15
25
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Commercial
52-Lead Plastic Leaded Chip Carrier
52-Lead Pb-Free Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Commercial
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Industrial
30
35
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Commercial
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Industrial
Commercial
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Industrial
45
55
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Commercial
Industrial
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Commercial
Industrial
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Document #: 38-06002 Rev. *D
Page 15 of 19
[+] Feedback
CY7C130/CY7C131
CY7C140/CY7C141
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
READ CYCLE
tRC
tAA
tACE
tDOE
WRITE CYCLE
Subgroups
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
Parameter
VOH
VOL
Subgroups
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
VIH
VIL Max.
IIX
tWC
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tSCE
IOZ
tAW
ICC
tHA
ISB1
tSA
ISB2
tPWE
ISB3
tSD
ISB4
tHD
BUSY/INTERRUPT TIMING
tBLA
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tBHA
tBLC
tBHC
tPS
tWINS
tEINS
tINS
tOINR
tEINR
tINR
BUSY TIMING
[24]
tWB
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
tWH
tBDD
Note:
24. CY7C140/CY7C141 only.
Document #: 38-06002 Rev. *D
Page 16 of 19
[+] Feedback
CY7C130/CY7C131
CY7C140/CY7C141
Package Diagrams
48-Lead (600-Mil) Sidebraze DIP D26
MIL-STD-1835 D-14 Config. C
51-80044 **
52-Lead Plastic Leaded Chip Carrier J69
52-Lead Pb-Free Plastic Leaded Chip Carrier J69
MIN.
DIMENSIONS IN INCHES
MAX.
SEATING PLANE
PIN #1 ID
7
1
47
8
46
0.013
0.021
0.750
0.756
0.045
0.055
0.690
0.730
0.785
0.795
20
34
0.023
0.033
21
33
0.020 MIN.
0.750
0.756
0.090
0.130
51-85004-*A
0.165
0.200
0.785
0.795
Document #: 38-06002 Rev. *D
Page 17 of 19
[+] Feedback
CY7C130/CY7C131
CY7C140/CY7C141
Package Diagrams (continued)
48-Lead (600-Mil) Molded DIP P25
51-85020-*A
52-Lead Plastic Quad Flatpack N52
52-Lead Pb-Free Plastic Quad Flatpack N52
51-85042-**
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-06002 Rev. *D
Page 18 of 19
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback
CY7C130/CY7C131
CY7C140/CY7C141
Document History Page
Document Title: CY7C130/CY7C131/CY7C140/CY7C141 1K x 8 Dual-Port Static RAM
Document Number: 38-06002
Issue
Orig. of
Change
REV.
**
ECN NO. Date
Description of Change
110169
122255
236751
325936
09/29/01
SZV
RBI
Change from Spec number: 38-00027 to 38-06002
Power up requirements added to Maximum Ratings Information
Removed cross information from features section
*A
*B
*C
12/26/02
See ECN
See ECN
YDT
RUY
Added pin definitions table, 52-pin PQFP package diagram and Pb-free
information
*D
393153
See ECN
YIM
Added CY7C131-15JI to ordering information
Added Pb-Free parts to ordering information:
CY7C131-15JXI
Document #: 38-06002 Rev. *D
Page 19 of 19
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