CY7C1311BV18-278BZC [CYPRESS]
18-Mbit QDR⑩-II SRAM 4-Word Burst Architecture; 18 - Mbit的QDR ™-II SRAM 4字突发架构
| 型号： | CY7C1311BV18-278BZC |
| 厂家： | 
CYPRESS |
| 描述： | 18-Mbit QDR⑩-II SRAM 4-Word Burst Architecture |
| 文件： | 总28页 (文件大小：501K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
18-Mbit QDR™-II SRAM 4-Word
Burst Architecture
Features
Functional Description
• Separate Independent Read and Write data ports
— Supports concurrent transactions
The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and
CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR™-II architecture. QDR-II architecture
consists of two separate ports to access the memory array.
The Read port has dedicated Data Outputs to support Read
operations and the Write port has dedicated Data Inputs to
support Write operations. QDR-II architecture has separate
data inputs and data outputs to completely eliminate the need
to “turn-around” the data bus required with common I/O
devices. Access to each port is accomplished through a
common address bus. Addresses for Read and Write
addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the QDR-II Read and Write ports are
completely independent of one another. In order to maximize
data throughput, both Read and Write ports are equipped with
Double Data Rate (DDR) interfaces. Each address location is
associated with four 8-bit words (CY7C1311BV18) or 9-bit
words (CY7C1911BV18) or 18-bit words (CY7C1313BV18) or
36-bit words (CY7C1315BV18) that burst sequentially into or
out of the device. Since data can be transferred into and out
of the device on every rising edge of both input clocks (K and
K and C and C), memory bandwidth is maximized while simpli-
fying system design by eliminating bus “turn-arounds”.
• 300-MHz clock for high bandwidth
• 4-Word Burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces on both Read and
Write ports (data transferred at 600 MHz) at 300 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches
• Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• Available in x 8, x 9, x 18, and x 36 configurations
• Full data coherency providing most current data
• Core VDD = 1.8 (±0.1V); I/O VDDQ = 1.4V to VDD
• Available in 165-ballFBGA package (13 x 15 x 1.4 mm)
• Offered in both lead-free and non-lead free packages
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
• Variable drive HSTL output buffers
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1311BV18 – 2M x 8
CY7C1911BV18 – 2M x 9
CY7C1313BV18 – 1M x 18
CY7C1315BV18 – 512K x 36
Selection Guide
300 MHz
300
278 MHz
250 MHz
250
200 MHz
200
167 MHz
167
Unit
MHz
mA
Maximum Operating Frequency
Maximum Operating Current
278
530
550
500
450
400
Cypress Semiconductor Corporation
Document Number: 38-05620 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 27, 2006
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CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Logic Block Diagram (CY7C1311BV18)
D[7:0]
8
Write Write Write Write
Address
Register
A(18:0)
Reg
Reg Reg
Reg
19
Address
Register
A(18:0)
19
RPS
C
K
K
Control
Logic
CLK
Gen.
DOFF
Read Data Reg.
32
CQ
CQ
C
16
VREF
Reg.
Reg.
Reg.
WPS
Control
Logic
16
NWS[1:0]
8
Q[7:0]
8
Logic Block Diagram (CY7C1911BV18)
D[8:0]
9
Write
Reg
Write Write
Write
Reg
Address
Register
A(18:0)
Reg
Reg
19
Address
Register
A(18:0)
19
RPS
K
K
Control
Logic
CLK
Gen.
C
DOFF
Read Data Reg.
36
C
CQ
CQ
18
VREF
WPS
Reg.
Reg.
Reg.
Control
Logic
18
BWS[0]
9
Q[8:0]
9
Document Number: 38-05620 Rev. *C
Page 2 of 28
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CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Logic Block Diagram (CY7C1313BV18)
D[17:0]
18
Write Write Write Write
Address
Register
A(17:0)
Reg
Reg Reg
Reg
18
Address
Register
A(17:0)
18
RPS
C
K
K
Control
Logic
CLK
Gen.
DOFF
Read Data Reg.
72
C
CQ
CQ
36
VREF
Reg.
Reg.
Reg.
WPS
Control
Logic
36
BWS[1:0]
18
Q[17:0]
18
Logic Block Diagram (CY7C1315BV18)
D[35:0]
36
Write Write Write Write
Address
Register
A(16:0)
Reg
Reg Reg
Reg
17
Address
Register
A(16:0)
17
RPS
K
K
Control
Logic
CLK
Gen.
C
C
DOFF
Read Data Reg.
144
CQ
CQ
72
VREF
Reg.
Reg.
Reg.
WPS
Control
Logic
72
BWS[3:0]
36
Q[35:0]
36
Document Number: 38-05620 Rev. *C
Page 3 of 28
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CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Pin Configurations
165-ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1311BV18 (2M x 8)
1
2
3
A
6
K
9
A
10
NC/36M
11
CQ
5
7
8
RPS
A
4
WPS
NC/72M
NC/144M
A
CQ
NWS
1
NC
NC
NC
NC
NC
D4
NC
NC
NC
A
NC/288M
A
K
NWS
NC
NC
NC
NC
NC
NC
Q3
D3
NC
B
C
D
0
V
NC
A
V
SS
SS
V
V
V
V
V
SS
SS
SS
SS
SS
NC
NC
NC
NC
NC
D5
Q4
NC
Q5
V
V
V
V
V
NC
NC
NC
D2
NC
NC
Q2
NC
NC
ZQ
D1
NC
Q0
E
F
DDQ
SS
SS
SS
DDQ
V
V
V
V
V
DDQ
DD
SS
DD
DDQ
V
V
V
V
V
G
DDQ
DD
SS
DD
DDQ
V
V
V
V
V
V
V
V
V
H
J
REF
DDQ
DDQ
DD
SS
DD
DDQ
DDQ
REF
DOFF
NC
NC
NC
Q6
NC
D7
NC
V
V
V
V
V
NC
Q1
NC
NC
NC
NC
NC
DDQ
DD
SS
DD
DDQ
NC
NC
NC
NC
NC
NC
D6
NC
NC
Q7
V
V
V
V
V
NC
NC
NC
NC
NC
K
L
DDQ
DD
SS
DD
DDQ
V
V
V
V
V
DDQ
SS
SS
SS
DDQ
V
V
V
V
V
D0
NC
NC
M
N
P
SS
SS
SS
SS
SS
V
A
A
A
C
A
A
V
SS
SS
NC
A
A
A
A
A
A
TDO
TCK
A
A
TMS
TDI
R
C
CY7C1911BV18 (2M x 9)
1
2
NC/72M
NC
3
6
K
9
10
NC/36M
NC
11
5
NC
7
8
4
WPS
A
CQ
NC
NC
NC
A
NC/144M RPS
A
CQ
Q4
D4
NC
A
NC
NC/288M
A
K
BWS
A
A
NC
B
C
D
0
NC
NC
NC
Q5
NC
Q6
V
NC
V
NC
NC
NC
NC
NC
NC
SS
SS
D5
V
V
V
V
V
NC
SS
SS
SS
SS
SS
NC
NC
NC
V
V
V
V
V
V
V
V
V
V
V
D3
Q3
NC
NC
ZQ
D2
NC
Q1
E
F
DDQ
SS
SS
SS
DDQ
NC
V
V
V
V
NC
DDQ
DD
SS
DD
DDQ
DDQ
DDQ
DDQ
NC
D6
V
V
V
V
NC
G
H
J
DDQ
DD
SS
DD
V
V
V
V
DOFF
NC
V
V
V
V
DDQ
DD
DDQ
REF
REF
DDQ
SS
DD
NC
NC
Q7
NC
D8
NC
V
V
V
V
NC
Q2
NC
NC
NC
NC
D0
DDQ
DD
SS
DD
NC
NC
D7
NC
NC
Q8
V
V
V
V
NC
NC
NC
NC
NC
K
L
DDQ
DD
SS
DD
DDQ
DDQ
NC
V
V
V
V
DDQ
SS
SS
SS
NC
NC
NC
V
V
V
V
V
D1
NC
Q0
M
N
P
SS
SS
SS
SS
SS
V
A
A
A
C
A
A
V
SS
SS
NC
A
A
A
A
A
A
TDO
TCK
A
A
TMS
TDI
R
C
Document Number: 38-05620 Rev. *C
Page 4 of 28
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CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Pin Configurations (continued)
165-ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1313BV18 (1M x 18)
2
3
5
BWS
NC
A
6
K
7
9
10
NC/72M
NC
11
CQ
Q8
D8
D7
Q6
Q5
D5
1
4
WPS
A
8
CQ
NC
NC
NC
NC
NC
NC
NC/144M NC/36M
NC/288M RPS
A
A
B
C
D
E
F
1
Q9
NC
D9
K
BWS
A
A
NC
NC
NC
NC
NC
NC
0
D10
Q10
Q11
D12
Q13
V
NC
V
Q7
SS
SS
D11
NC
V
V
V
V
V
NC
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
D6
DDQ
SS
SS
SS
DDQ
DDQ
DDQ
Q12
D13
V
V
V
V
NC
DDQ
DD
SS
DD
V
V
V
V
NC
G
DDQ
DD
SS
DD
V
DOFF
NC
V
NC
V
D14
V
V
V
V
V
V
V
V
V
ZQ
D4
H
J
DDQ
REF
DDQ
DDQ
DD
SS
DD
DDQ
DDQ
REF
V
V
NC
Q4
D3
NC
Q1
NC
D0
DDQ
DD
SS
DD
NC
NC
NC
NC
NC
NC
Q15
NC
Q14
D15
D16
Q16
Q17
V
V
V
V
V
V
NC
NC
NC
NC
NC
Q3
Q2
K
L
DDQ
DD
SS
DD
DDQ
DDQ
V
V
V
V
DDQ
SS
SS
SS
V
V
V
V
V
D2
D1
Q0
M
N
P
SS
SS
SS
SS
SS
D17
NC
V
A
A
A
C
A
A
V
SS
SS
A
A
A
A
A
A
R
TDO
A
A
TMS
TDI
TCK
C
CY7C1315BV18 (512K x 36)
7
1
2
3
8
9
10
11
CQ
Q8
D8
D7
4
WPS
A
5
BWS
BWS
A
6
K
NC/288M NC/72M
NC/36M NC/144M
A
B
C
D
CQ
BWS
RPS
A
2
3
1
Q27
D27
D28
Q29
Q30
D30
Q18
Q28
D20
D29
Q21
D22
D18
D19
Q19
Q20
D21
Q22
K
D17
D16
Q16
Q15
D14
Q13
Q17
Q7
BWS
A
0
V
NC
V
SS
SS
V
V
V
V
V
D15
D6
SS
SS
SS
SS
SS
V
V
V
V
V
Q6
Q5
D5
ZQ
D4
Q3
Q2
E
F
DDQ
SS
SS
SS
DDQ
V
V
V
V
V
Q14
D13
DDQ
DD
SS
DD
DD
DD
DD
DDQ
V
V
V
V
V
V
V
V
G
H
J
DDQ
DD
SS
DDQ
V
V
V
V
V
V
V
V
REF
REF
DDQ
DDQ
DD
SS
DDQ
DDQ
DOFF
D31
Q31
D23
V
V
V
V
D12
Q4
DDQ
DD
SS
DDQ
Q32
Q33
D33
D34
Q35
D32
Q24
Q34
D26
D35
Q23
D24
D25
Q25
Q26
V
V
V
V
Q12
D11
D10
Q10
Q9
D3
Q11
Q1
D9
K
L
DDQ
DD
SS
DD
DDQ
V
V
V
V
V
V
DDQ
SS
SS
SS
DDQ
V
V
V
V
D2
D1
Q0
M
N
P
SS
SS
SS
SS
SS
V
A
A
A
C
A
A
V
SS
SS
D0
A
A
A
A
A
A
TDO
TCK
A
A
TMS
TDI
R
C
Document Number: 38-05620 Rev. *C
Page 5 of 28
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CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Pin Definitions
Pin Name
I/O
Pin Description
Data input signals, sampled on the rising edge of K and K clocks during valid write opera-
D[x:0]
Input-
Synchronous tions.
CY7C1311BV18 − D[7:0]
CY7C1911BV18 − D[8:0]
CY7C1313BV18 − D[17:0]
CY7C1315BV18 − D[35:0]
Input-
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active,
WPS
Synchronous a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port
will cause D[x:0] to be ignored.
Input-
Synchronous the K and K clocks during Write operations. Used to select which nibble is written into the device
NWS0 controls D[3:0] and NWS1 controls D[7:4]
Nibble Write Select 0, 1 − active LOW.(CY7C1311BV18 Only) Sampled on the rising edge of
NWS0,
NWS1
,
.
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble
Write Select will cause the corresponding nibble of data to be ignored and not written into the
device.
Input-
Byte Write Select 0, 1, 2, and 3 − active LOW. Sampled on the rising edge of the K and K clocks
BWS0,BWS1,
BWS2, BWS3
Synchronous during Write operations. Used to select which byte is written into the device during the current
portion of the Write operations. Bytes not written remain unaltered.
CY7C1911BV18 − BWS0 controls D[8:0]
CY7C1313BV18 − BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1315BV18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and
BWS3 controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
A
Input-
Address Inputs. Sampled on the rising edge of the K clock during active Read and Write opera-
Synchronous tions. These address inputs are multiplexed for both Read and Write operations. Internally, the
device is organized as 2M x 8 (4 arrays each of 512K x 8) for CY7C1311BV18, 2M x 9 (4 arrays
each of 512K x 9) for CY7C1911BV18,1M x 18 (4 arrays each of 256K x 18) for CY7C1313BV18
and 512K x 36 (4 arrays each of 128K x 36) for CY7C1315BV18. Therefore, only 19 address
inputs are needed to access the entire memory array of CY7C1311BV18 and CY7C1911BV18,
18 address inputs for CY7C1313BV18 and 17 address inputs for CY7C1315BV18. These inputs
are ignored when the appropriate port is deselected.
Q[x:0]
Outputs-
Data Output signals. These pins drive out the requested data during a Read operation. Valid
Synchronous data is driven out on the rising edge of both the C and C clocks during Read operations or K and
K. when in single clock mode. When the Read port is deselected, Q[x:0] are automatically
tri-stated.
CY7C1311BV18 − Q[7:0]
CY7C1911BV18 − Q[8:0]
CY7C1313BV18 − Q[17:0]
CY7C1315BV18 − Q[35:0]
RPS
Input-
Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When
Synchronous active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When
deselected, the pending access is allowed to complete and the output drivers are automatically
tri-stated following the next rising edge of the C clock. Each Read access consists of a burst of
four sequential transfers.
C
C
K
K
Input-
Clock
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
Input-
Clock
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
Input-
Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated
on the rising edge of K.
Input-
Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the
device and to drive out data through Q[x:0] when in single clock mode.
Document Number: 38-05620 Rev. *C
Page 6 of 28
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CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Pin Definitions (continued)
Pin Name
CQ
I/O
Pin Description
Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized to the input
clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect
to K. The timings for the echo clocks are shown in the AC Timing table.
Echo Clock
CQ
ZQ
CQ is referenced with respect to C. This is a free running clock and is synchronized to the input
clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect
to K. The timings for the echo clocks are shown in the AC Timing table.
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a
resistor connected between ZQ and ground. Alternately, this pin can be connected directly to
VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to
GND or left unconnected.
Input
DLL Turn Off - active LOW. Connecting this pin to ground will turn off the DLL inside the device.
The timings in the DLL turned off operation will be different from those listed in this data sheet.
DOFF
TDO
Output
Input
Input
Input
N/A
TDO for JTAG.
TCK
TCK pin for JTAG.
TDI
TDI pin for JTAG.
TMS
TMS pin for JTAG.
NC
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs and outputs
NC/36M
NC/72M
NC/144M
NC/288M
VREF
N/A
N/A
N/A
N/A
Input-
Reference as well as AC measurement points.
VDD
VSS
Power Supply Power supply inputs to the core of the device.
Ground
Ground for the device.
VDDQ
Power Supply Power supply inputs for the outputs of the device.
All synchronous data inputs (D[x:0]) inputs pass through input
registers controlled by the input clocks (K and K). All
synchronous data outputs (Q[x:0]) outputs pass through output
registers controlled by the rising edge of the output clocks (C
and C or K and K when in single-clock mode).
Functional Overview
The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18,
CY7C1315BV18 are synchronous pipelined Burst SRAMs
equipped with both a Read port and a Write port. The Read
port is dedicated to Read operations and the Write port is
dedicated to Write operations. Data flows into the SRAM
through the Write port and out through the Read port. These
devices multiplex the address inputs in order to minimize the
number of address pins required. By having separate Read
and Write ports, the QDR-II completely eliminates the need to
“turn-around” the data bus and avoids any possible data
contention, thereby simplifying system design. Each access
consists of four 8-bit data transfers in the case of
CY7C1311BV18, four 9-bit data transfers in the case of
CY7C1911BV18, four 18-bit data transfers in the case of
CY7C1313BV18, and four 36-bit data in the case of
CY7C1315BV18 transfers in two clock cycles.
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the
input clocks (K and K).
CY7C1313BV18 is described in the following sections. The
same basic descriptions apply to CY7C1311BV18,
CY7C1911BV18, and CY7C1315BV18.
Read Operations
The CY7C1313BV18 is organized internally as 4 arrays of
256K x 18. Accesses are completed in a burst of four
sequential 18-bit data words. Read operations are initiated by
asserting RPS active at the rising edge of the Positive Input
Clock (K). The address presented to Address inputs are stored
in the Read address register. Following the next K clock rise,
the corresponding lowest order 18-bit word of data is driven
onto the Q[17:0] using C as the output timing reference. On the
subsequent rising edge of C the next 18-bit data word is driven
onto the Q[17:0]. This process continues until all four 18-bit data
words have been driven out onto Q[17:0]. The requested data
Accesses for both ports are initiated on the Positive Input
Clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K) and all output timing
is referenced to the output clocks (C and C or K and K when
in single clock mode).
Document Number: 38-05620 Rev. *C
Page 7 of 28
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CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
will be valid 0.45 ns from the rising edge of the output clock (C
or C or (K or K when in single-clock mode)). In order to
maintain the internal logic, each read access must be allowed
to complete. Each Read access consists of four 18-bit data
words and takes 2 clock cycles to complete. Therefore, Read
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device will ignore the
second Read request. Read accesses can be initiated on
every other K clock rise. Doing so will pipeline the data flow
such that data is transferred out of the device on every rising
edge of the output clocks (C and C or K and K when in
single-clock mode).
the user must tie C and C HIGH at power on. This function is
a strap option and not alterable during device operation.
Concurrent Transactions
The Read and Write ports on the CY7C1313BV18 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the transaction
on the other port. If the ports access the same location when a
Read follows a Write in successive clock cycles, the SRAM will
deliver the most recent information associated with the
specified address location. This includes forwarding data from
a Write cycle that was initiated on the previous K clock rise.
When the read port is deselected, the CY7C1313BV18 will first
complete the pending Read transactions. Synchronous
internal circuitry will automatically tri-state the outputs following
the next rising edge of the Positive Output Clock (C). This will
allow for a seamless transition between devices without the
insertion of wait states in a depth expanded memory.
Read accesses and Write access must be scheduled such that
one transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on
the previous state of the SRAM. If both ports were deselected,
the Read port will take priority. If a Read was initiated on the
previous cycle, the Write port will assume priority (since Read
operations can not be initiated on consecutive cycles). If a
Write was initiated on the previous cycle, the Read port will
assume priority (since Write operations can not be initiated on
consecutive cycles). Therefore, asserting both port selects
active from a deselected state will result in alternating
Read/Write operations being initiated, with the first access
being a Read.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the Positive Input Clock (K). On the following K
clock rise the data presented to D[17:0] is latched and stored
into the lower 18-bit Write Data register, provided BWS[1:0] are
both asserted active. On the subsequent rising edge of the
Negative Input Clock (K) the information presented to D[17:0]
is also stored into the Write Data register, provided BWS[1:0]
are both asserted active. This process continues for one more
cycle until four 18-bit words (a total of 72 bits) of data are
stored in the SRAM. The 72 bits of data are then written into
the memory array at the specified location. Therefore, Write
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device will ignore the
second Write request. Write accesses can be initiated on
every other rising edge of the Positive Input Clock (K). Doing
so will pipeline the data flow such that 18 bits of data can be
transferred into the device on every rising edge of the input
clocks (K and K).
Depth Expansion
The CY7C1313BV18 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the Positive Input Clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM. The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω, with
When deselected, the Write port will ignore all inputs after the
pending Write operations have been completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1313BV18.
A Write operation is initiated as described in the Write Opera-
tions section above. The bytes that are written are determined
by BWS0 and BWS1, which are sampled with each set of 18-bit
data words. Asserting the appropriate Byte Write Select input
during the data portion of a Write will allow the data being
presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write will allow the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
V
DDQ = 1.5V. The output impedance is adjusted every 1024
cycles upon power-up to account for drifts in supply voltage
and temperature.
Echo Clocks
Echo clocks are provided on the QDR-II to simplify data
capture on high-speed systems. Two echo clocks are
generated by the QDR-II. CQ is referenced with respect to C
and CQ is referenced with respect to C. These are free running
clocks and are synchronized to the output clock of the QDR-II.
In the single clock mode, CQ is generated with respect to K
and CQ is generated with respect to K. The timings for the
echo clocks are shown in the AC Timing table.
Single Clock Mode
The CY7C1313BV18 can be used with a single clock that
controls both the input and output registers. In this mode the
device will recognize only a single pair of input clocks (K and
K) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
Document Number: 38-05620 Rev. *C
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CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
DLL
DLL to be specifically reset in order to lock the DLL to the
desired frequency. The DLL will automatically lock 1024 clock
cycles after a stable clock is presented. The DLL may be
disabled by applying ground to the DOFF pin. For information
refer to the application note ‘DLL Considerations in
QDRII/DDRII/QDRII+/DDRII+.’
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency. During power-up, when the DOFF is tied HIGH, the
DLL gets locked after 1024 cycles of stable clock. The DLL can
also be reset by slowing or stopping the input clock K and K
for a minimum of 30 ns. However, it is not necessary for the
Application Example[11]
R = 250ohms
SRAM #4
R = 250ohms
ZQ
SRAM #1
R
ZQ
CQ/CQ#
Q
R W
B
W
P
B
W
S
Vt
CQ/CQ#
P
S
#
P
S
#
P
S
#
W
S
D
A
D
A
Q
S
#
R
C
C#
K
K#
C
C#
K
K#
#
#
DATA IN
DATA OUT
Address
Vt
Vt
R
RPS#
BUS
MASTER
(CPU
or
ASIC)
WPS#
BWS#
CLKIN/CLKIN#
Source K
Source K#
Delayed K
Delayed K#
R
R = 50ohms
Vt = Vddq/2
Truth Table[12, 13, 14, 15, 16, 17]
Operation
Write Cycle:
K
RPS WPS
DQ
DQ
DQ
DQ
L-H
H[8] L[9] D(A) at K(t + 1) ↑ D(A + 1) at K(t + 1) ↑ D(A + 2) at K(t + 2) ↑ D(A + 3) at K(t + 2) ↑
Load address on the
rising edge of K; input
write data on two
consecutive K and K
rising edges.
Read Cycle:
L-H
L[9]
X
Q(A) at C(t + 1) ↑ Q(A + 1) at C(t + 2) ↑ Q(A + 2) at C(t + 2)↑ Q(A + 3) at C(t + 3) ↑
Load address on the
rising edge of K; wait
one and a half cycle;
read data on two
consecutive C and C
rising edges.
NOP: No Operation
L-H
H
X
H
X
D = X
Q = High-Z
D = X
Q = High-Z
D = X
Q = High-Z
D = X
Q = High-Z
Standby: Clock
Stopped
Stopped
Previous State Previous State
Previous State
Previous State
Notes:
1. The above application shows four QDR-II being used.
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
3. Device will power-up deselected and the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst.
5. “t” represents the cycle at which a Read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the
“t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will
ignore the second Read or Write request.
Document Number: 38-05620 Rev. *C
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CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
[2, 10]
Write Cycle Descriptions (CY7C1311BV18 and CY7C1313BV18)
BWS0/NWS0 BWS1/NWS1
K
K
Comments
During the Data portion of a Write sequence:
CY7C1311BV18 − both nibbles (D[7:0]) are written into the device,
CY7C1313BV18 − both bytes (D[17:0]) are written into the device.
L
L
L
L
L
L–H
–
–
L-H During the Data portion of a Write sequence:
CY7C1311BV18 − both nibbles (D[7:0]) are written into the device,
CY7C1313BV18 − both bytes (D[17:0]) are written into the device.
H
L–H
–
During the Data portion of a Write sequence :
CY7C1311BV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will
remain unaltered,
CY7C1313BV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will
remain unaltered.
L
H
H
H
L
L
–
L–H
–
L–H During the Data portion of a Write sequence :
CY7C1311BV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will
remain unaltered,
CY7C1313BV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will
remain unaltered.
–
During the Data portion of a Write sequence :
CY7C1311BV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will
remain unaltered,
CY7C1313BV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will
remain unaltered.
L–H During the Data portion of a Write sequence :
CY7C1311BV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will
remain unaltered,
CY7C1313BV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will
remain unaltered.
H
H
H
H
L–H
–
–
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
Note:
10. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS0, NWS1, BWS0, BWS1, BWS2 and BWS3 can be altered on different
portions of a Write cycle, as long as the set-up and hold requirements are achieved.
Document Number: 38-05620 Rev. *C
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CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Write Cycle Descriptions(CY7C1315BV18)[2, 10]
BWS0 BWS1 BWS2 BWS3
K
K
Comments
L
L
L
L
L–H
–
During the Data portion of a Write sequence, all four bytes (D[35:0]) are written
into the device.
L
L
L
L
–
L–H
–
L–H During the Data portion of a Write sequence, all four bytes (D[35:0]) are written
into the device.
L
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
–
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] will remain unaltered.
L
L–H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] will remain unaltered.
H
H
H
H
H
H
L–H
–
–
During the Data portion of a Write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] will remain unaltered.
L
L–H During the Data portion of a Write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] will remain unaltered.
H
H
H
H
L–H
–
–
During the Data portion of a Write sequence, only the byte (D[26:18]) is written
into the device. D[17:0] and D[35:27] will remain unaltered.
L
L–H During the Data portion of a Write sequence, only the byte (D[26:18]) is written
into the device. D[17:0] and D[35:27] will remain unaltered.
H
H
L–H
–
During the Data portion of a Write sequence, only the byte (D[35:27]) is written
into the device. D[26:0] will remain unaltered.
L
L–H During the Data portion of a Write sequence, only the byte (D[35:27]) is written
into the device. D[26:0] will remain unaltered.
H
H
H
H
H
H
H
H
L–H
–
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Write Cycle Descriptions (CY7C1911BV18)[2, 10]
BWS0
K
L–H
–
K
L
L
–
During the Data portion of a Write sequence, the single byte (D[8:0]) is written into the device.
L–H During the Data portion of a Write sequence, the single byte (D[8:0]) is written into the device.
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
H
H
L–H
–
–
Document Number: 38-05620 Rev. *C
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CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
TDI and TDO pins as shown in TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant
with IEEE Standard #1149.1-1900. The TAP operates using
JEDEC standard 1.8V I/O logic levels.
When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Access Port—Test Clock
Boundary Scan Register
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
Test Mode Select
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.
TAP Instruction Set
Performing a TAP Reset
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
Document Number: 38-05620 Rev. *C
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CY7C1911BV18
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CY7C1315BV18
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the in-
struction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is cap-
tured in the boundary scan register.
EXTEST OUTPUT BUS TRI-STATE
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possi-
ble that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #47.
When this scan cell, called the “extest output bus tristate”, is
latched into the preload register during the “Update-DR” state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the bound-
ary scan register between the TDI and TDO pins.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
Document Number: 38-05620 Rev. *C
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CY7C1911BV18
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TAP Controller State Diagram[11]
TEST-LOGIC
1
RESET
0
1
1
1
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note:
11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 38-05620 Rev. *C
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TAP Controller Block Diagram
0
Bypass Register
Selection
TDI
Selection
Circuitry
2
1
0
0
0
TDO
Circuitry
Instruction Register
29
31 30
.
.
2
1
Identification Register
.
106 .
.
.
2
1
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[12, 15, 16]
Parameter
VOH1
Description
Output HIGH Voltage
Test Conditions
IOH = −2.0 mA
Min.
1.4
Max.
Unit
V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
IOH = −100 µA
IOL = 2.0 mA
IOL = 100 µA
1.6
V
0.4
0.2
V
V
0.65VDD
–0.3
VDD + 0.3
0.35VDD
5
V
VIL
Input LOW Voltage
V
IX
Input and Output Load Current
GND ≤ VI ≤ VDD
–5
µA
TAP AC Switching Characteristics Over the Operating Range [13, 14]
Parameter
tTCYC
Description
Min.
Max.
Unit
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
50
tTF
20
MHz
ns
tTH
20
20
tTL
TCK Clock LOW
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
5
5
5
ns
ns
ns
tTDIS
tCS
Hold Times
tTMSH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
ns
ns
tTDIH
Notes:
12. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.
13. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
14. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
15. Overshoot: VIH(AC) < VDDQ + 0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > −1.5V (Pulse width less than tCYC/2).
16. All Voltage referenced to Ground.
Document Number: 38-05620 Rev. *C
Page 15 of 28
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CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
TAP AC Switching Characteristics Over the Operating Range [13, 14] (continued)
Parameter
tCH
Description
Min.
Max.
Unit
Capture Hold after Clock Rise
5
ns
Output Times
tTDOV
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
10
ns
ns
tTDOX
0
TAP Timing and Test Conditions[14]
0.9V
ALL INPUT PULSES
0.9V
1.8V
50Ω
0V
TDO
Z = 50Ω
0
C = 20 pF
L
GND
tTL
tTH
(a)
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
tTDOX
Document Number: 38-05620 Rev. *C
Page 16 of 28
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CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Identification Register Definitions
Value
CY7C1911BV18
000
Instruction Field
CY7C1311BV18
CY7C1313BV18
CY7C1315BV18
000
Description
Revision Number (31:29)
000
000
Version
number.
Cypress Device ID (28:12) 11010011011000101 11010011011001101 11010011011010101 11010011011100101 Defines the
type of SRAM.
Cypress JEDEC ID (11:1)
00000110100
00000110100
00000110100
00000110100
Allows unique
identification of
SRAM vendor.
ID Register Presence (0)
1
1
1
1
Indicates the
presence of an
ID register.
Scan Register Sizes
Register Name
Instruction
Bit Size
3
1
Bypass
ID
32
107
Boundary Scan
Instruction Codes
Instruction
EXTEST
Code
Description
Captures the Input/Output ring contents.
000
001
IDCODE
Loads the ID register with the vendor ID code and places the register
between TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register
between TDI and TDO. Forces all SRAM output drivers to a High-Z
state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan
register between TDI and TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does
not affect SRAM operation.
Document Number: 38-05620 Rev. *C
Page 17 of 28
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CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Boundary Scan Order
Bit #
0
Bump ID
6R
Bit #
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
Bump ID
11H
10G
9G
Bit #
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Bump ID
7B
6B
6A
5B
5A
4A
5C
4B
3A
1H
1A
2B
3B
1C
1B
3D
3C
1D
2C
3E
2D
2E
1E
2F
Bit #
81
Bump ID
3G
2G
1J
1
6P
82
2
6N
83
3
7P
11F
11G
9F
84
2J
4
7N
85
3K
3J
5
7R
86
6
8R
10F
11E
10E
10D
9E
87
2K
1K
2L
7
8P
88
8
9R
89
9
11P
10P
10N
9P
90
3L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
91
1M
1L
10C
11D
9C
92
93
3N
3M
1N
2M
3P
2N
2P
1P
3R
4R
4P
5P
5N
5R
10M
11N
9M
94
9D
95
11B
11C
9B
96
9N
97
11L
11M
9L
98
10B
11A
Internal
9A
99
100
101
102
103
104
105
106
10L
11K
10K
9J
8B
7C
9K
6C
3F
10J
11J
8A
1G
1F
7A
Document Number: 38-05620 Rev. *C
Page 18 of 28
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CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Power-Up Sequence in QDR-II SRAM[17, 18]
DLL Constraints
QDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
• DLL uses either K or C clock as its synchronizing input.The
input should have low phase jitter, which is specified as
tKC Var
Power-Up Sequence
• The DLL will function at frequencies down to 80 MHz
• Apply power and drive DOFF LOW (All other inputs can be
HIGH or LOW)
• If the input clock is unstable and the DLL is enabled, then
the DLL may lock to an incorrect frequency, causing
unstable SRAM behavior
— Apply VDD before VDDQ
— Apply VDDQ before VREF or at the same time as VREF
• After the power and clock (K, K, C, C) are stable take DOFF
HIGH
• The additional 1024 cycles of clocks are required for the
DLL to lock
Power-up Waveforms
K
K
Unstable Clock
> 1024 Stable clock
Start Normal
Operation
/
V
Clock Start (Clock Starts after V
Stable)
DDQ
DD
Stable (< +/- 0.1V DC per 50ns )
/
/
V
DDQ
VDDQ
V
DD
VDD
Fix High (or tied to V
)
DDQ
DOFF
Notes:
17. It is recommended that the DOFF pin be pulled HIGH via a pull up resistor of 1 Kohm.
18. During Power-Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock.
Document Number: 38-05620 Rev. *C
Page 19 of 28
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CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V
Latch-up Current.................................................... > 200 mA
Operating Range
Maximum Ratings
(Above which the useful life may be impaired.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with Power Applied..–55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +2.9V
Supply Voltage on VDDQ Relative to GND ......–0.5V to +VDD
DC Applied to Outputs in High-Z .........–0.5V to VDDQ + 0.3V
DC Input Voltage[15] ...............................–0.5V to VDD + 0.3V
Ambient
[21]
[21]
Range Temperature (TA)
VDD
1.8 ± 0.1V
VDDQ
1.4V to VDD
Com’l
Ind’l
0°C to +70°C
–40°C to +85°C
Electrical Characteristics Over the Operating Range[16]
DC Electrical Characteristics Over the Operating Range
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
1.7
Typ.
Max.
Unit
V
1.8
1.5
1.9
VDDQ
VOH
1.4
VDD
V
Output HIGH Voltage
Output LOW Voltage
Note 19
Note 20
VDDQ/2 – 0.12
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOL
VDDQ/2 + 0.12
V
VOH(LOW) Output HIGH Voltage
IOH = −0.1 mA, Nominal Impedance VDDQ – 0.2
VDDQ
0.2
V
VOL(LOW) Output LOW Voltage
IOL = 0.1 mA, Nominal Impedance
VSS
VREF + 0.1
–0.3
V
VIH
VIL
IX
Input HIGH Voltage[15]
Input LOW Voltage[15]
Input Leakage Current
Output Leakage Current
VDDQ + 0.3
VREF – 0.1
5
V
V
GND ≤ VI ≤ VDDQ
−5
µA
µA
V
IOZ
VREF
IDD
GND ≤ VI ≤ VDDQ, Output Disabled
−5
5
Input Reference Voltage[22] Typical Value = 0.75V
0.68
0.75
0.95
400
VDD Operating Supply
VDD = Max., IOUT = 0 mA, 167 MHz
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
f = fMAX = 1/tCYC
200 MHz
250 MHz
278 MHz
300 MHz
167 MHz
200 MHz
250 MHz
278 MHz
300 MHz
450
500
530
550
ISB1
Automatic Power-down
Current
Max. VDD, Both Ports
Deselected, VIN ≥ VIH or
VIN ≤ VIL
200
220
240
f = fMAX = 1/tCYC
,
Inputs Static
250
260
AC Electrical Characteristics Over the Operating Range
Parameter
Description
Input HIGH Voltage
Input LOW Voltage
Test Conditions
Min.
VREF + 0.2
–
Typ.
Max.
–
Unit
V
VIH
VIL
–
–
VREF – 0.2
V
Capacitance[23]
Parameter
Description
Test Conditions
Max.
Unit
pF
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
VDD = 1.8V
DDQ = 1.5V
5
6
7
CCLK
Clock Input Capacitance
Output Capacitance
pF
V
CO
pF
Notes:
19. Output are impedance controlled. IOH = −(VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350 Ωs.
20. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350 Ωs.
21. Power-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH< VDD and VDDQ< VDD
22. VREF (Min.) = 0.68V or 0.46VDDQ, whichever is larger, VREF (Max.) = 0.95V or 0.54VDDQ, whichever is smaller.
23. Tested initially and after any design or process change that may affect these parameters.
.
Document Number: 38-05620 Rev. *C
Page 20 of 28
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CY7C1911BV18
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CY7C1315BV18
Thermal Resistance[23]
165 FBGA
Package
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal Resistance
(Junction to Ambient) measuring thermal impedance, per EIA/JESD51.
Test conditions follow standard test methods and procedures for
28.51
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
5.91
°C/W
AC Test Loads and Waveforms
V
REF = 0.75V
0.75V
VREF
VREF
0.75V
R = 50Ω
OUTPUT
[24]
ALL INPUT PULSES
1.25V
Z = 50Ω
0
OUTPUT
Device
R = 50Ω
L
0.75V
Under
Test
Device
Under
0.25V
5 pF
VREF = 0.75V
Slew Rate = 2 V/ns
ZQ
Test
ZQ
RQ =
RQ =
250
250Ω
Ω
(a)
(b)
Note:
24. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads.
Document Number: 38-05620 Rev. *C
Page 21 of 28
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CY7C1911BV18
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CY7C1315BV18
Switching Characteristics Over the Operating Range[24,26]
300 MHz
278 MHz
250 MHz
200 MHz
167 MHz
Cypress Consortium
Parameter Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tPOWER
VDD(Typical) to the First
Access[25]
1
1
1
1
1
ms
ns
ns
ns
ns
tCYC
tKH
tKHKH
tKHKL
tKLKH
tKHKH
KClockandCClockCycle 3.30 5.25 3.60 5.25 4.0 5.25 5.0
Time
6.3
6.0
2.4
2.4
2.7
8.4
–
1.32
1.32
1.49
–
–
–
1.4
1.4
1.6
–
–
–
1.6
1.6
1.8
–
–
–
2.0
2.0
2.2
Input Clock (K/K; C/C)
HIGH
tKL
–
–
–
Input Clock (K/K; C/C)
LOW
tKHKH
–
K Clock Rise to K Clock
Rise and C to C Rise
(rising edge to rising edge)
tKHCH
tKHCH
0.0 1.45 0.0 1.55 0.0 1.8
0.0
2.2
0.0
2.7
ns
K/K Clock Rise to C/C
Clock Rise (rising edge to
rising edge)
Set-up Times
tSA
tAVKH
tIVKH
tIVKH
Address Set-up to K Clock 0.4
Rise
–
–
–
0.4
0.4
0.3
–
–
–
0.5
0.5
–
–
–
0.6
0.6
0.4
–
–
–
0.7
0.7
0.5
–
–
–
ns
ns
ns
tSC
0.4
Control Set-up to K Clock
Rise (RPS, WPS)
tSCDDR
Double Data Rate Control 0.3
Set-uptoClock(K, K)Rise
(BWS0, BWS1, BWS2,
BWS3)
0.35
[27]
tSD
tDVKH
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
D[X:0] Set-up to Clock
(K/K) Rise
Hold Times
tHA
tKHAX
tKHIX
tKHIX
0.4
–
–
–
0.4
0.4
0.3
–
–
–
0.5
0.5
–
–
–
0.6
0.6
0.4
–
–
–
0.7
0.7
0.5
–
–
–
ns
ns
ns
Address Hold after K
Clock Rise
tHC
Control Hold after K Clock 0.4
Rise (RPS, WPS)
tHCDDR
Double Data Rate Control 0.3
Hold after Clock (K, K)
Rise (BWS0, BWS1,
0.35
BWS2, BWS3)
tHD
tKHDX
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
D[X:0] Hold after Clock
(K/K) Rise
Output Times
tCO
tCHQV
0.45
–
0.45
–
–
–0.45
–
0.45
–
–
–0.45
–
0.45
–
–
–0.50
–
0.50
–
ns
ns
ns
C/C Clock Rise (or K/K in
single clock mode) to Data
Valid
tDOH
tCHQX
–0.45
–
–0.45
–
Data Output Hold after
Output C/C Clock Rise
(Active to Active)
tCCQO
tCHCQV
0.45
0.45
0.45
0.45
0.50
C/C Clock Rise to Echo
Clock Valid
Notes:
25. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a Read or Write operation
can be initiated.
26. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
27. For D2 data signal on CY7C1911BV18 device, tSD is 0.5 ns for 200 MHz, 250 MHz, 278 MHz and 300 MHz frequencies.
Document Number: 38-05620 Rev. *C
Page 22 of 28
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CY7C1911BV18
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Switching Characteristics Over the Operating Range[24,26] (continued)
300 MHz
278 MHz
250 MHz
200 MHz
167 MHz
Cypress Consortium
Parameter Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tCQOH
tCQD
tCQDOH
tCHZ
tCHCQX
tCQHQV
tCQHQX
tCHQZ
–0.45
–
–0.45
–
–0.45
–
–
–0.45
–
–
–0.50
–
–
ns
ns
ns
ns
Echo Clock Hold after C/C
Clock Rise
Echo Clock High to Data
Valid
0.27
–
0.27
–
0.30
–
0.35
–
0.40
–
Echo Clock High to Data –0.27
Invalid
–0.27
–
–0.30
–
–0.35
–
–0.40
–
–
0.45
0.45
0.45
0.45
0.50
Clock (C/C)
Rise to High-Z
(Active to High-Z)[28, 29]
tCLZ
tCHQX1
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
Clock (C/C) Rise to
Low-Z[28, 29]
DLL Timing
tKC Var
tKC Var
Clock Phase Jitter
–
0.20
–
–
0.20
–
–
0.20
–
–
0.20
–
–
0.20
–
ns
Cycles
ns
tKC lock
tKC lock
tKC Reset
DLL Lock Time (K, C)
K Static to DLL Reset
1024
30
1024
30
1024
30
1024
30
1024
30
tKC Reset
Notes:
28. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
29. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO
.
Document Number: 38-05620 Rev. *C
Page 23 of 28
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CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Switching Waveforms[30, 31, 32]
Read/Write/Deselect Sequence
NOP
6
NOP
1
WRITE
3
READ
4
WRITE
5
READ
2
7
K
t
t
t
t
t
KHKH
KH
KL
SC
CYC
K
RPS
t
HC
t
t
SC
HC
WPS
A
A0
A1
A2
A3
t
t
HD
t
t
HD
SA
HA
t
t
SD
SD
D13
D30
D31
D12
D32
D33
D10
Q00
D11
D
Q
Q20
CQDOH
Q21
Q22
Q01
Q02
Q03
Q23
CHZ
t
t
t
CO
t
KHCH
t
CLZ
t
t
t
KHCH
DOH
CQD
C
t
t
t
t
KHKH
KH
CYC
KL
C
CQ
CQ
t
CCQO
t
CQOH
t
CCQO
t
CQOH
DON’T CARE
UNDEFINED
Notes:
30. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.
31. Output are disabled (High-Z) one clock cycle after a NOP.
32. In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole
diagram.
Document Number: 38-05620 Rev. *C
Page 24 of 28
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CY7C1911BV18
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Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
167 CY7C1311BV18-167BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Commercial
CY7C1911BV18-167BZC
CY7C1313BV18-167BZC
CY7C1315BV18-167BZC
CY7C1311BV18-167BZXC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1911BV18-167BZXC
CY7C1313BV18-167BZXC
CY7C1315BV18-167BZXC
CY7C1311BV18-167BZI
CY7C1911BV18-167BZI
CY7C1313BV18-167BZI
CY7C1315BV18-167BZI
51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Industrial
CY7C1311BV18-167BZXI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1911BV18-167BZXI
CY7C1313BV18-167BZXI
CY7C1315BV18-167BZXI
200 CY7C1311BV18-200BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Commercial
CY7C1911BV18-200BZC
CY7C1313BV18-200BZC
CY7C1315BV18-200BZC
CY7C1311BV18-200BZXC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1911BV18-200BZXC
CY7C1313BV18-200BZXC
CY7C1315BV18-200BZXC
CY7C1311BV18-200BZI
CY7C1911BV18-200BZI
CY7C1313BV18-200BZI
CY7C1315BV18-200BZI
51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Industrial
CY7C1311BV18-200BZXI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1911BV18-200BZXI
CY7C1313BV18-200BZXI
CY7C1315BV18-200BZXI
250 CY7C1311BV18-250BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Commercial
CY7C1911BV18-250BZC
CY7C1313BV18-250BZC
CY7C1315BV18-250BZC
CY7C1311BV18-250BZXC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1911BV18-250BZXC
CY7C1313BV18-250BZXC
CY7C1315BV18-250BZXC
Document Number: 38-05620 Rev. *C
Page 25 of 28
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CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
250 CY7C1311BV18-250BZI
CY7C1911BV18-250BZI
CY7C1313BV18-250BZI
CY7C1315BV18-250BZI
51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Industrial
Commercial
Industrial
CY7C1311BV18-250BZXI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1911BV18-250BZXI
CY7C1313BV18-250BZXI
CY7C1315BV18-250BZXI
278 CY7C1311BV18-278BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1911BV18-278BZC
CY7C1313BV18-278BZC
CY7C1315BV18-278BZC
CY7C1311BV18-278BZXC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1911BV18-278BZXC
CY7C1313BV18-278BZXC
CY7C1315BV18-278BZXC
CY7C1311BV18-278BZI
CY7C1911BV18-278BZI
CY7C1313BV18-278BZI
CY7C1315BV18-278BZI
51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1311BV18-278BZXI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1911BV18-278BZXI
CY7C1313BV18-278BZXI
CY7C1315BV18-278BZXI
300 CY7C1311BV18-300BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Commercial
CY7C1911BV18-300BZC
CY7C1313BV18-300BZC
CY7C1315BV18-300BZC
CY7C1311BV18-300BZXC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1911BV18-300BZXC
CY7C1313BV18-300BZXC
CY7C1315BV18-300BZXC
CY7C1311BV18-300BZI
CY7C1911BV18-300BZI
CY7C1313BV18-300BZI
CY7C1315BV18-300BZI
51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Industrial
CY7C1311BV18-300BZXI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1911BV18-300BZXI
CY7C1313BV18-300BZXI
CY7C1315BV18-300BZXI
Document Number: 38-05620 Rev. *C
Page 26 of 28
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CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Package Diagram
165-ball FBGA (13 x 15 x 1.4 mm) (51-85180)
BOTTOM VIEW
PIN 1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
PIN 1 CORNER
-0.06
Ø0.50
(165X)
+0.14
1
2
3
4
5
6
7
8
9
10
11
11 10
9
8
7
6
5
4
3
2
1
A
A
B
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
A
1.00
5.00
10.00
13.00 0.10
B
B
13.00 0.10
0.15(4X)
NOTES :
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g
JEDECREFERENCE: MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
SEATING PLANE
C
51-85180-*A
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT,NEC, and Samsung
technology. All product and company names mentioned in this document are the trademarks of their respective holders.
Document Number: 38-05620 Rev. *C
Page 27 of 28
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1311BV18
CY7C1911BV18
CY7C1313BV18
CY7C1315BV18
Document History Page
Document Title: CY7C1311BV18/CY7C1911BV18/CY7C1313BV18/CY7C1315BV18 18-Mbit QDR™-II SRAM 4-Word
Burst Architecture
Document Number: 38-05620
Orig. of
REV.
**
ECN No. Issue Date Change
Description of Change
252474
325581
See ECN
See ECN
SYT
SYT
New data sheet
*A
Removed CY7C1911BV18 from the title
Included 300-MHz Speed Bin
Added Industrial Temperature Grade
Replaced TBDs for IDD and ISB1 specs
Replaced the TBDs on the Thermal Characteristics Table to ΘJA = 28.51°C/W
and ΘJC = 5.91°C/W
Replaced TBDs in the Capacitance Table for the 165 FBGA Package
Changed the package diagram from BB165E (15 x 17 x 1.4 mm) to BB165D
(13 x 15 x 1.4 mm)
Added Lead-Free Product Information
Updated the Ordering Information by Shading and Unshading MPNs as per
availability
*B
413997
See ECN
NXR
Converted from Preliminary to Final
Added CY7C1911BV18 to the title
Added 278-MHz speed Bin
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed C/C Description in the features section
Added power-up sequence details and waveforms
Added foot notes# 17, 18, 19 on page# 19
Changed the description of IX from Input Load Current to Input Leakage
Current on page# 20
Modified the IDD and ISB values
Modified test condition in Footnote # 22 on page# 20 from VDDQ < VDD to
V
DDQ < VDD
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated Ordering Information Table
*C
472384
See ECN
NXR
Modified the ZQ Definition from Alternately, this pin can be connected directly
to VDD to Alternately, this pin can be connected directly to VDDQ
Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND
Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD
Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH
,
t
TDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC
Switching Characteristics table
Modified Power-Up waveform
Changed the Maximum rating of Ambient Temperature with Power Applied
from –10°C to +85°C to –55°C to +125°C
Added additional notes in the AC parameter section
Modified AC Switching Waveform
Corrected the typo In the AC Switching Characteristics Table
Updated the Ordering Information Table
Document Number: 38-05620 Rev. *C
Page 28 of 28
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