CY7C1316BV18 [CYPRESS]
18-Mbit DDR-II SRAM 2-Word Burst Architecture; 18兆位的DDR - II SRAM的2字突发架构
| 型号： | CY7C1316BV18 |
| 厂家： | 
CYPRESS |
| 描述： | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| 文件： | 总24页 (文件大小：258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
PRELIMINARY
18-Mbit DDR-II SRAM 2-Word
Burst Architecture
Features
Functional Description
• 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)
• 250-MHz clock for high bandwidth
The CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and
CY7C1320BV18 are 1.8V Synchronous Pipelined SRAM
equipped with DDR-II architecture. The DDR-II consists of an
SRAM core with advanced synchronous peripheral circuitry
and a 1-bit burst counter. Addresses for Read and Write are
latched on alternate rising edges of the input (K) clock. Write
data is registered on the rising edges of both K and K. Read
data is driven on the rising edges of C and C if provided, or on
the rising edge of K and K if C/C are not provided. Each
address location is associated with two 8-bit words in the case
of CY7C1316BV18 and two 9-bit words in the case of
CY7C1916BV18 that burst sequentially into or out of the
device. The burst counter always starts with a “0” internally in
the case of CY7C1316BV18 and CY7C1916BV18. On
CY7C1318BV18 and CY7C1320BV18, the burst counter
takes in the least significant bit of the external address and
bursts two 18-bit words in the case of CY7C1318BV18 and two
36-bit words in the case of CY7C1320BV18 sequentially into
or out of the device.
• 2-Word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces
(data transferred at 500 MHz) @ 250 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two output clocks (C and C) account for clock skew
and flight time mismatching
• Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–VDD
)
Asynchronous inputs include impedance match (ZQ).
Synchronous data outputs (Q, sharing the same physical pins
as the data inputs D) are tightly matched to the two output echo
clocks CQ/CQ, eliminating the need for separately capturing
data from each individual DDR SRAM in the system design.
Output data clocks (C/C) enable maximum system clocking
and data synchronization flexibility.
• 15 x 17 x 1.4 mm 1.0-mm pitch fBGA package,
165 ball (11x15 matrix)
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
Configurations
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
CY7C1316BV18 – 2M x 8
CY7C1916BV18 – 2M x 9
CY7C1318BV18 – 1M x 18
CY7C1320BV18 – 512K x 36
Selection Guide
250 MHz
250
200 MHz
200
167 MHz
167
Unit
MHz
mA
Maximum Operating Frequency
Maximum Operating Current
TBD
TBD
TBD
Shaded areas contain advance information.
Cypress Semiconductor Corporation
Document Number: 38-05621 Rev. **
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised July 26, 2004
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
PRELIMINARY
Logic Block Diagram (CY7C1316BV18)
Write
Reg
Write
Reg
A(19:0)
Address
Register
20
LD
K
8
Output
Logic
Control
CLK
K
R/W
Gen.
DOFF
C
C
Read Data Reg.
16
CQ
8
VREF
Reg.
Reg.
Reg.
CQ
8
R/W
Control
Logic
8
NWS[1:0]
DQ[7:0]
8
Logic Block Diagram (CY7C1916BV18)
Write
Reg
Write
Reg
A(19:0)
Address
Register
20
LD
K
9
Output
Logic
Control
CLK
K
R/W
Gen.
DOFF
C
C
Read Data Reg.
18
CQ
CQ
9
VREF
Reg.
Reg.
Reg.
9
R/W
Control
Logic
9
BWS[0]
DQ[8:0]
9
Document Number: 38-05621 Rev. **
Page 2 of 24
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
PRELIMINARY
Logic Block Diagram (CY7C1318BV18)
Burst
A0
Logic
19
Write
Reg
Write
Reg
20
A(19:0)
Address
Register
A(19:1)
LD
18
1M x 18 Array
K
K
Output
Logic
Control
CLK
Gen.
R/W
DOFF
C
C
Read Data Reg.
36
CQ
18
VREF
R/W
CQ
Reg.
Reg.
Reg.
Control
Logic
18
BWS[1:0]
18
DQ[17:0]
18
Logic Block Diagram (CY7C1320BV18)
Burst
Logic
A0
18
Write
Reg
Write
Reg
19
A(18:0)
Address
Register
A(18:1)
36
LD
512K x 36 Array
K
K
R/W
Output
Logic
Control
CLK
Gen.
DOFF
C
C
Read Data Reg.
72
CQ
CQ
36
VREF
R/W
36
Reg.
Reg.
Reg.
Control
Logic
36
BWS[3:0]
36
DQ[35:0]
36
Document Number: 38-05621 Rev. **
Page 3 of 24
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
PRELIMINARY
Pin Configurations
CY7C1316BV18 (2M × 8) – 15 × 17 FBGA
1
2
3
A
4
R/W
5
6
K
7
NC/144M
NWS0
A
8
LD
9
A
10
NC/36M
11
CQ
DQ3
NC
CQ
NC
NC
NC
NC/72M
NWS1
A
B
C
D
NC
NC
NC
NC
NC
NC
A
NC/288M
K
A
A
NC
NC
NC
NC
NC
NC
VSS
VSS
A
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
DQ4
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
NC
NC
DQ2
E
F
VDD
VDD
VDD
VDD
VDD
VSS
NC
NC
NC
DQ5
VDDQ
NC
NC
NC
G
H
J
VREF
NC
VDDQ
NC
VREF
DQ1
NC
ZQ
DOFF
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
K
L
DQ6
NC
NC
NC
DQ0
NC
NC
NC
NC
NC
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
M
N
P
DQ7
A
C
A
A
A
A
A
A
A
TDO
TCK
A
C
A
TMS
TDI
R
CY7C1916BV18 (2M × 9) – 15 × 17 FBGA
1
2
3
A
4
5
NC
6
K
7
NC/144M
BWS0
A
8
LD
9
A
10
NC/36M
11
CQ
DQ3
NC
CQ
NC
NC
NC
NC/72M
A
B
C
D
R/W
A
NC
NC
NC
NC
NC
NC
NC/288M
K
A
NC
NC
NC
NC
NC
NC
VSS
VSS
A
A
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
DQ4
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
NC
NC
DQ2
E
F
VDD
VDD
VDD
VDD
VDD
VSS
NC
NC
NC
DQ5
VDDQ
NC
NC
NC
G
H
J
VREF
NC
VDDQ
NC
VREF
DQ1
NC
ZQ
DOFF
NC
NC
NC
NC
NC
NC
NC
NC
K
L
DQ6
NC
NC
NC
DQ0
NC
NC
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
M
N
P
DQ7
A
C
A
DQ8
A
A
A
A
A
A
TDO
TCK
A
A
TMS
TDI
R
C
Document Number: 38-05621 Rev. **
Page 4 of 24
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
PRELIMINARY
Pin Configurations (continued)
CY7C1318BV18 (1M × 18) – 15 × 17 FBGA
1
2
3
A
4
5
BWS1
NC/288M
A
6
K
7
NC/144M
BWS0
A
8
9
A
10
NC/36M
11
CQ
DQ8
NC
NC/72M
A
B
C
D
CQ
NC
NC
NC
NC
NC
NC
R/W
A
LD
A
DQ9
NC
NC
NC
K
NC
NC
NC
NC
DQ7
NC
VSS
VSS
A0
VSS
VSS
VSS
NC
DQ10
VSS
VSS
NC
NC
DQ12
NC
DQ11
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
NC
NC
DQ6
E
F
VDD
VDD
VDD
VDD
VDD
VSS
DQ5
NC
DQ13
VDDQ
NC
NC
NC
G
H
J
VREF
NC
VDDQ
NC
VREF
DQ4
NC
ZQ
DOFF
NC
NC
NC
NC
NC
DQ14
NC
NC
DQ3
DQ2
K
L
DQ15
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
DQ1
NC
NC
NC
M
N
P
DQ16
DQ17
A
C
A
NC
DQ0
A
A
A
A
A
A
TDO
TCK
A
A
TMS
TDI
R
C
CY7C1320BV18 (512K × 36) – 15 × 17 FBGA
1
2
3
4
5
BWS2
BWS3
A
6
K
7
8
9
A
10
NC/72M
11
CQ
CQ
NC
NC
NC
NC/144M NC/36M
BWS1
BWS0
A
A
B
C
D
R/W
A
LD
A
DQ27
NC
DQ18
DQ28
DQ19
K
NC
NC
NC
NC
DQ17
NC
DQ8
DQ7
DQ16
VSS
VSS
A0
VSS
VSS
VSS
DQ29
VSS
VSS
NC
NC
NC
NC
DQ30
DQ31
VREF
NC
DQ20
DQ21
DQ22
VDDQ
DQ32
DQ23
DQ24
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
DQ15
NC
DQ6
E
F
VDD
VDD
VDD
VDD
VDD
VSS
DQ5
DQ14
ZQ
NC
NC
G
H
J
VDDQ
NC
VREF
DQ13
DQ12
NC
DOFF
NC
DQ4
DQ3
DQ2
NC
NC
NC
NC
K
L
DQ33
NC
NC
NC
NC
NC
DQ35
NC
DQ34
DQ25
DQ26
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
DQ11
NC
DQ1
DQ10
DQ0
M
N
P
A
C
A
DQ9
A
A
A
A
A
A
TDO
TCK
A
C
A
TMS
TDI
R
Document Number: 38-05621 Rev. **
Page 5 of 24
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
PRELIMINARY
Pin Definitions
Pin Name
I/O
Pin Description
DQ[x:0]
Input/Output- Data Input/Output signals. Inputs are sampled on the rising edge of K and K clocks during valid
Synchronous Write operations. These pins drive out the requested data during a Read operation. Valid data is
driven out on the rising edge of both the C and C clocks during Read operations or K and K when
in single clock mode. When read access is deselected, Q[x:0] are automatically three-stated.
CY7C1316BV18 − DQ[7:0]
CY7C1916BV18 − DQ[8:0]
CY7C1318BV18 − DQ[17:0]
CY7C1320BV18 − DQ[35:0]
LD
Input-
Synchronous Load. This input is brought LOW when a bus cycle sequence is to be defined.
Synchronous This definition includes address and Read/Write direction. All transactions operate on a burst of
2 data.
NWS0, NWS1
Input-
Nibble Write Select 0, 1 − active LOW (CY7C1316BV18 only). Sampled on the rising edge of
Synchronous the K and K clocks during Write operations. Used to select which nibble is written into the device
during the current portion of the Write operations. Nibbles not written remain unaltered.
NWS0 controls D[3:0] and NWS1 controls D[7:4]
.
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble
Write Select will cause the corresponding nibble of data to be ignored and not written into the
device.
BWS0, BWS1,
Input-
Byte Write Select 0, 1, 2, and 3 − active LOW. Sampled on the rising edge of the K and K clocks
BWS2, BWS3 Synchronous during Write operations. Used to select which byte is written into the device during the current
portion of the Write operations. Bytes not written remain unaltered.
CY7C1916BV18 − BWS0 controls D[8:0]
CY7C1318BV18 − BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1320BV18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27]
.
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
A, A0
Input-
Address Inputs. These address inputs are multiplexed for both Read and Write operations.
Synchronous Internally, the device is organized as 2M x 8 (2 arrays each of 1M x 8) for CY7C1316BV18 and
2M x 9 (2 arrays each of 1M x 9) for CY7C1916BV18, a single 1M x 18 array for CY7C1318BV18,
and a single array of 512K x 36 for CY7C1320BV18.
CY7C1316BV18 – Since the least significant bit of the address internally is a “0,” only 20 external
address inputs are needed to access the entire memory array.
CY7C1916BV18 – Since the least significant bit of the address internally is a “0,” only 20 external
address inputs are needed to access the entire memory array.
CY7C1318BV18 – A0 is the input to the burst counter. These are incremented in a linear fashion
internally. 20 address inputs are needed to access the entire memory array.
CY7C1320BV18 – A0 is the input to the burst counter. These are incremented in a linear fashion
internally. 19 address inputs are needed to access the entire memory array. All the address inputs
are ignored when the appropriate port is deselected.
R/W
C
Input-
Synchronous Read/Write Input. When LD is LOW, this input designates the access type (Read
Synchronous when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the set-up and
hold times around edge of K.
Input-
Clock
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
C
Input-
Clock
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
K
Input-
Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated
on the rising edge of K.
K
Input-
Clock
Negative Input Clock Input. K is used to capture synchronous data beingpresented to the device
and to drive out data through Q[x:0] when in single clock mode.
Document Number: 38-05621 Rev. **
Page 6 of 24
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
PRELIMINARY
Pin Definitions (continued)
Pin Name
CQ
I/O
Pin Description
Output-
Clock
CQ is referenced with respect to C. This is a free running clock and is synchronized to the
output clock (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC Timing table.
CQ
ZQ
Output-
Clock
CQ is referenced with respect to C. This is a free running clock and is synchronized to the
output clock (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC Timing table.
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a
resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDD
,
which enables the minimum impedance mode. This pin cannot be connected directly to GND or
left unconnected.
DOFF
Input
DLL Turn Off, active LOW. Connecting this pin to ground will turn off the DLL inside the device.
The timings in the DLL turned off operation will be different from those listed in this data sheet.
More details on this operation can be found in the application note, “DLL Operation in the
QDR™-II.”
TDO
Output
Input
Input
Input
N/A
TDO for JTAG.
TCK
TCK pin for JTAG.
TDI
TDI pin for JTAG.
TMS
TMS pin for JTAG.
NC
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs
NC/36M
NC/72M
NC/144M
NC/288M
VREF
N/A
N/A
N/A
N/A
Input-
Reference as well as AC measurement points.
VDD
VSS
Power Supply Power supply inputs to the core of the device.
Ground
Ground for the device.
VDDQ
Power Supply Power supply inputs for the outputs of the device.
Read Operations
Functional Overview
The CY7C1318BV18 is organized internally as a single array
of 1M x 18. Accesses are completed in a burst of two
sequential 18-bit data words. Read operations are initiated by
asserting R/W HIGH and LD LOW at the rising edge of the
positive input clock (K). The address presented to Address
inputs is stored in the Read address register and the least
significant bit of the address is presented to the burst counter.
The burst counter increments the address in a linear fashion.
Following the next K clock rise the corresponding 18-bit word
of data from this address location is driven onto the Q[17:0]
using C as the output timing reference. On the subsequent
rising edge of C the next 18-bit data word from the address
location generated by the burst counter is driven onto the
The CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and
CY7C1320BV18 are synchronous pipelined Burst SRAMs
equipped with a DDR interface.
Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K) and all output timing
is referenced to the rising edge of the output clocks (C/C or
K/K when in single clock mode).
All synchronous data inputs (D[x:0]) pass through input
registers controlled by the rising edge of the input clocks (K
and K). All synchronous data outputs (Q[x:0]) pass through
output registers controlled by the rising edge of the output
clocks (C/C or K/K when in single-clock mode).
Q
[17:0]. The requested data will be valid 0.45 ns from the rising
edge of the output clock (C or C, or K and K when in single
clock mode, 200-MHz and 250-MHz device). In order to
maintain the internal logic, each read access must be allowed
to complete. Read accesses can be initiated on every rising
edge of the positive input clock (K).
All synchronous control (R/W, LD, BWS[0:X]) inputs pass
through input registers controlled by the rising edge of the
input clock (K).
CY7C1318BV18 is described in the following sections. The
same basic descriptions apply to CY7C1316BV18,
CY7C1916BV18, and CY7C1320BV18.
When Read access is deselected, the CY7C1318BV18 will
first complete the pending Read transactions. Synchronous
Document Number: 38-05621 Rev. **
Page 7 of 24
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
PRELIMINARY
internal circuitry will automatically three-state the outputs
DDR Operation
following the next rising edge of the positive output clock (C).
This will allow for a seamless transition between devices
without the insertion of wait states in a depth expanded
memory.
The CY7C1318BV18 enables high-performance operation
through high clock frequencies (achieved through pipelining)
and double data rate mode of operation. The CY7C1318BV18
requires a single No Operation (NOP) cycle when transitioning
from a Read to a Write cycle. At higher frequencies, some
applications may require a second NOP cycle to avoid
contention.
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to Address inputs is stored in the Write
address register and the least significant bit of the address is
presented to the burst counter. The burst counter increments
the address in a linear fashion. On the following K clock rise
the data presented to D[17:0] is latched and stored into the
18-bit Write Data register provided BWS[1:0] are both asserted
active. On the subsequent rising edge of the Negative Input
Clock (K) the information presented to D[17:0] is also stored
into the Write Data register provided BWS[1:0] are both
asserted active. The 36 bits of data are then written into the
memory array at the specified location. Write accesses can be
initiated on every rising edge of the positive input clock (K).
Doing so will pipeline the data flow such that 18 bits of data
can be transferred into the device on every rising edge of the
input clocks (K and K).
If a Read occurs after a Write cycle, address and data for the
Write are stored in registers. The Write information must be
stored because the SRAM cannot perform the last word Write
to the array without conflicting with the Read. The data stays
in this register until the next Write cycle occurs. On the first
Write cycle after the Read(s), the stored data from the earlier
Write will be written into the SRAM array. This is called a
Posted Write.
If a Read is performed on the same address on which a Write
is performed in the previous cycle, the SRAM reads out the
most current data. The SRAM does this by bypassing the
memory array and reading the data from the registers.
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
When Write access is deselected, the device will ignore all
inputs after the pending Write operations have been
completed.
Programmable Impedance
Byte Write Operations
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5x the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω, with
Byte Write operations are supported by the CY7C1318BV18.
A Write operation is initiated as described in the Write Opera-
tions section above. The bytes that are written are determined
by BWS0 and BWS1 which are sampled with each set of 18-bit
data word. Asserting the appropriate Byte Write Select input
during the data portion of a Write will allow the data being
presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write will allow the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
VDDQ = 1.5V. The output impedance is adjusted every 1024
cycles upon power-up to account for drifts in supply voltage
and temperature.
Echo Clocks
Echo clocks are provided on the DDR-II to simplify data
capture on high-speed systems. Two echo clocks are
generated by the DDR-II. CQ is referenced with respect to C
and CQ is referenced with respect to C. These are
free-running clocks and are synchronized to the output clock
of the DDR-II. In the single clock mode, CQ is generated with
respect to K and CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC Timing table.
Single Clock Mode
The CY7C1318BV18 can be used with a single clock that
controls both the input and output registers. In this mode the
device will recognize only a single pair of input clocks (K and
K) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C HIGH at power-on. This function is
a strap option and not alterable during device operation.
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency. The DLL may be disabled by applying ground to the
DOFF pin. The DLL can also be reset by slowing the cycle time
of input clocks K and K to greater than 30 ns.
Document Number: 38-05621 Rev. **
Page 8 of 24
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
PRELIMINARY
Application Example[1]
ZQ
ZQ
SRAM#1
LD# R/W# C C#
SRAM#2
DQ
CQ/CQ#
DQ
CQ/CQ#
K#
R = 250ohms
R = 250ohms
A
K
K#
A
LD# R/W# C C# K
DQ
Addresses
Cycle Start#
R/W#
BUS
MASTER
(CPU
Return CLK
Source CLK
Return CLK#
Source CLK#
or
ASIC)
Vterm = 0.75V
R = 50ohms
Vterm = 0.75V
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
Truth Table[2, 3, 4, 5, 6, 7]
Operation
K
LD R/W
DQ
DQ
Write Cycle:
L-H
L
L
D(A1)at K(t + 1) ↑ D(A2) at K(t + 1) ↑
Load address; wait one cycle; input write data on consecutive K
and K rising edges.
Read Cycle:
L-H
L
H
Q(A1) at C(t + 1)↑ Q(A2) at C(t + 2) ↑
Load address; wait one and a half cycle; read data on consec-
utive C and C rising edges.
NOP: No Operation
L-H
H
X
X
X
High-Z
High-Z
Standby: Clock Stopped
Stopped
Previous State
Previous State
Burst Address Table (CY7C1318BV18,
CY7C1320BV18)
First Address (External)
Second Address (Internal)
X..X0
X..X1
X..X1
X..X0
Notes:
1. The above application shows two DDR-II used.
2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
3. Device will power-up deselected and the outputs in a three-state condition.
4. On CY7C1318BV18 and CY7C1320BV18, “A1” represents address location latched by the devices when transaction was initiated and A2 represents the addresses
sequence in the burst. On CY7C1316BV18, “A1” represents A + ‘0’ and A2 represents A + ‘1’.
5. “t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
Document Number: 38-05621 Rev. **
Page 9 of 24
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
PRELIMINARY
Write Cycle Descriptions (CY7C1316BV18 and CY7C1318BV18)[2, 8]
BWS0,NWS0
BWS1,NWS1
K
K
Comments
L
L
L-H
–
During the Data portion of a Write sequence:
CY7C1316BV18 − both nibbles (D[7:0]) are written into the device,
CY7C1318BV18 − both bytes (D[17:0]) are written into the device.
L
L
L
–
L-H During the Data portion of a Write sequence:
CY7C1316BV18 − both nibbles (D[7:0]) are written into the device,
CY7C1318BV18 − both bytes (D[17:0]) are written into the device.
H
L-H
–
During the Data portion of a Write sequence:
CY7C1316BV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4]
will remain unaltered,
CY7C1318BV18 − only the lower byte (D[8:0]) is written into the device. D[17:9]
will remain unaltered.
L
H
H
H
L
L
–
L-H
–
L-H During the Data portion of a Write sequence:
CY7C1316BV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4]
will remain unaltered,
CY7C1318BV18 − only the lower byte (D[8:0]) is written into the device. D[17:9]
will remain unaltered.
–
During the Data portion of a Write sequence:
CY7C1316BV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0]
will remain unaltered,
CY7C1318BV18 − only the upper byte (D[17:9]) is written into the device. D[8:0]
will remain unaltered.
L-H During the Data portion of a Write sequence:
CY7C1316BV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0]
will remain unaltered,
CY7C1318BV18 − only the upper byte (D[17:9]) is written into the device. D[8:0]
will remain unaltered.
H
H
H
H
L-H
–
–
No data is written into the devices during this portion of a Write operation.
L-H No data is written into the devices during this portion of a Write operation.
Write Cycle Descriptions[2, 8] (CY7C1320BV18)
BWS0 BWS1 BWS2 BWS3
K
K
Comments
L
L
L
L
L-H
–
During the Data portion of a Write sequence, all four bytes (D[35:0]) are
written into the device.
L
L
L
L
–
L-H
–
L-H During the Data portion of a Write sequence, all four bytes (D[35:0]) are
written into the device.
L
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
–
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is
written into the device. D[35:9] will remain unaltered.
L
L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is
written into the device. D[35:9] will remain unaltered.
H
H
H
H
L-H
–
–
During the Data portion of a Write sequence, only the byte (D[17:9]) is
written into the device. D[8:0] and D[35:18] will remain unaltered.
L
L-H During the Data portion of a Write sequence, only the byte (D[17:9]) is
written into the device. D[8:0] and D[35:18] will remain unaltered.
H
H
H
L-H
–
–
During the Data portion of a Write sequence, only the byte (D[26:18]) is
written into the device. D[17:0] and D[35:27] will remain unaltered.
L
L-H During the Data portion of a Write sequence, only the byte (D[26:18]) is
written into the device. D[17:0] and D[35:27] will remain unaltered.
H
H
L-H
During the Data portion of a Write sequence, only the byte (D[35:27]) is
written into the device. D[26:0] will remain unaltered.
Note:
8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS , NWS , BWS , BWS , BWS , and BWS can be altered on different
0
1
0
1
2
3
portions of a Write cycle, as long as the set-up and hold requirements are achieved.
Document Number: 38-05621 Rev. **
Page 10 of 24
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
PRELIMINARY
Write Cycle Descriptions[2, 8] (CY7C1320BV18) (continued)
BWS0 BWS1 BWS2 BWS3
K
K
Comments
H
H
H
L
–
L-H During the Data portion of a Write sequence, only the byte (D[35:27]) is
written into the device. D[26:0] will remain unaltered.
H
H
H
H
H
H
H
H
L-H
–
–
No data is written into the device during this portion of a Write operation.
L-H No data is written into the device during this portion of a Write operation.
Write Cycle Descriptions[2, 8](CY7C1916BV18)
BWS0
K
K
Comments
L
L-H
–
During the Data portion of a Write sequence,
the single byte (D[8:0]) is written into the device.
L
–
L-H During the Data portion of a Write sequence,
the single byte (D[8:0]) is written into the device.
H
H
L-H
–
–
No data is written into the device during this portion of a Write operation.
L-H No data is written into the device during this portion of a Write operation.
Document Number: 38-05621 Rev. **
Page 11 of 24
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V
Latch-up Current..................................................... >200 mA
Maximum Ratings
(Above which the useful life may be impaired.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with Power Applied....–10°C to +85°C
Supply Voltage on VDD Relative to GND........ –0.5V to +2.9V
DC Applied to Outputs in High-Z......... –0.5V to VDDQ + 0.3V
DC Input Voltage[9].............................. –0.5V to VDDQ + 0.3V
Operating Range
Ambient
[10]
[10]
Range
Temperature
VDD
VDDQ
1.4V to VDD
Com’l
0°C to +70°C
1.8 ± 0.1V
Electrical Characteristics Over the Operating Range[11]
DC Electrical Characteristics
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
1.7
Typ.
1.8
Max.
Unit
V
1.9
VDDQ
VOH
1.4
1.5
VDD
V
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[9]
Input LOW Voltage[9]
Input Load Current
Note 12
Note 13
VDDQ/2 – 0.12
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOL
VDDQ/2 + 0.12
VDDQ
0.2
V
VOH(LOW)
VOL(LOW)
VIH
IOH = –0.1 mA, Nominal Impedance VDDQ – 0.2
V
IOL = 0.1 mA, Nominal Impedance
VSS
VREF + 0.1
–0.3
V
VDDQ + 0.3
VREF – 0.1
5
V
VIL
V
IX
GND ≤ VI ≤ VDDQ
–5
µA
µA
V
IOZ
Output Leakage Current
Input Reference Voltage[14] Typical Value = 0.75V
GND ≤ VI ≤ VDDQ, Output Disabled
–5
5
VREF
IDD
0.68
0.75
0.95
VDD Operating Supply
VDD = Max., IOUT= 0mA, 167 MHz
TBD
mA
mA
mA
mA
mA
mA
f = fMAX = 1/tCYC
200 MHz
250 MHz
167 MHz
200 MHz
250 MHz
TBD
TBD
ISB1
Automatic Power-down
Current
Max. VDD, Both Ports
TBD
Deselected, VIN ≥ VIH or
TBD
VIN ≤ VIL f = fMAX
=
TBD
1/tCYC, Inputs Static
AC Input Requirements
Parameter
Description
Test Conditions
Min.
VREF + 0.2
–
Typ.
Max.
–
Unit
V
VIH
VIL
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
–
–
VREF – 0.2
V
Thermal Resistance[15]
Parameter
Description
Test Conditions
165 FBGA Package Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA / JESD51.
TBD
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
TBD
°C/W
Shaded areas contain advance information.
Notes:
9. Overshoot: V (AC) < V +0.85V (Pulse width less than t
/2); Undershoot V (AC) > −1.5V (Pulse width less than t
/2).
IH
DD
TCYC
IL
TCYC
10. Power-up: Assumes a linear ramp from 0V to V (Min.) within 200 ms. During this time V < V and V
< V
.
DD
IH
DD
DDQ
DD
11. All voltage referenced to ground.
12. Outputs are impedance controlled. I = –(V
/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
OH
DDQ
13. Outputs are impedance controlled. I = (V
/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
OL
DDQ
14. V
(Min.) = 0.68V or 0.46V
, whichever is larger, V
(Max.) = 0.95V or 0.54V
, whichever is smaller.
REF
DDQ
REF
DDQ
Document Number: 38-05621 Rev. **
Page 12 of 24
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
PRELIMINARY
Capacitance[15]
Parameter
Description
Test Conditions
Max.
TBD
TBD
TBD
Unit
pF
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
DD = 1.8V
VDDQ = 1.5V
V
CCLK
CO
Clock Input Capacitance
Output Capacitance
pF
pF
AC Test Loads and Waveforms
VREF = 0.75V
0.75V
VREF
VREF
OUTPUT
Device
0.75V
R = 50Ω
OUTPUT
[14]
ALL INPUT PULSES
Z = 50Ω
0
1.25V
Device
R = 50Ω
L
0.75V
Under
Test
0.25V
5 pF
Slew Rate = 2V/ns
Under
Test
VREF = 0.75V
ZQ
ZQ
(a)
RQ =
250Ω
RQ =
250Ω
INCLUDING
JIG AND
SCOPE
(b)
Document Number: 38-05621 Rev. **
Page 13 of 24
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
PRELIMINARY
Switching Characteristics Over the Operating Range [16,17]
250 MHz
200 MHz
167 MHz
Cypress Consortium
Parameter Parameter
Description
VDD(Typical) to the first Access[18]
K Clock and C Clock Cycle Time
Input Clock (K/K and C/C) HIGH
Input Clock (K/K and C/C) LOW
Min. Max. Min. Max. Min. Max. Unit
tPOWER
1
1
1
ms
ns
ns
ns
ns
tCYC
tKH
tKHKH
tKHKL
tKLKH
tKHKH
4.0
1.6
1.6
6.3
–
5.0
2.0
2.0
2.2
7.9
–
6.0
2.4
2.4
2.7
8.4
–
tKL
–
–
–
tKHKH
K Clock Rise to K Clock Rise and C to C Rise (rising 1.8
edge to rising edge)
–
–
–
tKHCH
tKHCH
K/KClockRisetoC/CClockRise(risingedgetorisingedge) 0.0
1.8
0.0
2.2
0.0
2.7
ns
Set-up Times
tSA
tSA
tSC
tSC
Address Set-up to K Clock Rise
0.5
0.5
–
–
–
0.6
0.6
0.4
–
–
–
0.7
0.7
0.5
–
–
–
ns
ns
ns
tSC
Control Set-up to Clock (K, K) Rise (LD, R/W)
tSCDDR
Double Data Rate Control Set-up to Clock (K, K)
Rise (BWS0, BWS1, BWS2, BWS3)
0.35
tSD
tSD
D[X:0] Set-up to Clock (K and K) Rise
0.35
–
0.4
–
0.5
–
ns
Hold Times
tHA
tHA
tHC
tHC
Address Hold after Clock (K and K) Rise
0.5
–
–
–
0.6
0.6
0.4
–
–
–
0.7
0.7
0.5
–
–
–
ns
ns
ns
tHC
Control Hold after Clock (K and K) Rise (LD, R/W) 0.5
tHCDDR
Double Data Rate Control Hold after Clock (K and 0.35
K) Rise (BWS0, BWS1, BWS2, BWS3)
tHD
tHD
D[X:0] Hold after Clock (K and K) Rise
0.35
–
0.4
–
0.5
–
ns
Output Times
tCO
tCHQV
C/CClockRise(orK/Kinsingleclockmode)toDataValid
–
0.45
–
–
0.45
–
–
0.50
–
ns
ns
tDOH
tCHQX
Data Output Hold after Output C/C Clock Rise
(Active to Active)
–0.45
–0.45
–0.50
tCCQO
tCHCQV
C/C Clock Rise to Echo Clock Valid
–
0.45
–
0.45
–
0.50
ns
tCQOH
tCHCQX
tCQHQV
tCQHQX
tCHZ
Echo Clock Hold after C/C Clock Rise
Echo Clock High to Data Valid
–0.45
–
–
0.30
–
–0.45
–
–
0.35
–
–0.50
–
–
0.40
–
ns
ns
ns
ns
ns
tCQD
tCQDOH
tCHZ
Echo Clock High to Data Invalid
–0.30
–
–0.35
–
–0.40
–
Clock (C and C) Rise to High-Z (Active to High-Z)[19, 20]
Clock (C and C) Rise to Low-Z[19, 20]
0.45
–
0.45
–
0.50
–
tCLZ
tCLZ
–0.45
–0.45
–0.50
DLL Timing
tKC Var
tKC lock
tKC Reset
tKC Var
Clock Phase Jitter
–
0.20
–
–
0.20
–
–
0.20
–
ns
Cycles
ns
tKC lock
tKC Reset
DLL Lock Time (K, C)
K Static to DLL Reset
1024
30
1024
30
1024
30
Shaded areas contain advance information.
Notes:
15. Tested initially and after any design or process change that may affect these parameters.
16. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
17. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, V
= 0.75V, RQ = 250Ω, V
= 1.5V, input
DDQ
REF
pulse levels of 0.25V to 1.25V, and output loading of the specified I /I and load capacitance shown in (a) of AC Test Loads.
OL OH
18. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V minimum initially before a read or write operation
POWER
DD
can be initiated.
19. t
, t
, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
CHZ CLZ
20. At any given voltage and temperature t
is less than t
and t
less than t
.
CO
CHZ
CLZ
CHZ
Document Number: 38-05621 Rev. **
Page 14 of 24
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
PRELIMINARY
Switching Waveforms[21, 22, 23]
NOP
READ
READ
NOP
4
NOP
5
WRITE
6
WRITE
7
READ
1
8
9
10
2
3
K
t
t
t
t
KH
KL
CYC
KHKH
K
LD
t
t
HC
SC
R/W
A
A0
t
A1
A2
A3
A4
t
t
HD
HD
t
SA
HA
t
t
SD
SD
Qx2
DQ
Q00
Q01
Q10
Q11
D20
D21
D30
D31
Q40
Q41
t
t
t
t
CQD
KHCH
CO
CO
t
CHZ
DOH
t
t
t
CLZ
KHCH
t
DOH
C
t
t
t
t
KHKH
KH
KL
CYC
C#
t
CCQO
t
CQOH
CQ
t
t
CCQO
CQOH
CQ#
DON’T CARE
UNDEFINED
Notes:
21. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0 + 1.
22. Output are disabled (High-Z) one clock cycle after a NOP.
23. In this example, if address A2 = A1,then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document Number: 38-05621 Rev. **
Page 15 of 24
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
PRELIMINARY
TDI and TDO pins as shown in TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant
with IEEE Standard #1149.1-1900. The TAP operates using
JEDEC standard 1.8V I/O logic levels.
When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Access Port—Test Clock
Boundary Scan Register
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
Test Mode Select
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.
TAP Instruction Set
Performing a TAP Reset
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
Document Number: 38-05621 Rev. **
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PRELIMINARY
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
SAMPLE Z
BYPASS
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the in-
struction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is cap-
tured in the boundary scan register.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possi-
ble that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
EXTEST Output Bus Three-State
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a three-state mode.
The boundary scan register has a special bit located at bit #47.
When this scan cell, called the “extest output bus three-state”,
is latched into the preload register during the “Update-DR”
state in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the bound-
ary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells pri-
or to the selection of another boundary scan test operation.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 38-05621 Rev. **
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TAP Controller State Diagram[24]
TEST-LOGIC
1
RESET
0
1
1
1
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note:
24. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 38-05621 Rev. **
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PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
2
1
1
0
TDO
TDI
Instruction Register
29
31 30
.
.
2
0
0
Identification Register
.
106 .
.
.
2
1
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[9, 11, 25]
Parameter
VOH1
Description
Output HIGH Voltage
Test Conditions
IOH = −2.0 mA
Min.
1.4
Max.
Unit
V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
IOH = −100 µA
IOL = 2.0 mA
IOL = 100 µA
1.6
V
0.4
0.2
V
V
0.65VDD
–0.3
VDD + 0.3
0.35VDD
5
V
VIL
Input LOW Voltage
V
IX
Input and OutputLoad Current
GND ≤ VI ≤ VDD
−5
µA
TAP AC Switching Characteristics Over the Operating Range[26, 27]
Parameter
tTCYC
tTF
Description
Min.
Max.
Unit
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
50
20
MHz
ns
tTH
40
40
tTL
TCK Clock LOW
ns
Notes:
25. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
26. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
27. Test conditions are specified using the load in TAP AC test conditions. t /t = 1 ns.
R
F
Document Number: 38-05621 Rev. **
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PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range[26, 27] (continued)
Parameter
Description
Min.
Max.
Unit
Set-up Times
tTMSS
tTDIS
TMS Set-up to TCK Clock Rise
10
10
10
ns
ns
ns
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
10
10
10
ns
ns
ns
tCH
Capture Hold after Clock Rise
Output Times
tTDOV TCK Clock LOW to TDO Valid
tTDOX TCK Clock LOW to TDO Invalid
20
ns
ns
0
TAP Timing and Test Conditions[27]
0.9V
50Ω
ALL INPUT PULSES
0.9V
TDO
1.8V
Z = 50Ω
0
C = 20 pF
L
0V
tTL
tTH
GND
(a)
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
tTDOX
Document Number: 38-05621 Rev. **
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PRELIMINARY
Identification Register Definitions
Value
Instruction
Field
CY7C1316BV18
CY7C1916BV18
000
CY7C1318BV18
000
CY7C1320BV18
000
Description
Revision
Number (31:29)
000
Version number.
Cypress Device 11010100010000101 11010100010001101 11010100010010101 11010100010100101 Defines the type
ID (28:12)
of SRAM.
Cypress JEDEC
ID (11:1)
00000110100
1
00000110100
1
00000110100
1
00000110100
1
Allows unique
identification of
SRAM vendor.
ID Register
Presence (0)
Indicate the
presence of an
ID register.
Scan Register Sizes
Register Name
Instruction
Bit Size
3
1
Bypass
ID
32
107
Boundary Scan
Instruction Codes
Instruction
EXTEST
Code
Description
000
001
Captures the Input/Output ring contents.
IDCODE
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
Boundary Scan Order
Boundary Scan Order (continued)
Bit #
0
Bump ID
6R
Bit #
12
13
14
15
16
17
18
19
20
21
22
23
Bump ID
9P
1
6P
10M
11N
9M
2
6N
3
7P
4
7N
9N
5
7R
11L
11M
9L
6
8R
7
8P
8
9R
10L
11K
10K
9J
9
11P
10P
10N
10
11
Document Number: 38-05621 Rev. **
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PRELIMINARY
Boundary Scan Order (continued)
Boundary Scan Order (continued)
Bit #
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
Bump ID
Bit #
68
Bump ID
1B
3D
3C
1D
2C
3E
2D
2E
1E
2F
9K
10J
11J
11H
10G
9G
69
70
71
72
73
11F
11G
9F
74
75
76
10F
11E
10E
10D
9E
77
78
3F
79
1G
1F
80
81
3G
2G
1J
10C
11D
9C
82
83
84
2J
9D
85
3K
3J
11B
11C
9B
86
87
2K
1K
2L
88
10B
11A
Internal
9A
89
90
3L
91
1M
1L
92
8B
93
3N
3M
1N
2M
3P
2N
2P
1P
3R
4R
4P
5P
5N
5R
7C
94
6C
95
8A
96
7A
97
7B
98
6B
99
6A
100
101
102
103
104
105
106
5B
5A
4A
5C
4B
3A
1H
1A
2B
3B
1C
Document Number: 38-05621 Rev. **
Page 22 of 24
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PRELIMINARY
Ordering Information
Speed
Package
Operating
Range
(MHz)
Ordering Code
Name
Package Type
15 x 17 x 1.4 mm FBGA
250
CY7C1316BV18-250BZC
CY7C1916BV18-250BZC
CY7C1318BV18-250BZC
CY7C1320BV18-250BZC
CY7C1316BV18-200BZC
CY7C1916BV18-200BZC
CY7C1318BV18-200BZC
CY7C1320BV18-200BZC
CY7C1316BV18-167BZC
CY7C1916BV18-167BZC
CY7C1318BV18-167BZC
CY7C1320BV18-167BZC
BB165E
Commercial
Commercial
Commercial
200
167
BB165E
BB165E
15 x 17 x 1.4 mm FBGA
15 x 17 x 1.4 mm FBGA
Shaded areas contain advance information.
Package Diagram
165-Ball FBGA (15 x 17 x 1.40 mm) Pkg. Outline (0.50 Ball Dia.) BB165E
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
PIN 1 CORNER
1
+0.14
Ø0.50 (165X)
-0.06
2
3
4
5
6
7
8
9
10
11
11 10
9
8
7
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
1.00
5.00
10.00
B
15.00 0.10
0.15(4X)
SEATING PLANE
C
51-85195-**
QDR™ RAMs and Quad Data Rate™ RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC
and Samsung technology. All product and company names mentioned in this document are the trademarks of their respective
holders.
Document Number: 38-05621 Rev. **
Page 23 of 24
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Cypressproductsarenotwarrantednorintendedtobeusedformedical, life-support, life-saving, criticalcontrolorsafetyapplications, unlesspursuanttoanexpresswrittenagreementwithCypress.
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
PRELIMINARY
Document History Page
Document Title: CY7C1316BV18/CY7C1916BV18/CY7C1318BV18/CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word
Burst Architecture
Document Number: 38-05621
Orig. of
REV.
ECN No. Issue Date Change
Description of Change
**
252474
See ECN
SYT
New Data Sheet
Document Number: 38-05621 Rev. **
Page 24 of 24
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