CY7C1319KV18-250BZC [CYPRESS]
18-Mbit DDR II SRAM Four-Word Burst Architecture 333-MHz clock for high bandwidth; 18兆位的DDR II SRAM四字突发架构333 - MHz时钟实现高带宽
| 型号： | CY7C1319KV18-250BZC |
| 厂家： | 
CYPRESS |
| 描述： | 18-Mbit DDR II SRAM Four-Word Burst Architecture 333-MHz clock for high bandwidth |
| 文件： | 总33页 (文件大小：756K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
18-Mbit DDR II SRAM
Four-Word Burst Architecture
18-Mbit DDR II SRAM Four-Word Burst Architecture
Features
Configurations
■ 18-Mbit density (2 M × 8, 2 M × 9, 1 M × 18, 512 K × 36)
■ 333-MHz clock for high bandwidth
CY7C1317KV18 – 2 M × 8
CY7C1917KV18 – 2 M × 9
CY7C1319KV18 – 1 M × 18
CY7C1321KV18 – 512 K × 36
■ Four-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces
(data transferred at 666 MHz) at 333 MHz
Functional Description
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
The CY7C1317KV18, CY7C1917KV18, CY7C1319KV18, and
CY7C1321KV18 are 1.8 V Synchronous Pipelined SRAMs
equipped with DDR II architecture. The DDR II consists of an
SRAM core with advanced synchronous peripheral circuitry and
a two-bit burst counter. Addresses for read and write are latched
on alternate rising edges of the input (K) clock. Write data is
registered on the rising edges of both K and K. Read data is
driven on the rising edges of C and C if provided, or on the rising
edge of K and K if C/C are not provided. Each address location
is associated with four 8-bit words in the case of CY7C1317KV18
and four 9-bit words in the case of CY7C1917KV18 that burst
sequentially into or out of the device. The burst counter always
starts with a ‘00’ internally in the case of CY7C1317KV18 and
CY7C1917KV18. For CY7C1319KV18 and CY7C1321KV18,
the burst counter takes in the least two significant bits of the
external address and bursts four 18-bit words in the case of
CY7C1319KV18, and four 36-bit words in the case of
CY7C1321KV18, sequentially into or out of the device.
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Synchronous internally self-timed writes
■ DDR II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
■ Operates similar to DDR I device with one cycle read latency
when DOFF is asserted LOW
■ 1.8 V core power supply with HSTL inputs and outputs
■ Variable drive HSTL output buffers
■ Expanded HSTL output voltage (1.4 V–VDD
)
❐ Supports both 1.5 V and 1.8 V I/O supply
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs, D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need to capture data
separately from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
■ Available in 165-ball FBGA package (13 × 15 ×1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Phase locked loop (PLL) for accurate data placement
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
Description
Maximum operating frequency
Maximum operating current
333 MHz
300
300 MHz
300
250 MHz
250
200 MHz
200
167 MHz
167
Unit
MHz
mA
× 8
× 9
370
350
320
280
260
370
350
320
280
260
× 18
× 36
370
350
320
290
270
440
420
370
330
300
Cypress Semiconductor Corporation
Document Number: 001-58906 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 20, 2011
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Logic Block Diagram (CY7C1317KV18)
Write Write
Reg
Reg
Write
Reg
Write
Reg
19
A
(18:0)
Address
Register
8
LD
K
K
Output
R/W
CLK
Logic
Gen.
Control
C
C
DOFF
Read Data Reg.
32
16
CQ
CQ
V
8
8
8
8
REF
Reg.
Reg.
Reg.
Control
Logic
R/W
16
NWS
8
[1:0]
DQ
[7:0]
Logic Block Diagram (CY7C1917KV18)
Write Write
Reg
Reg
Write
Reg
Write
Reg
19
A
(18:0)
Address
Register
9
LD
K
K
Output
Logic
Control
CLK
R/W
Gen.
C
C
DOFF
Read Data Reg.
36
18
CQ
CQ
V
9
9
9
9
REF
Reg.
Reg.
Reg.
Control
Logic
R/W
18
BWS
9
[0]
DQ
[8:0]
Document Number: 001-58906 Rev. *D
Page 2 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Logic Block Diagram (CY7C1319KV18)
Burst
Logic
A
(1:0)
2
Write Write
Reg
Reg
Write
Reg
Write
Reg
20 18
A
A
(19:0)
Address
Register
(19:2)
18
LD
K
K
Output
R/W
CLK
Logic
Gen.
Control
C
C
DOFF
Read Data Reg.
72
36
V
18
18
18
18
REF
CQ
CQ
Reg.
Reg.
Reg.
Control
Logic
R/W
36
18
BWS
[1:0]
DQ
[17:0]
Logic Block Diagram (CY7C1321KV18)
Burst
Logic
A
(1:0)
2
Write Write
Reg
Reg
Write
Reg
Write
Reg
19 17
A
A
(18:0)
Address
Register
(18:2)
36
LD
K
K
Output
Logic
Control
CLK
R/W
Gen.
C
C
DOFF
Read Data Reg.
144
72
CQ
CQ
V
36
36
36
36
REF
Reg.
Reg.
Reg.
Control
Logic
R/W
72
36
BWS
DQ
[3:0]
[35:0]
Document Number: 001-58906 Rev. *D
Page 3 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Contents
Pin Configuration .............................................................5
165-ball FBGA (13 × 15 × 1.4 mm) Pinout ..................5
Pin Definitions ..................................................................7
Functional Overview ........................................................9
Read Operations .........................................................9
Write Operations .........................................................9
Byte Write Operations .................................................9
Single Clock Mode ......................................................9
DDR Operation ............................................................9
Depth Expansion .......................................................10
Programmable Impedance ........................................10
Echo Clocks ..............................................................10
PLL ............................................................................10
Application Example ......................................................11
Truth Table ......................................................................11
Burst Address Table ......................................................12
Write Cycle Descriptions ...............................................12
Write Cycle Descriptions ...............................................13
Write Cycle Descriptions ...............................................13
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................14
Disabling the JTAG Feature ......................................14
Test Access Port—Test Clock ...................................14
Test Mode Select (TMS) ...........................................14
Test Data-In (TDI) .....................................................14
Test Data-Out (TDO) .................................................14
Performing a TAP Reset ...........................................14
TAP Registers ...........................................................14
TAP Instruction Set ...................................................14
TAP Controller State Diagram .......................................16
TAP Controller Block Diagram ......................................17
TAP Electrical Characteristics ......................................17
TAP AC Switching Characteristics ...............................18
TAP Timing and Test Conditions ..................................18
Identification Register Definitions ................................19
Scan Register Sizes .......................................................19
Instruction Codes ...........................................................19
Boundary Scan Order ....................................................20
Power Up Sequence in DDR II SRAM ...........................21
Power Up Sequence .................................................21
PLL Constraints .........................................................21
Maximum Ratings ...........................................................22
Operating Range .............................................................22
Neutron Soft Error Immunity .........................................22
Electrical Characteristics ...............................................22
DC Electrical Characteristics .....................................22
AC Electrical Characteristics .....................................24
Capacitance ....................................................................25
Thermal Resistance ........................................................25
AC Test Loads and Waveforms .....................................25
Switching Characteristics ..............................................26
Switching Waveforms ....................................................28
Ordering Information ......................................................29
Ordering Code Definitions .........................................29
Package Diagram ............................................................30
Acronyms ........................................................................31
Document Conventions .................................................31
Units of Measure .......................................................31
Document History Page .................................................32
Sales, Solutions, and Legal Information ......................33
Worldwide Sales and Design Support .......................33
Products ....................................................................33
PSoC Solutions .........................................................33
Document Number: 001-58906 Rev. *D
Page 4 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Pin Configuration
The pin configurations for CY7C1317KV18, CY7C1917KV18, CY7C1319KV18, and CY7C1321KV18 follow. [1]
165-ball FBGA (13 × 15 × 1.4 mm) Pinout
CY7C1317KV18 (2 M × 8)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/72M
NC
3
A
4
5
NWS1
NC/288M
A
6
7
NC/144M
NWS0
A
8
9
A
10
NC/36M
NC
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
A
B
C
D
E
F
R/W
A
K
LD
NC
NC
NC
DQ4
NC
DQ5
VDDQ
NC
NC
NC
NC
NC
DQ7
A
K
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
NC
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
NC
NC
NC
NC
NC
G
H
J
NC
NC
VREF
NC
VREF
DQ1
NC
NC
NC
DQ0
NC
NC
NC
TDI
K
L
NC
DQ6
NC
NC
M
N
P
R
NC
NC
NC
NC
A
C
A
NC
TCK
A
A
C
A
A
TMS
CY7C1917KV18 (2 M × 9)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/72M
NC
3
A
4
5
NC
6
7
NC/144M
BWS0
A
8
9
A
10
NC/36M
NC
11
CQ
DQ3
NC
A
B
C
D
E
F
R/W
A
K
LD
NC
NC
NC
DQ4
NC
DQ5
VDDQ
NC
NC
NC
NC
NC
DQ7
A
NC/288M
A
K
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
NC
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
NC
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
NC
NC
NC
NC
DQ2
NC
NC
NC
G
H
J
NC
NC
NC
VREF
NC
VREF
DQ1
NC
ZQ
NC
K
L
NC
NC
DQ6
NC
NC
DQ0
NC
M
N
P
R
NC
NC
NC
NC
NC
A
C
A
NC
DQ8
TDI
TCK
A
A
C
A
A
TMS
Note
1. NC/36M, NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-58906 Rev. *D
Page 5 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Pin Configuration (continued)
The pin configurations for CY7C1317KV18, CY7C1917KV18, CY7C1319KV18, and CY7C1321KV18 follow. [1]
165-ball FBGA (13 × 15 × 1.4 mm) Pinout
CY7C1319KV18 (1 M × 18)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/72M
DQ9
NC
3
4
5
BWS1
NC/288M
A
6
7
NC/144M
BWS0
A1
8
9
A
10
NC/36M
NC
11
CQ
A
B
C
D
E
F
A
R/W
A
K
LD
NC
K
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
DQ8
NC
NC
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
DQ7
NC
NC
DQ10
DQ11
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
NC
NC
NC
DQ6
DQ5
NC
DQ12
NC
NC
G
H
J
DQ13
VDDQ
NC
NC
VREF
NC
VREF
DQ4
NC
ZQ
NC
K
L
NC
DQ14
NC
DQ3
DQ2
NC
DQ15
NC
NC
M
N
P
R
NC
DQ1
NC
NC
DQ16
DQ17
A
NC
NC
A
C
A
NC
DQ0
TDI
TCK
A
A
C
A
A
TMS
CY7C1321KV18 (512 K × 36)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
3
4
5
BWS2
BWS3
A
6
7
BWS1
BWS0
A1
8
9
A
10
NC/72M
NC
11
A
B
C
D
E
F
NC/144M NC/36M
R/W
A
K
LD
CQ
DQ27
NC
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
VDDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
A
K
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
A0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
A
DQ17
NC
DQ29
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
A
DQ15
NC
DQ30
DQ31
VREF
NC
G
H
J
NC
VREF
DQ13
DQ12
NC
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
K
L
NC
DQ33
NC
M
N
P
R
DQ11
NC
DQ35
NC
A
C
A
DQ9
TMS
TCK
A
A
C
A
A
Document Number: 001-58906 Rev. *D
Page 6 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Pin Definitions
Pin Name
I/O
Pin Description
DQ[x:0]
Input output- Data input output signals. Inputs are sampled on the rising edge of K and K clocks during valid write
synchronous operations. These pins drive out the requested data during a read operation. Valid data is driven out on
the rising edge of both the C and C clocks during read operations or K and K when in single clock mode.
When read access is deselected, Q[x:0] are automatically tristated.
CY7C1317KV18 DQ[7:0]
CY7C1917KV18 DQ[8:0]
CY7C1319KV18 DQ[17:0]
CY7C1321KV18 DQ[35:0]
LD
Input-
Synchronous load. This input is brought LOW when a bus cycle sequence is defined. This definition
synchronous includes address and read/write direction. All transactions operate on a burst of 4 data (two clock periods
of bus activity).
NWS0,
NWS1
Input-
Nibble write select 0, 1 Active LOW (CY7C1317KV18 only). Sampled on the rising edge of the K and
synchronous K clocks during write operations. Used to select which nibble is written into the device during the current
portion of the write operations. Nibbles not written remain unaltered.
NWS0 controls D[3:0] and NWS1 controls D[7:4]
.
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select
ignores the corresponding nibble of data and it is not written into the device.
BWS0,
BWS1,
BWS2,
BWS3
Input-
Byte write select 0, 1, 2, and 3 Active LOW. Sampled on the rising edge of the K and K clocks during
synchronous write operations. Used to select which byte is written into the device during the current portion of the
Write operations. Bytes not written remain unaltered.
CY7C1917KV18 BWS0 controls D[8:0]
CY7C1319KV18 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1321KV18 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27]
.
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A, A0, A1
Input-
Address inputs. These address inputs are multiplexed for both read and write operations. Internally, the
synchronous device is organized as 2 M × 8 (4 arrays each of 512 K × 8) for CY7C1317KV18 and 2 M × 9 (4 arrays
each of 512 K × 9) for CY7C1917KV18, 1 M × 18 (4 arrays each of 256 K × 18) for CY7C1319KV18,
and 512 K × 36 (4 arrays each of 128 K × 36) for CY7C1321KV18.
CY7C1317KV18 – Because the least two significant bits of the address internally are “00”, only 19
external address inputs are needed to access the entire memory array.
CY7C1917KV18 – Because the least two significant bits of the address internally are “00”, only 19
external address inputs are needed to access the entire memory array.
CY7C1319KV18 – A0 and A1 are the inputs to the burst counter. These are incremented internally in a
linear fashion. 20 address inputs are needed to access the entire memory array.
CY7C1321KV18 – A0 and A1 are the inputs to the burst counter. These are incremented internally in a
linear fashion. 19 address inputs are needed to access the entire memory array.
R/W
C
Input-
Synchronous read/write input. When LD is LOW, this input designates the access type (read when R/W
synchronous is HIGH, write when R/W is LOW) for the loaded address. R/W must meet the setup and hold times
around the edge of K.
Input clock Positive input clock for output data. C is used in conjunction with C to clock out the read data from the
device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See Application Example on page 11 for more information.
C
Input clock Negative input clock for output data. C is used in conjunction with C to clock out the read data from the
device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See Application Example on page 11 for more information.
K
Input clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device and
to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge
of K.
Document Number: 001-58906 Rev. *D
Page 7 of 33
[+] Feedback
CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Pin Definitions (continued)
Pin Name
I/O
Pin Description
K
Input clock Negative input clock input. K is used to capture synchronous data being presented to the device and to
drive out data through Q[x:0] when in single clock mode.
CQ
CQ
ZQ
Output clock CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock for
output data (C) of the DDR II. In single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in Switching Characteristics on page 26.
Output Clock CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock for
output data (C) of the DDR II. In single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in Switching Characteristics on page 26.
Input
Output impedance matching input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor connected
between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF
Input
PLL turn off Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing
in the PLL turned off operation is different from that listed in this data sheet. For normal operation, this
pin is connected to a pull up through a 10 K ohm or less pull up resistor. The device behaves in DDR I
mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to
167 MHz with DDR I timing.
TDO
Output
Input
Input
Input
N/A
TDO for JTAG.
TCK
TCK pin for JTAG.
TDI
TDI pin for JTAG.
TMS
TMS pin for JTAG.
NC
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC
NC/36M
NC/72M
NC/144M
NC/288M
VREF
N/A
N/A
N/A
N/A
Input-
reference measurement points.
VDD
VSS
Power supply Power supply inputs to the core of the device.
Ground
Ground for the device.
VDDQ
Power supply Power supply inputs for the outputs of the device.
Document Number: 001-58906 Rev. *D
Page 8 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Write Operations
Functional Overview
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to address inputs is stored in the write
address register and the least two significant bits of the address
are presented to the burst counter. The burst counter increments
the address in a linear fashion. On the following K clock rise the
data presented to D[17:0] is latched and stored into the 18-bit
write data register, provided BWS[1:0] are both asserted active.
On the subsequent rising edge of the negative input clock (K) the
information presented to D[17:0] is also stored into the write data
register, provided BWS[1:0] are both asserted active. This
process continues for one more cycle until four 18-bit words (a
total of 72 bits) of data are stored in the SRAM. The 72 bits of
data are then written into the memory array at the specified
location. Therefore, Write accesses to the device cannot be
initiated on two consecutive K clock rises. The internal logic of
the device ignores the second write request. Write accesses can
be initiated on every other rising edge of the positive input clock
(K). Doing so pipelines the data flow such that 18 bits of data can
be transferred into the device on every rising edge of the input
clocks (K and K).
The CY7C1317KV18, CY7C1917KV18, CY7C1319KV18, and
CY7C1321KV18 are synchronous pipelined Burst SRAMs
equipped with a DDR interface, which operates with a read
latency of one and half cycles when DOFF pin is tied HIGH.
When DOFF pin is set LOW or connected to VSS the device
behaves in DDR I mode with a read latency of one clock cycle.
Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K) and all output timing is
referenced to the rising edge of the output clocks (C/C, or K/K
when in single clock mode).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the rising edge of the input clocks (K and K). All
synchronous data outputs (Q[x:0]) pass through output registers
controlled by the rising edge of the output clocks (C/C, or K/K
when in single-clock mode).
All synchronous control (R/W, LD, BWS[0:X]) inputs pass through
input registers controlled by the rising edge of the input clock (K).
CY7C1319KV18 is described in the following sections. The
same basic descriptions apply to CY7C1317KV18,
CY7C1917KV18, and CY7C1321KV18.
When Write access is deselected, the device ignores all inputs
after the pending write operations are completed.
Read Operations
Byte Write Operations
The CY7C1319KV18 is organized internally as four arrays of
256 K × 18. Accesses are completed in a burst of four sequential
18-bit data words. Read operations are initiated by asserting
R/W HIGH and LD LOW at the rising edge of the positive input
clock (K). The address presented to address inputs is stored in
the read address register and the least two significant bits of the
address are presented to the burst counter. The burst counter
increments the address in a linear fashion. Following the next K
clock rise, the corresponding 18-bit word of data from this
address location is driven onto Q[17:0], using C as the output
timing reference. On the subsequent rising edge of C the next
18-bit data word from the address location generated by the
burst counter is driven onto Q[17:0]. This process continues until
all four 18-bit data words are driven out onto Q[17:0]. The
requested data is valid 0.45 ns from the rising edge of the output
clock (C or C, or K and K when in single clock mode, for 200 MHz
and 250 MHz device). To maintain the internal logic, each read
access must be allowed to complete. Each read access consists
of four 18-bit data words and takes two clock cycles to complete.
Therefore, read accesses to the device cannot be initiated on
two consecutive K clock rises. The internal logic of the device
ignores the second read request. Read accesses can be initiated
on every other K clock rise. Doing so pipelines the data flow such
that data is transferred out of the device on every rising edge of
the output clocks (C/C or K/K when in single-clock mode).
Byte write operations are supported by the CY7C1319KV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS1, which are sampled with each set of 18-bit data words.
Asserting the appropriate Byte Write Select input during the data
portion of a write latches the data being presented and writes it
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature is used to simplify
read/modify/write operations to a byte write operation.
Single Clock Mode
The CY7C1319KV18 is used with a single clock that controls
both the input and output registers. In this mode the device
recognizes only a single pair of input clocks (K and K) that control
both the input and output registers. This operation is identical to
the operation if the device had zero skew between the K/K and
C/C clocks. All timing parameters remain the same in this mode.
To use this mode of operation, tie C and C HIGH at power on.
This function is a strap option and not alterable during device
operation.
DDR Operation
The CY7C1319KV18 enables high-performance operation
through high clock frequencies (achieved through pipelining) and
double data rate mode of operation. The CY7C1319KV18
requires a single No Operation (NOP) cycle when transitioning
from a read to a write cycle. At higher frequencies, some
applications may require a second NOP cycle to avoid
contention.
The CY7C1319KV18 first completes the pending read
transactions, when read access is deselected. Synchronous
internal circuitry automatically tristates the output following the
next rising edge of the positive output clock (C). This enables a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
If a read occurs after a write cycle, address and data for the write
are stored in registers. The write information must be stored
because the SRAM cannot perform the last word write to the
array without conflicting with the read. The data stays in this
Document Number: 001-58906 Rev. *D
Page 9 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
register until the next write cycle occurs. On the first write cycle
after the read(s), the stored data from the earlier write is written
into the SRAM array. This is called a posted write.
Echo Clocks
Echo clocks are provided on the DDR II to simplify data capture
on high speed systems. Two echo clocks are generated by the
DDR II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free running clocks and are
synchronized to the output clock of the DDR II. In the single clock
mode, CQ is generated with respect to K and CQ is generated
with respect to K. The timing for the echo clocks is shown in
Switching Characteristics on page 26.
If a read is performed on the same address on which a write is
performed in the previous cycle, the SRAM reads out the most
current data. The SRAM does this by bypassing the memory
array and reading the data from the registers.
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
PLL
These chips use a PLL that is designed to function between
120 MHz and the specified maximum clock frequency. During
power up, when the DOFF is tied HIGH, the PLL is locked after
20 s of stable clock. The PLL can also be reset by slowing or
stopping the input clocks K and K for a minimum of 30 ns.
However, it is not necessary to reset the PLL to lock it to the
desired frequency. The PLL automatically locks 20 s after a
stable clock is presented. The PLL may be disabled by applying
ground to the DOFF pin. When the PLL is turned off, the device
behaves in DDR I mode (with one cycle latency and a longer
access time).
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to enable the SRAM to adjust its output
driver impedance. The value of RQ must be 5 × the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175 and 350 , with VDDQ = 1.5 V. The
output impedance is adjusted every 1024 cycles at power up to
account for drifts in supply voltage and temperature.
Document Number: 001-58906 Rev. *D
Page 10 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Application Example
Figure 1 shows two DDR II used in an application.
Figure 1. Application Example
R = 250ohms
R = 250ohms
SRAM#2
SRAM#1
ZQ
ZQ
DQ
A
DQ
A
CQ/CQ#
LD# R/W# C C# K K#
CQ/CQ#
LD# R/W# C C# K
K#
DQ
Addresses
Cycle Start#
R/W#
Return CLK
Source CLK
Return CLK#
Source CLK#
BUS
MASTER
(CPU
or
Vterm = 0.75V
R = 50ohms
Vterm = 0.75V
ASIC)
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
Truth Table
The truth table for the CY7C1317KV18, CY7C1917KV18, CY7C1319KV18, and CY7C1321KV18 follows. [2, 3, 4, 5, 6, 7]
Operation
K
LD R/W
DQ
DQ
DQ
DQ
Write cycle:
L–H
L
L D(A1) at K(t + 1) D(A2) at K(t + 1) D(A3) at K(t + 2) D(A4) at K(t + 2)
Load address; wait one cycle; input
write data on four consecutive K
and K rising edges.
Read cycle:
L–H
L
H Q(A1) at C(t + 1) Q(A2) at C(t + 2) Q(A3) at C(t + 2) Q(A4) at C(t + 3)
Load address; wait one and a half
cycle; read data on four
consecutive C and C rising edges.
NOP: No operation
L–H
H
X
X
X
High Z
High Z
High Z
High Z
Standby: Clock stopped
Stopped
Previous state
Previous state
Previous state
Previous state
Notes
2. X = ‘Don’t Care’, H = Logic HIGH, L = Logic LOW, represents rising edge.
3. Device powers up deselected with the outputs in a tristate condition.
4. On CY7C1319KV18 and CY7C1321KV18, ‘A1’ represents address location latched by the devices when transaction was initiated and ‘A2’, ‘A3’, ‘A4’ represents the
addresses sequence in the burst. On CY7C1317KV18 and CY7C1917KV18, ‘A1’ represents A + ‘00’ and ‘A2’ represents A + ‘01’, ‘A3’ represents A + ‘10’ and ‘A4’
represents A + ‘11’.
5. ‘t’ represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the ‘t’ clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
Document Number: 001-58906 Rev. *D
Page 11 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Burst Address Table
(CY7C1319KV18, CY7C1321KV18)
First Address (External)
Second Address (Internal)
Third Address (Internal)
Fourth Address (Internal)
X..X00
X..X01
X..X10
X..X11
X..X01
X..X10
X..X11
X..X00
X..X10
X..X11
X..X00
X..X01
X..X11
X..X00
X..X01
X..X10
Write Cycle Descriptions
The write cycle description table for CY7C1317KV18 and CY7C1319KV18 follows. [8, 9]
BWS0/ BWS1/
K
Comments
K
NWS0 NWS1
L
L
L
L
L–H
–
During the data portion of a write sequence
CY7C1317KV18 both nibbles (D[7:0]) are written into the device.
CY7C1319KV18 both bytes (D[17:0]) are written into the device.
–
L–H
–
L–H During the data portion of a write sequence:
CY7C1317KV18 both nibbles (D[7:0]) are written into the device.
CY7C1319KV18 both bytes (D[17:0]) are written into the device.
L
H
H
L
–
During the data portion of a write sequence:
CY7C1317KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1319KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L
L–H During the data portion of a write sequence
CY7C1317KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1319KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H
H
L–H
–
–
During the data portion of a write sequence
CY7C1317KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1319KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
L
L–H During the data portion of a write sequence
CY7C1317KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1319KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
H
H
H
L–H
–
–
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
Notes
8. X = ‘Don’t Care’, H = Logic HIGH, L = Logic LOW, represents rising edge.
9. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS , NWS , BWS , BWS , BWS , and BWS can be altered on
0
1
0
1
2
3
different portions of a write cycle, as long as the setup and hold requirements are achieved.
Document Number: 001-58906 Rev. *D
Page 12 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Write Cycle Descriptions
The write cycle description table for CY7C1917KV18 follows. [10, 11]
BWS0
K
L–H
–
K
Comments
During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
L
L
–
L–H During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
H
H
L–H
–
–
Write Cycle Descriptions
The write cycle description table for CY7C1321KV18 follows. [10, 12]
BWS0 BWS1 BWS2 BWS3
K
K
Comments
L
L
L
L
L–H
–
During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
–
L–H
–
L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
–
During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L
L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H
H
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
L
L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H
H
H
H
H
H
H
H
L–H
–
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Notes
10. X = ‘Don’t Care’, H = Logic HIGH, L = Logic LOW, represents rising edge.
11. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS , NWS , BWS , BWS , BWS , and BWS can be altered on
0
1
0
1
2
3
different portions of a write cycle, as long as the setup and hold requirements are achieved.
12. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS , NWS , BWS , BWS , BWS , and BWS can be altered on
0
1
0
1
2
3
different portions of a write cycle, as long as the setup and hold requirements are achieved.
Document Number: 001-58906 Rev. *D
Page 13 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Instruction Register
IEEE 1149.1 Serial Boundary Scan (JTAG)
Three-bit instructions are serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in TAP Controller Block Diagram on
page 17. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
These SRAMs incorporate a serial boundary scan Test Access
Port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-2001. The TAP operates using JEDEC
standard 1.8 V IO logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternatively be connected to VDD through a pull up resistor. TDO
must be left unconnected. Upon power up, the device comes up
in a reset state, which does not interfere with the operation of the
device.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions are
used to capture the contents of the input and output ring.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see the TAP Controller State
Diagram on page 16. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
The Boundary Scan Order on page 20 shows the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
Test Data-Out (TDO)
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and is shifted out when the TAP controller is in the
Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 19.
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 19).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
TAP Instruction Set
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and is performed when the SRAM is operating. At power
up, the TAP is reset internally to ensure that TDO comes up in a
high Z state.
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 19. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
TAP Registers
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction once it is shifted in, the TAP controller must be
moved into the Update-IR state.
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Document Number: 001-58906 Rev. *D
Page 14 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
IDCODE
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-Reset state.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High Z state until the next command is supplied during the
Update IR state.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
EXTEST OUTPUT BUS TRISTATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
The boundary scan register has a special bit located at bit #47.
When this scan cell, called the “extest output bus tristate,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High Z condition.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
This bit is set by entering the SAMPLE/PRELOAD or EXTEST
command, and then shifting the desired bit into that cell, during
the Shift-DR state. During Update-DR, the value loaded into that
shift-register cell latches into the preload register. When the
EXTEST instruction is entered, this bit directly controls the output
Q-bus pins. Note that this bit is pre-set HIGH to enable the output
when the device is powered up, and also when the TAP controller
is in the Test-Logic-Reset state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 001-58906 Rev. *D
Page 15 of 33
[+] Feedback
CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
TAP Controller State Diagram
The state diagram for the TAP controller follows. [13]
Test-Logic
1
Reset
0
1
1
1
Select
Test-Logic/
Select
0
IR-Scan
Idle
DR-Scan
0
0
1
1
Capture-DR
0
Capture-IR
0
0
1
0
1
SHIFT-DR
1
Shift-IR
1
Exit1-DR
0
Exit1-IR
0
0
0
Pause-DR
1
Pause-IR
1
0
0
Exit2-DR
1
Exit2-IR
1
Update-IR
0
Update-DR
1
1
0
Note
13. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-58906 Rev. *D
Page 16 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
TAP Controller Block Diagram
0
Bypass Register
2
1
1
1
0
0
0
Selection
TDI
Selection
Circuitry
TDO
Instruction Register
Circuitry
31 30
29
.
.
2
Identification Register
.
106
.
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics
Over the Operating Range
Parameter [14, 15, 16]
Description
Output HIGH voltage
Output HIGH voltage
Output LOW voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Test Conditions
IOH =2.0 mA
Min
1.4
1.6
–
Max
–
Unit
V
VOH1
VOH2
VOL1
VOL2
VIH
IOH =100 A
IOL = 2.0 mA
IOL = 100 A
–
–
V
0.4
0.2
V
–
V
0.65 × VDD VDD + 0.3
V
VIL
–
–0.3
–5
0.35 × VDD
5
V
IX
Input and output load current
GND VI VDD
A
Notes
14. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics on page 22.
15. Overshoot: V (AC) < V + 0.85 V (Pulse width less than t /2).
/2), Undershoot: V (AC) > 1.5 V (Pulse width less than t
CYC
IH
DDQ
CYC
IL
16. All voltage referenced to Ground.
Document Number: 001-58906 Rev. *D
Page 17 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
TAP AC Switching Characteristics
Over the Operating Range
Parameter [17, 18]
Description
Min
50
–
Max
–
Unit
ns
tTCYC
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
tTF
20
–
MHz
ns
tTH
20
20
tTL
TCK Clock LOW
–
ns
Setup Times
tTMSS
tTDIS
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
–
–
–
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture Hold after Clock Rise
Output Times
tTDOV
tTDOX
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
–
0
10
–
ns
ns
TAP Timing and Test Conditions
Figure 2 shows the TAP timing and test conditions. [18]
Figure 2. TAP Timing and Test Conditions
0.9 V
All Input Pulses
1.8 V
50
0.9 V
TDO
0 V
Z = 50
0
C = 20 pF
L
t
TL
t
TH
GND
(a)
Test Clock
TCK
t
TCYC
t
TMSH
t
TMSS
Test Mode Select
TMS
t
TDIS
t
TDIH
Test Data In
TDI
Test Data Out
TDO
t
TDOV
t
TDOX
Notes
17. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
18. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.
R
F
Document Number: 001-58906 Rev. *D
Page 18 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Identification Register Definitions
Value
Instruction Field
Description
CY7C1317KV18
CY7C1917KV18
000
CY7C1319KV18
000
CY7C1321KV18
Revision number
(31:29)
000
000
Version number.
Cypress device ID 11010100011000101 11010100011001101 11010100011010101 11010100011100101 Defines the type of
(28:12)
SRAM.
Cypress JEDEC ID
(11:1)
00000110100
1
00000110100
1
00000110100
1
00000110100
1
Allows unique
identification of
SRAM vendor.
ID register
presence (0)
Indicates the
presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size
Instruction
Bypass
3
1
ID
32
107
Boundary Scan
Instruction Codes
Instruction
EXTEST
Code
000
Description
Captures the input and output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High Z state.
RESERVED
011
100
Do not use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the input and output ring contents. Places the boundary scan register between TDI
and TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do not use: This instruction is reserved for future use.
Do not use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 001-58906 Rev. *D
Page 19 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Boundary Scan Order
Bit #
0
Bump ID
6R
Bit #
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
Bump ID
10G
9G
Bit #
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
Bump ID
6A
5B
5A
4A
5C
4B
3A
1H
1A
2B
3B
1C
1B
3D
3C
1D
2C
3E
2D
2E
1E
2F
Bit #
84
Bump ID
2J
1
6P
85
3K
2
6N
11F
11G
9F
86
3J
3
7P
87
2K
4
7N
88
1K
5
7R
10F
11E
10E
10D
9E
89
2L
6
8R
90
3L
7
8P
91
1M
1L
8
9R
92
9
11P
10P
10N
9P
93
3N
3M
1N
2M
3P
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
10C
11D
9C
94
95
96
10M
11N
9M
9D
97
11B
11C
9B
98
2N
2P
99
9N
100
101
102
103
104
105
106
1P
11L
11M
9L
10B
11A
Internal
9A
3R
4R
4P
10L
11K
10K
9J
5P
8B
5N
5R
7C
3F
6C
1G
1F
9K
8A
10J
11J
11H
7A
3G
2G
1J
7B
6B
Document Number: 001-58906 Rev. *D
Page 20 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
PLL Constraints
Power Up Sequence in DDR II SRAM
■ PLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var
DDR II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
.
■ The PLL functions at frequencies down to 120 MHz.
Power Up Sequence
■ If the input clock is unstable and the PLL is enabled, then the
PLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 20 s of stable clock to
relock to the desired clock frequency.
■ Apply power and drive DOFF either HIGH or LOW (All other
inputs can be HIGH or LOW).
❐ Apply VDD before VDDQ
.
❐ Apply VDDQ before VREF or at the same time as VREF
.
❐ Drive DOFF HIGH.
■ Provide stable DOFF (HIGH), power and clock (K, K) for 20 s
to lock the PLL.
Figure 3. Power Up Waveforms
K
K
Unstable Clock
> 20μs Stable clock
Stable)
DDQ
Start Normal
Operation
/
V
Clock Start (Clock Starts after V
DD
Stable (< +/- 0.1V DC per 50ns )
/
/
V
VDDQ
V
VDD
DD
DDQ
Fix HIGH (or tie to V
DDQ
)
DOFF
Document Number: 001-58906 Rev. *D
Page 21 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Maximum Ratings
Neutron Soft Error Immunity
Test
Conditions
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Parameter Description
Typ Max* Unit
LSBU
LMBU
SEL
Logical
single-bit
upsets
25 °C
197 216 FIT/
Mb
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Logical
multi-bit
upsets
25 °C
85 °C
0
0
0.01 FIT/
Mb
Supply voltage on VDD relative to GND .......–0.5 V to +2.9 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
DC applied to outputs in High Z ........–0.5 V to VDDQ + 0.3 V
DC input voltage [19] ...........................–0.5 V to VDD + 0.3 V
Current into outputs (LOW) ........................................ 20 mA
Single event
latch up
0.1
FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
2
statistical , 95% confidence limit calculation. For more details refer to
Application Note, Accelerated Neutron SER Testing and Calculation of Terrestrial
Failure Rates - AN54908.
Static discharge voltage
(MIL-STD-883, M 3015) ......................................... > 2001 V
Latch up current .................................................... > 200 mA
Operating Range
Ambient
Temperature (TA)
[20]
[20]
Range
VDD
VDDQ
Commercial
Industrial
0 °C to +70 °C
1.8 ± 0.1 V 1.4 V to VDD
–40 °C to +85 °C
Electrical Characteristics
Over the Operating Range
DC Electrical Characteristics
Over the Operating Range
Parameter [21]
VDD
Description
Test Conditions
Min
1.7
Typ
1.8
1.5
–
Max
Unit
V
Power supply voltage
I/O supply voltage
–
1.9
VDD
VDDQ
VOH
–
1.4
V
Output HIGH voltage
Output LOW voltage
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Input leakage current
Output leakage current
Note 22
VDDQ/2 – 0.12
VDDQ/2 – 0.12
VDDQ – 0.2
VSS
VDDQ/2 + 0.12
VDDQ/2 + 0.12
VDDQ
V
VOL
Note 23
–
V
VOH(LOW)
VOL(LOW)
VIH
IOH =0.1 mA, nominal impedance
–
V
IOL = 0.1 mA, nominal impedance
–
0.2
V
–
VREF + 0.1
–0.3
–
VDDQ + 0.3
VREF – 0.1
5
V
VIL
–
–
V
IX
GND VI VDDQ
5
–
A
A
V
IOZ
GND VI VDDQ, output disabled
5
–
5
VREF
Input reference voltage [24] Typical Value = 0.75 V
0.68
0.75
0.95
Notes
19. Overshoot: V (AC) < V
20. Power up: assumes a linear ramp from 0 V to V
+ 0.85 V (Pulse width less than t
/2), Undershoot: V (AC) > 1.5 V (Pulse width less than t
/2).
IH
DDQ
CYC
IL
CYC
within 200 ms. During this time V < V and V
< V
.
DD
DD(min)
IH
DD
DDQ
21. All voltage referenced to Ground.
22. Outputs are impedance controlled. I = –(V
/2)/(RQ/5) for values of 175 < RQ < 350 .
DDQ
OH
23. Outputs are impedance controlled. I = (V
/2)/(RQ/5) for values of 175 < RQ < 350 .
OL
DDQ
24. V
= 0.68 V or 0.46 V
, whichever is larger, V
(max) = 0.95 V or 0.54 V
, whichever is smaller.
REF(min)
DDQ
REF
DDQ
Document Number: 001-58906 Rev. *D
Page 22 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Electrical Characteristics (continued)
Over the Operating Range
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter [21]
Description
Test Conditions
Min
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max
370
370
370
440
350
350
350
420
320
320
320
370
280
280
290
330
260
260
270
300
Unit
[25]
IDD
VDD operating supply
VDD = Max, IOUT = 0 mA, 333 MHz (× 8)
f = fMAX = 1/tCYC
mA
(× 9)
(× 18)
(× 36)
300 MHz (× 8)
(× 9)
mA
mA
mA
mA
(× 18)
(× 36)
250 MHz (× 8)
(× 9)
(× 18)
(× 36)
200 MHz (× 8)
(× 9)
(× 18)
(× 36)
167 MHz (× 8)
(× 9)
(× 18)
(× 36)
Note
25. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-58906 Rev. *D
Page 23 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Electrical Characteristics (continued)
Over the Operating Range
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter [21]
Description
Test Conditions
Min
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max
270
270
270
270
260
260
260
260
250
250
250
250
250
250
250
250
250
250
250
250
Unit
ISB1
Automatic power down
current
Max VDD
,
333 MHz (× 8)
(× 9)
mA
Both ports deselected,
VIN VIH or VIN VIL
f = fMAX = 1/tCYC
inputs static
,
(× 18)
(× 36)
300 MHz (× 8)
(× 9)
mA
mA
mA
mA
(× 18)
(× 36)
250 MHz (× 8)
(× 9)
(× 18)
(× 36)
200 MHz (× 8)
(× 9)
(× 18)
(× 36)
167 MHz (× 8)
(× 9)
(× 18)
(× 36)
AC Electrical Characteristics
Over the Operating Range
Parameter [26]
Description
Input HIGH voltage
Input LOW voltage
Test Conditions
Min
VREF + 0.2
–
Typ
–
Max
–
Unit
V
VIH
VIL
–
–
–
VREF – 0.2
V
Note
26. Overshoot: V (AC) < V
+ 0.85 V (Pulse width less than t
/2), Undershoot: V (AC) > 1.5 V (Pulse width less than t
/2).
IH
DDQ
CYC
IL
CYC
Document Number: 001-58906 Rev. *D
Page 24 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Capacitance
Parameter [27]
Description
Input capacitance
Output capacitance
Test Conditions
Max
4
Unit
pF
CIN
CO
TA = 25 C, f = 1 MHz, VDD = 1.8 V, VDDQ = 1.5 V
4
pF
Thermal Resistance
165-ballFBGA
Package
Parameter [27]
Description
Test Conditions
Unit
JA
Thermal resistance
(junction to ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
13.7
°C/W
JC
Thermal resistance
(junction to case)
3.73
°C/W
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
VREF = 0.75 V
0.75 V
VREF
VREF
0.75 V
R = 50
Output
[28]
All Input Pulses
1.25 V
Z = 50
0
Output
Device
R = 50
L
0.75 V
Under
Device
0.25 V
Test
5 pF
Under
Test
VREF = 0.75 V
Slew Rate = 2 V/ns
ZQ
ZQ
RQ =
RQ =
250
(b)
250
Including
JIG and
Scope
(a)
Notes
27. Tested initially and after any design or process change that may affect these parameters.
28. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75 V, V
= 0.75 V, RQ = 250 , V
= 1.5 V, input
REF
DDQ
pulse levels of 0.25 V to 1.25 V, and output loading of the specified I /I and load capacitance shown in (a) of Figure 4.
OL OH
Document Number: 001-58906 Rev. *D
Page 25 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Switching Characteristics
Over the Operating Range
Parameter [29, 30]
333 MHz
300 MHz
250 MHz
200 MHz
167 MHz
Description
Unit
Cypress Consortium
Parameter Parameter
Min Max Min Max Min Max Min Max Min Max
tPOWER
tCYC
tKH
VDD(typical) to the First Access [31]
K Clock and C Clock Cycle Time 3.0 8.4 3.3 8.4 4.0 8.4 5.0 8.4 6.0 8.4
1
–
1
–
1
–
1
–
1
–
ms
ns
ns
ns
ns
tKHKH
tKHKL
tKLKH
tKHKH
Input Clock (K/K and C/C) HIGH 1.20
Input Clock (K/K and C/C) LOW 1.20
–
–
–
1.32
1.32
1.49
–
–
–
1.6
1.6
1.8
–
–
–
2.0
2.0
2.2
–
–
–
2.4
2.4
2.7
–
–
–
tKL
tKHKH
K Clock Rise to K Clock Rise and 1.35
C to C Rise (rising edge to rising
edge)
tKHCH
tKHCH
K/K Clock Rise to C/C Clock Rise 0.0 1.30 0.0 1.45 0.0 1.8 0.0 2.2 0.0 2.7
(rising edge to rising edge)
ns
Setup Times
tSA
tSC
tAVKH
tIVKH
Address Setup to K Clock Rise
0.4
–
–
0.4
0.4
–
–
0.5
0.5
–
–
0.6
0.6
–
–
0.7
0.7
–
–
ns
ns
ControlSetuptoKClockRise(LD, 0.4
R/W)
tSCDDR
tIVKH
Double Data Rate Control Setup 0.3
to Clock (K/K) Rise (BWS0,
BWS1, BWS2, BWS3)
–
–
0.3
0.3
–
–
0.35
0.35
–
–
0.4
0.4
–
–
0.5
0.5
–
–
ns
ns
tSD
tDVKH
D[X:0] Setup to Clock (K/K) Rise
0.3
Hold Times
tHA
tHC
tKHAX
tKHIX
Address Hold after K Clock Rise 0.4
–
–
0.4
0.4
–
–
0.5
0.5
–
–
0.6
0.6
–
–
0.7
0.7
–
–
ns
ns
Control Hold after K Clock Rise
(LD, R/W)
0.4
tHCDDR
tKHIX
Double Data Rate Control Hold
after Clock (K/K) Rise (BWS0,
BWS1, BWS2, BWS3)
0.3
–
–
0.3
0.3
–
–
0.35
0.35
–
–
0.4
0.4
–
–
0.5
0.5
–
–
ns
ns
tHD
tKHDX
D[X:0] Hold after Clock (K/K) Rise 0.3
Notes
29. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75 V, V
= 0.75 V, RQ = 250 , V
= 1.5 V, input
REF
DDQ
pulse levels of 0.25 V to 1.25 V, and output loading of the specified I /I and load capacitance shown in (a) of Figure 4 on page 25.
OL OH
30. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is
operated and outputs data with the output timings of that frequency range.
31. This part has an internal voltage regulator; t
is the time that the power is supplied above V minimum initially before a read or write operation can be initiated.
DD
POWER
Document Number: 001-58906 Rev. *D
Page 26 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Switching Characteristics (continued)
Over the Operating Range
Parameter [29, 30]
333 MHz
300 MHz
250 MHz
200 MHz
167 MHz
Description
Unit
Cypress Consortium
Parameter Parameter
Min Max Min Max Min Max Min Max Min Max
Output Times
tCO
tCHQV
C/C Clock Rise (or K/K in single
clock mode) to Data Valid
–
0.45
–
–
0.45
–
–
0.45
–
–
0.45
–
–
0.50 ns
ns
0.50 ns
ns
0.40 ns
tDOH
tCCQO
tCQOH
tCHQX
DataOutputHoldafterOutputC/C –0.45
Clock Rise (Active to Active)
–0.45
–
–0.45
–
–0.45
–
–0.50
–
–
tCHCQV
tCHCQX
C/C Clock Rise to Echo Clock
Valid
–
0.45
–
0.45
–
0.45
–
0.45
–
Echo Clock Hold after C/C Clock –0.45
Rise
–0.45
–0.45
–0.45
–0.50
–
tCQD
tCQHQV
tCQHQX
tCQHCQL
tCQHCQH
Echo Clock High to Data Valid
–
0.25
–
0.27
–
0.30
–
0.35
–
tCQDOH
tCQH
Echo Clock High to Data Invalid –0.25
Output Clock (CQ/CQ) HIGH [32] 1.25
–
–
–
–0.27
1.40
1.40
–
–
–
–0.30
1.75
1.75
–
–
–
–0.35
2.25
2.25
–
–
–
–0.40
2.75
2.75
–
–
–
ns
ns
ns
tCQHCQH
CQ Clock Rise to CQ Clock Rise 1.25
(rising edge to rising edge) [32]
tCHZ
tCHQZ
Clock (C/C) Rise to High Z (Active
to High Z) [33, 34]
–
0.45
–
–
0.45
–
–
0.45
–
–
0.45
–
–
0.50 ns
ns
tCLZ
tCHQX1
Clock (C/C) Rise to Low Z [33, 34] –0.45
–0.45
–0.45
–0.45
–0.50
–
PLL Timing
tKC Var
tKC Var
Clock Phase Jitter
–
0.20
–
–
0.20
–
–
0.20
–
–
0.20
–
–
0.20 ns
tKC lock
tKC lock
tKC Reset
PLL Lock Time (K, C)[35]
20
30
20
30
20
30
20
30
20
30
–
–
s
tKC Reset
K Static to PLL Reset
–
–
–
–
ns
Notes
32. These parameters are extrapolated from the input timing parameters (t
design and are not tested in production.
/2 – 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
CYC
33. t
, t
are specified with a load capacitance of 5 pF as in (b) of Figure 4 on page 25. Transition is measured 100 mV from steady-state voltage.
CHZ CLZ
34. At any voltage and temperature t
is less than t
and t
less than t
.
CHZ
CLZ
CHZ
CO
35. For frequencies 300 MHz or below, the Cypress QDR II devices surpass the QDR consortium specification for PLL lock time (t lock) of 20 µs (min. spec.) and will
KC
lock after 1024 clock cycles (min. spec.), after a stable clock is presented, per the previous 90 nm version.
Document Number: 001-58906 Rev. *D
Page 27 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Switching Waveforms
Figure 5. Read/Write/Deselect Sequence [36, 37, 38]
READ
(burst of 4)
4
READ
(burst of 4)
12
READ
(burst of 4)
2
WRITE
(burst of 4)
8
WRITE
(burst of 4)
10
NOP
1
NOP
6
NOP
7
3
5
9
11
13
K
t
t
t
t
KH KL
CYC
KHKH
K
LD
t
t
SC HC
R/W
A
A4
A2
A3
A0
A1
t
t
t
t
SA HA
HD
HD
t
t
SD
SD
DQ
Q00 Q01 Q02 Q03 Q10 Q11 Q12 Q13
D20 D21 D22 D23 D30 D31 D32 D33
Q40
t
t
CQD
t
CLZ
t
KHCH
CO
t
t
DOH
CQDOH
t
t
KHCH
CHZ
C
C
t
t
t
KH KL
t
KHKH
CYC
t
CCQO
t
CQOH
CQ
CQ
t
t
CQHCQH
CCQO
t
CQH
t
CQOH
DON’T CARE
UNDEFINED
Notes
36. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
37. Outputs are disabled (High Z) one clock cycle after a NOP.
38. In this example, if address A4 = A3, then data Q40 = D30, Q41 = D31, Q42 = D32, and Q43 = D43. Write data is forwarded immediately as read results. This note
applies to the whole diagram.
Document Number: 001-58906 Rev. *D
Page 28 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Ordering Information
The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
333 CY7C1321KV18-333BZC
250 CY7C1319KV18-250BZC
CY7C1321KV18-250BZC
51-85180 165-ball fine-pitch ball grid array (13 × 15 × 1.4 mm)
51-85180 165-ball fine-pitch ball grid array (13 × 15 × 1.4 mm)
Commercial
Commercial
CY7C1321KV18-250BZXC
165-ball fine-pitch ball grid array (13 × 15 × 1.4 mm) Pb-free
Ordering Code Definitions
CY
7
C 13XX K V18 - XXX BZ
X
C
Temperature Range:
C = Commercial = 0 C to +70 C
X = Pb-free; X Absent = Leaded
Package Type:
BZ = 165-ball FBGA
Speed Grade: XXX = 333 MHz / 250 MHz
V18 = 1.8 V VDD
Process Technology: K = 65 nm
Part Identifier: 13XX = 1319 or 1321
Technology Code: C = CMOS
Marketing Code: 7 = SRAMs
Company ID: CY = Cypress
Document Number: 001-58906 Rev. *D
Page 29 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Package Diagram
Figure 6. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter), 51-85180
51-85180 *C
Document Number: 001-58906 Rev. *D
Page 30 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
Description
DDR
EIA
double data rate
Unit of Measure
electronic industries alliance
fine-pitch ball grid array
high-speed transceiver logic
input/output
°C
MHz
µA
µs
degree Celsius
FBGA
HSTL
I/O
Mega Hertz
micro Amperes
micro seconds
milli Amperes
milli meter
milli seconds
milli Volts
JEDEC
JTAG
LMBU
LSB
joint electron devices engineering council
joint test action group
logical multiple bit upset
least significant bit
mA
mm
ms
mV
ns
LSBU
MSB
PLL
logical single bit upset
most significant bit
nano seconds
ohms
phase locked loop
%
percent
SEL
single event latch up
static random access memory
test access port
pF
V
pico Farad
Volts
SRAM
TAP
W
Watts
TCK
test clock
TDI
test data-in
TDO
TMS
test data-out
test mode select
Document Number: 001-58906 Rev. *D
Page 31 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Document History Page
Document Title: CY7C1317KV18/CY7C1917KV18/CY7C1319KV18/CY7C1321KV18, 18-Mbit DDR II SRAM Four-Word Burst
Architecture
Document Number: 001-58906
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
2860800
2897150
3081152
VKN
NJY
NJY
01/20/2010 New Data Sheet
*A
*B
03/22/2010 Removed Inactive parts
11/09/2010 Changed status from Preliminary to Final.
Updated Ordering Information.
Added Ordering Code Definitions.
Added Acronyms and Document Conventions.
*C
*D
3169007
3321978
NJY
NJY
02/10/2011 Added Note 33.
Updated Ordering Information.
07/20/2011 Updated Ordering Information.
Updated in new template.
Document Number: 001-58906 Rev. *D
Page 32 of 33
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CY7C1317KV18, CY7C1917KV18
CY7C1319KV18, CY7C1321KV18
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2010-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-58906 Rev. *D
Revised July 20, 2011
Page 33 of 33
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All products and company names mentioned in this document
may be the trademarks of their respective holders.
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