CY7C1324-100ACT [CYPRESS]
Cache SRAM, 128KX18, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100;
| 型号： | CY7C1324-100ACT |
| 厂家： | 
CYPRESS |
| 描述： | Cache SRAM, 128KX18, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总16页 (文件大小：281K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
324
CY7C1324
3.3V 128K x 18 Synchronous
Cache RAM
Features
Functional Description
• Supports117-MHzmicroprocessorcachesystemswith
zero wait states
• 128K by 18 common I/O
• Fast clock-to-output times
— 7.5 ns (117 MHz)
The CY7C1324 is a 3.3V, 128K by 18 synchronous cache
RAM designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access delay from clock
rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap-
tures the first address in a burst and increments the address
automatically for the rest of the burst access.
• Two-bit wrap-around counter supporting either inter-
leaved or linear burst sequence
• Separateprocessorandcontrolleraddressstrobespro-
vides direct interface with the processor and external
cache controller
• Synchronous self-timed write
• Asynchronous output enable
• I/Os capable of 2.5–3.3V operation
• JEDEC-standard pinout
• 100-pin TQFP packaging
• ZZ “sleep” mode
The CY7C1324 allows both interleaved or linear burst se-
quences, selected by the MODE input pin. A HIGH input on
MODE selects an interleaved burst sequence, while a LOW
selects a linear burst sequence. Burst accesses can be initiat-
ed with the Processor Address Strobe (ADSP) or the cache
Controller Address Strobe (ADSC) inputs. Address advance-
ment is controlled by the Address Advancement (ADV) input.
A synchronous self-timed write mechanism is provided to sim-
plify the write interface. A synchronous chip enable input and
an asynchronous output enable input provide easy control for
bank selection and output three-state control.
Logic Block Diagram
MODE
(A0,A1)
2
Q
Q
CLK
ADV
ADSC
0
BURST
COUNTER
CE
CLR
1
ADSP
Q
15
17
ADDRESS
REGISTER
CE
D
128K X 18
MEMORY
ARRAY
A[16:0]
GW
17
15
BWE
D
Q
Q
DQ[15:8]
BYTEWRITE
REGISTERS
BW
1
D
DQ[7:0]
BW
0
BYTEWRITE
REGISTERS
CE
1
2
CE
D
CE
ENABLE
REGISTER
CLK
Q
CE
3
18
18
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ[15:0]
DP[1:0]
Pin
Selection Guide
7C1324–117
7C1324–100
7C1324–80
7C1324–50
11.0
Maximum Access Time (ns)
7.5
350
1.0
8.0
325
1.0
8.5
300
1.0
Maximum Operating Current (mA)
Maximum Standby Current (mA)
250
1.0
Pentium is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05077 Rev. **
Revised September 4, 2001
CY7C1324
Pin Configuration
100-Lead TQFP
NC
NC
NC
1
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
10
2
NC
NC
V
3
V
4
DDQ
DDQ
V
5
V
SS
SS
NC
NC
6
NC
DP
7
0
DQ
DQ
V
8
DQ
DQ
V
8
9
7
6
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
SS
V
V
DDQ
DDQ
DQ
DQ
DQ
DQ
V
10
5
4
11
CY7C1324
NC
SS
BYTE0
V
NC
DD
NC
V
ZZ
DD
BYTE1
V
SS
DQ
DQ
DQ
V
12
13
3
2
DQ
V
DDQ
DDQ
SS
V
V
SS
DQ
DQ
DQ
NC
NC
V
14
15
1
0
DQ
DP
1
NC
V
SS
SS
V
V
DDQ
DDQ
NC
NC
NC
NC
NC
NC
Document #: 38-05077 Rev. **
Page 2 of 16
CY7C1324
input is asserted LOW, the requested data will be available at
the data outputs a maximum to tCDV after clock rise. ADSP is
ignored if CE1 is HIGH.
Functional Description (continued)
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, and (2) ADSP is asserted LOW. The addresses pre-
sented are loaded into the address register and the burst
counter/control logic and delivered to the RAM core. The write
inputs (GW, BWE, and BWS[1:0]) are ignored during this first
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
During byte writes, BWS0 controls DQ[7:0] and DP0 while
BWS1 controls DQ[15:8] and DP1. All I/Os are three-stated dur-
ing a byte write. Since these are common I/O devices, the
asynchronous OE input signal must be deasserted and the
I/Os must be three-stated prior to the presentation of data to
DQ[15:0] and DP[1:0]. As a safety precaution, the data lines are
three-stated once a write cycle is detected, regardless of the
state of OE.
Burst Sequences
This family of devices provide a 2-bit wrap around burst
counter inside the SRAM. The burst counter is fed by A[1:0]
,
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LOW on MODE will select a linear burst sequence. A HIGH on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause the device to default to a interleaved
burst sequence.
Table 1. Counter Implementation for the Intel
Pentium®/80486 Processor’s Sequence
First
Address
Second
Address
Third
Fourth
Address
Address
AX + 1,Ax
AX + 1,Ax
AX + 1,Ax
AX + 1,Ax
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWS[1:0]
indicate a write access. ADSC is ignored if ADSP is active LOW.
)
Table 2. Counter Implementation for a Linear Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
The addresses presented are loaded into the address register,
burst counter/control logic and delivered to the RAM core. The
information presented to DQ[15:0] and DP[1:0] will be written
into the specified address location. Byte writes are allowed,
with BWS0 controlling DQ[7:0] and DP0 while BWS1 controlling
DQ[15:8] and DP1. All I/Os are three-stated when a write is
detected, even a byte write. Since these are common I/O de-
vices, the asynchronous OE input signal must be deasserted
and the I/Os must be three-stated prior to the presentation of
data to DQ[15:0] and DP[1:0]. As a safety precaution, the data
lines are three-stated once a write cycle is detected, regard-
less of the state of OE.
AX + 1, Ax
AX + 1, Ax
AX + 1, Ax
AX + 1, Ax
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting a HIGH
input on ZZ places the SRAM in a power conservation “sleep”
mode. Two clock cycles are required to enter into or exit from
this “sleep” mode. While in this mode, data integrity is guaran-
teed. Accesses pending when entering the “sleep” mode are
not considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must re-
main inactive for the duration of tZZREC after the ZZ input re-
turns low
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all as-
serted active, and (2) ADSP or ADSC is asserted LOW (if the
access is initiated by ADSC, the write inputs must be deassert-
ed during this first cycle). The address presented to the ad-
dress inputs is latched into the Address Register, burst counter
/control logic and presented to the memory core. If the OE
Document #: 38-05077 Rev. **
Page 3 of 16
CY7C1324
Cycle Description Table[1, 2, 3]
ADD
Used
Cycle Description
CE1 CE3 CE2 ZZ ADSP ADSP ADV WE OE
CLK
DQ
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
SNOOZE MODE, Power-down
READ Cycle, Begin Burst
None
H
L
X
X
H
X
X
X
L
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
None
None
L
X
L
L
None
L
H
H
X
L
None
X
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
X
X
L
X
HIGH-Z
Q
External
External
External
External
External
Next
L-H
READ Cycle, Begin Burst
L
L
L
H
X
L
L-H High-Z
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H
L-H
D
Q
L
L
L
H
H
H
H
H
H
L
READ Cycle, Begin Burst
L
L
L
H
L
L-H High-Z
L-H
L-H High-Z
L-H
L-H High-Z
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
Next
L
L-H
L-H
L-H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H High-Z
L-H
L-H High-Z
Q
H
X
X
L-H
L-H
D
D
WRITE Cycle, Suspend Burst
L
Notes:
1. X=Don’t Care”, 1=Logic HIGH, 0=Logic LOW.
2. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWS[1:0]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE
is a “Don't Care” for the remainder of the write cycle.
3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ = High-Z when OE is inactive, and DQ=data when OE is active.
Document #: 38-05077 Rev. **
Page 4 of 16
CY7C1324
Pin Descriptions
TQFP Pin
Number
Name
I/O
Description
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted
85
ADSC
Input-
Synchronous LOW, A[16:0] is captured in the address registers. A[1:0] are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
84
ADSP
Input-
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted
Synchronous LOW, A[16:0] is captured in the address registers. A[1:0] are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP
is ignored when CE1 is deasserted HIGH.
36, 37
A[1:0]
Input-
A1, A0 Address Inputs, These inputs feed the on-chip burst counter as the LSBs as
Synchronous well as being used to access a particular memory location in the memory array.
49–44,
80–82, 99,
100,
A[16:2]
Input- Address Inputs used in conjunction with A[1:0] to select one of the 128K address
Synchronous locations. Sampled at the rising edge of the CLK, if CE1, CE2, and CE3 are sampled
active, and ADSP or ADSC is active LOW.
32–35
94, 93
BWS[1:0]
ADV
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes.
Synchronous Sampled on the rising edge. BWS0 controls DQ[7:0] and DP0, BWS1 controls DQ[15:8]
and DP1. See Write Cycle Descriptions table for further details.
83
Input-
Advance Input used to advance the on-chip address counter. When LOW the internal
Synchronous burst counter is advanced in a burst sequence. The burst sequence is selected using
the MODE input.
87
88
BWE
GW
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
Synchronous must be asserted LOW to conduct a byte write.
Input-
Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is used
Synchronous to conduct a global write, independent of the state of BWE and BWS[1:0]. Global writes
override byte writes.
89
98
CLK
CE1
Input-Clock
Input-
Clock Input. Used to capture all synchronous inputs to the device.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in con-
Synchronous junction with CE2 and CE3, to select/deselect the device. CE1 gates ADSP.
Input- Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in con-
Synchronous junction with CE1 and CE3 to select/deselect the device.
Input- Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in con-
Synchronous junction with CE1 and CE2 to select/deselect the device.
Input- Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
97
92
86
CE2
CE3
OE
Asynchronous When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins.
64
31
ZZ
Input-
Snooze Input. Active HIGH asynchronous. When HIGH, the deviceenters a low-power
Asynchronous standby mode in which all other inputs are ignored, but the data in the memory array
is maintained. Leaving ZZ floating or NC will default the device into an active state.
MODE
-
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
burstorder. PulledLOWselectsthelinearburstorder. WhenleftfloatingorNC, defaults
to interleaved burst order.
23, 22, 19, DQ[15:0]
18, 13, 12,
9, 8, 73,
72, 69, 68,
63, 62, 59,
58
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
Synchronous triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by A[17:0] during the previous clock rise of the read cycle.
The direction of the pins is controlled by OE in conjunction with the internal control
logic. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ[15:0]
and DP[1:0] are placed in a three-state condition. The outputs are automatically
three-stated when a WRITE cycle is detected.
74, 24
DP[1:0]
I/O-
Bidirectional Data Parity lines. These behave identical to DQ[15:0] described above.
Synchronous These signals can be used as parity bits for bytes 0 and 1 respectively.
15, 41, 65, VDD
91
Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
Document #: 38-05077 Rev. **
Page 5 of 16
CY7C1324
Pin Descriptions
TQFP Pin
Number
Name
I/O
Description
5, 10, 17, VSS
21, 26, 40,
Ground
Ground for the device. Should be connected to ground of the system.
55, 60, 67,
71, 76, 90
4, 11, 20,
27, 54, 61,
70, 77
VDDQ
I/O Power
Supply
Power supply for the I/O circuitry. Should be connected to a 2.5 or 3.3V power supply.
No connects.
1–3, 6, 7, NC
14, 16, 25,
28–30,
-
50–53, 56,
57, 66, 75,
78, 79,
95–96
38, 39, 42, DNU
43
-
Do not use pins. Should be left unconnected or tied LOW.
Write Cycle Descriptions[1, 2, 3, 4]
Function
GW
1
BWE
BWS1
BWS0
Read
1
0
0
0
0
X
X
1
1
0
0
X
X
1
0
1
0
X
Read
1
Write Byte 0 - DQ[7:0] and DP0
Write Byte 1 - DQ[15:8] and DP1
Write All Bytes
1
1
1
Write All Bytes
0
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Test Conditions
Min
Max
Unit
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ > VDD − 0.2V
ZZ > VDD − 0.2V
ZZ < 0.2V
10
mA
ns
tZZS
2tCYC
tZZREC
2tCYC
ns
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature ...................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied...............................................–55°C to +125°C
Ambient
Range Temperature[6]
VDD
VDDQ
Supply Voltage on VDD Relative to GND...............–0.5V to +4.6V
DC Voltage Applied to Outputs
Com’l
0°C to +70°C
3.135V to 3.6V 2.375V to VDD
in High Z State[5]...............................................–0.5V to VDD + 0.5V
DC Input Voltage[5]...........................................–0.5V to VDD + 0.5V
Notes:
4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
5. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
6. TA is the case temperature.
Document #: 38-05077 Rev. **
Page 6 of 16
CY7C1324
Electrical Characteristics Over the Operating Range
7C1324
Parameter
Description
Test Conditions
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
VDDQ = 2.5V, VDD = Min., IOH = –2.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
VDDQ = 2.5V, VDD = Min., IOL = 2.0 mA
Min.
Max.
Unit
V
VOH
Output HIGH Voltage
2.4
1.7
V
VOL
Output LOW Voltage
0.4
0.7
V
V
VIH
Input HIGH Voltage
Input LOW Voltage[5]
1.7
VDD
0.3V
+
V
VIL
IX
–0.3
−1
0.8
1
V
Input Load Current
GND ≤ VI ≤ VDDQ
µA
(except ZZ and MODE)
Input Current of MODE
Input = VSS
–30
–5
µA
µA
Input = VDDQ
5
Input Current of ZZ
Input = VSS
µA
Input = VDDQ
30
5
µA
IOZ
IOS
IDD
Output Leakage Current
Output Short Circuit Current[7] VDD=Max., VOUT=GND
GND ≤ VI ≤ VDD, Output Disabled
–5
µA
–300
325
300
275
225
35
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VDD Operating Supply Current
VDD=Max., Iout=0mA,
f=fMAX =1/tCYC
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
11-ns cycle, 90 MHz
20-ns cycle, 50 MHz
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
11-ns cycle, 90 MHz
20-ns cycle, 50 MHz
All speeds
.
ISB1
Automatic CE Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL,
f=fMAX, inputs switching
30
25
20
ISB2
Automatic CE Power-Down
Max. VDD, Device Deselected,
10
Current — CMOS Inputs
VIN ≥ VDD –0.3V or VIN ≤ 0.3V, f=0,
inputs static
ISB3
Automatic CE Power-Down
Current—CMOS Inputs
Max. VDD, Device Deselected,
VIN ≥ VDDQ- 0.3V or VIN ≤ 0.3V,
f=fMAX, inputs switching
8.5-ns cycle, 117 MHz
10-ns cycle, 100 MHz
11-ns cycle, 90 MHz
20-ns cycle, 50 MHz
All speeds
10
10
10
10
18
mA
mA
mA
mA
mA
ISB4
Automatic CE
Max. VDD, Device Deselected,
Power-Down Current — TTL In- VIN ≥ VIH or VIN ≤ VIL,
puts static, F=0 f=0, inputs static
Capacitance[8]
Parameter
CIN
Description
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 5.0V
Max.
Unit
Input Capacitance
I/O Capacitance
4
4
pF
pF
CI/O
Notes:
7. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05077 Rev. **
Page 7 of 16
CY7C1324
AC Test Loads and Waveforms[10]
R1
2.5V
OUTPUT
OUTPUT
ALL INPUT PULSES
Z =50Ω
0
2.5V
GND
90%
10%
R =50Ω
L
90%
10%
R2
5 pF
V =1.5V
L
INCLUDING
JIG AND
SCOPE
≤ 2.5 ns
≤ 2.5 ns
(b)[9]
1324–3
(a)
1324–4
[10]
Switching Characteristics Over the Operating Range
-117
-100
-90
-50
Parameter
tCYC
Description
Clock Cycle Time
Min. Max. Min. Max. Min. Max. Min. Max. Unit
8.5
3.0
3.0
2.0
0.5
10
4.0
4.0
2.0
0.5
11
20
4.5
4.5
2.0
0.5
ns
tCH
Clock HIGH
4.5
4.5
2.0
0.5
ns
tCL
Clock LOW
ns
tAS
Address Set-Up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-Up Before CLK Rise
ADSP, ADSC Hold After CLK Rise
BWS[1:0], GW,BWE Set-Up Before CLK Rise
BWS[1:0], GW,BWE Hold After CLK Rise
ADV Set-Up Before CLK Rise
ADV Hold After CLK Rise
ns
tAH
ns
tCDV
tDOH
tADS
tADH
tWES
tWEH
tADVS
tADVH
tDS
7.5
8.0
8.5
11.0 ns
2.0
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Input Set-Up Before CLK Rise
Data Input Hold After CLK Rise
Chip Enable Set-Up
tDH
tCES
tCEH
tCHZ
tCLZ
tEOHZ
tEOLZ
Chip Enable Hold After CLK Rise
Clock to High-Z[11,12]
Clock to Low-Z[11,12]
OE HIGH to Output High-Z[11,13]
OE LOW to Output Low-Z[11,13]
OE LOW to Output Valid
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
ns
ns
ns
ns
ns
0
0
0
0
0
0
0
0
tEOV
Notes:
9. R1=1667Ω and R2=1538Ω for IOH/IOL= –4/8mA, R1=521Ω and R2=481Ω for IOH/IOL= –2/2mA.
10. Unless otherwise noted, test conditions assume signal transition time of 2.5ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC test loads.
11.
tCHZ, tCLZ, tEOHZ, and tEOLZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
12. At any given voltage and temperature, tCHZ (max) is less than tCLZ (min).
13. This parameter is sampled and not 100% tested.
Document #: 38-05077 Rev. **
Page 8 of 16
CY7C1324
Timing Diagrams
Write Cycle Timing[14, 15]
Single Write
Burst Write
Pipelined Write
t
Unselected
CH
t
CYC
CLK
t
ADH
t
ADS
t
ADSP ignored with CE inactive
CL
1
ADSP
ADSC
ADV
t
ADH
t
ADSC initiated write
ADS
t
t
ADVH
ADVS
t
ADV Must Be Inactive for ADSP Write
WD1
WD2
AS
WD3
ADD
GW
WE
t
AH
t
WH
t
WH
t
WS
t
WS
t
t
CES
CEH
CE masks ADSP
1
CE
1
t
t
CEH
CES
Unselected with CE
2
CE
2
CE
3
t
CES
t
CEH
OE
t
DH
t
DS
High-Z
High-Z
Data-
In
3a
2a
= UNDEFINED
2d
1a
2b
2c
= DON’T CARE
Note:
14. WE is the combination of BWE, BW[3:0] and GW to define a write cycle (see Write Cycle Descriptions table).
15. WDx stands for Write Data to Address X.
Document #: 38-05077 Rev. **
Page 9 of 16
CY7C1324
Timing Diagrams (continued)
Read Cycle Timing[14, 16]
Burst Read
Single Read
tCYC
Unselected
tCH
Pipelined Read
CLK
tADH
tADS
ADSP
tCL
ADSP ignored with CE1 inactive
tADS
ADSC initiated read
ADSC
ADV
tADVS
tADH
Suspend Burst
tADVH
tAS
ADD
GW
RD1
RD3
RD2
tAH
tWS
tWS
tWH
WE
tCES
tCEH
tWH
CE1 masks ADSP
CE1
Unselected with CE2
CE2
tCES
tCEH
CE3
OE
tCEH
tEOV
tCES
tOEHZ
tDOH
tCDV
3a
Data Out
2d
2a
2b
2c
1a
tCLZ
tCHZ
= DON’T CARE
= UNDEFINED
Note:
16. RDx stands for Read Data from Address X.
Document #: 38-05077 Rev. **
Page 10 of 16
CY7C1324
Timing Diagrams (continued)
READ/WRITE Timing
tCYC
tCL
tCH
CLK
tAH
tAS
A
D
B
C
ADD
tADH
tADS
ADSP
tADH
tADS
ADSC
ADV
tADVH
tADVS
tCEH
tCES
CE1
CE
tCEH
tCES
tWES
tWEH
WE
OE
ADSP ignored
with CE1 HIGH
tEOHZ
tCLZ
Data
Q
(B+3)
D
(C+1)
D
(C+2)
D
(C+3)
Q
(B+2)
Q
(B+1)
Q(B)
Q(B)
D(C)
Q(D)
Q(A)
In/Out
tCDV
tDOH
tCHZ
Device originally
deselected
WE is the combination of BWE, BWS[1:0] and GW to define a write cycle (see Write Cycle Definitions table).
CE is the combination of CE2 and CE3. All chip selects need to be active in order to select
the device. RAx stands for Read Address X, WA stands for Write Address X, Dx stands for Data-in X,
Qx stands for Data-out X.
= UNDEFINED
= DON’T CARE
Document #: 38-05077 Rev. **
Page 11 of 16
CY7C1324
Timing Diagrams (continued)
Pipeline Timing
tCYC
tCL
tCH
CLK
tAS
C
E
F
G
H
B
D
A
ADD
tADH
tADS
ADSP
ADSC
ADV
tCEH
tCES
CE1
CE
tWES
tWEH
WE
OE
ADSP ignored
with CE1 HIGH
tCLZ
Data
D (E)
D (F)
D (H)
Q(A)
D (G)
Q(B)
Q(C)
Q(D)
tCDV
tDOH
tCHZ
Device originally
deselected
CE is the combination of CE2 and CE3. All chip selects need to be active in order to select
the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,
Qx stands for Data-out X.
= UNDEFINED
= DON’T CARE
Document #: 38-05077 Rev. **
Page 12 of 16
CY7C1324
Timing Diagrams (continued)
OE Switching Waveforms
OE
tEOV
tEOHZ
three-state
tEOLZ
I/Os
Document #: 38-05077 Rev. **
Page 13 of 16
CY7C1324
Timing Diagrams (continued)
ZZ Mode Timing [17 ,18
CLK
ADSP
HIGH
ADSC
CE1
LOW
HIGH
CE2
CE3
ZZ
tZZS
ICC
ICC(active)
tZZREC
ICCZZ
I/Os
Three-state
Notes:
17. Device must be deselected when entering ZZ mode. See Cycle Description table for all possible signal conditions to deselect the device.
18. I/Os are in three-state when exiting ZZ sleep mode.
Document #: 38-05077 Rev. **
Page 14 of 16
CY7C1324
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
117
100
80
Ordering Code
Package Type
100-Lead Thin Quad Flat Pack
100-Lead Thin Quad Flat Pack
100-Lead Thin Quad Flat Pack
100-Lead Thin Quad Flat Pack
CY7C1324–117AC
CY7C1324–100AC
CY7C1324–80AC
CY7C1324–50AC
A101
A101
A101
A101
Commercial
Commercial
Commercial
Commercial
50
Package Diagram
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
Document #: 38-05077 Rev. **
Page 15 of 16
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1324
Document Title: CY7C1324 3.3V 128K x 18 Synchronous Cache RAM
Document Number: 38-05077
Issue
ECN NO. Date
Orig. of
Change
REV.
Description of Change
**
107337
09/15/01
SZV
Change from Spec number: 38-00651 to 38-05077
Document #: 38-05077 Rev. **
Page 16 of 16
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