CY7C1324H-133AXC [CYPRESS]
2-Mbit (128K x 18) Flow-Through Sync SRAM; 2兆位（ 128K ×18 ）流通型同步SRAM
| 型号： | CY7C1324H-133AXC |
| 厂家： | 
CYPRESS |
| 描述： | 2-Mbit (128K x 18) Flow-Through Sync SRAM |
| 文件： | 总15页 (文件大小：676K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1324H
2-Mbit (128K x 18) Flow-Through Sync SRAM
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst
Features
• 128K x 18 common I/O
• 3.3V core power supply
• 3.3V/2.5V I/O supply
Control inputs (ADSC, ADSP,
ADV), Write Enables
and
), and Global Write (
(OE)
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
• Provide high-performance 2-1-1-1 access rate
(BW[A:B]
BWE
GW
,
). Asynchronous
and
. The
and the ZZ pin
nputs include the Output Enable
i
CY7C1324H allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP) or the cache Controller
Address Strobe (ADSC) inputs. Address advancement is
controlled by the Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
• User-selectable burst counter supporting Intel®
Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in JEDEC-standard lead-free 100-pin TQFP
package
• “ZZ” Sleep Mode option
Functional Description[1]
The CY7C1324H operates from a +3.3V core power supply
while all outputs may operate with either a +3.3V or +2.5V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
The CY7C1324H is a 128K x 18 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
Logic Block Diagram
ADDRESS
REGISTER
A0,A1,A
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ
B,DQPB
DQ
B,DQPB
WRITE DRIVER
WRITE REGISTER
BW
B
A
MEMORY
ARRAY
OUTPUT
BUFFERS
DQs
DQP
DQP
SENSE
AMPS
A
B
DQ
A,DQPA
DQA,DQPA
WRITE REGISTER
WRITE DRIVER
BW
BWE
GW
INPUT
REGISTERS
ENABLE
REGISTER
CE
CE
CE
1
2
3
OE
SLEEP
CONTROL
ZZ
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-00208 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 26, 2006
[+] Feedback
CY7C1324H
Selection Guide
133 MHz
6.5
Unit
ns
Maximum Access Time
Maximum Operating Current
Maximum Standby Current
225
mA
mA
40
Pin Configurations
100-pin TQFP Pinout
NC
NC
1
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
NC
NC
NC
3
VDDQ
VSS
NC
4
VDDQ
VSS
NC
5
6
NC
7
DQPB
DQA
DQA
VSS
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
DQA
DQA
VSS
VDD
NC
CY7C1324H
NC
BYTE A
VDD
ZZ
BYTE B
VSS
DQB
DQB
VDDQ
VSS
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
DQB
DQB
DQPB
NC
NC
VSS
VSS
VDDQ
NC
VDDQ
NC
NC
NC
NC
NC
Document #: 001-00208 Rev. *B
Page 2 of 15
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CY7C1324H
Pin Definitions
Name
I/O
Description
Address Inputs used to select one of the 128K address locations. Sampled at the rising
A0, A1, A
Input-
Synchronous edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active.
A[1:0] feed the 2-bit counter.
BWA,BWB
GW
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the
Synchronous SRAM. Sampled on the rising edge of CLK.
Input-
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
Synchronous global Write is conducted (ALL bytes are written, regardless of the values on BW[A:B] and BWE).
BWE
CLK
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must
Synchronous be asserted LOW to conduct a Byte Write.
Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
CE1
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
CE
Synchronous with CE and CE to select/deselect the device. ADSP is ignored
if CE is HIGH
.
1 is sampled
2
3
1
only when a new external address is loaded.
CE2
CE3
OE
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
Synchronous with CE1 and CE3 to select/deselect the device. CE
2 is sampled only when a new external
address is loaded.
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
Synchronous with CE1 and CE2 to select/deselect the device. CE3 is sampled only when a new external
address is loaded.
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
Asynchronous When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a Read cycle when emerging
from a deselected state.
ADV
Input-
Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically
Synchronous increments the address in a burst cycle.
ADSP
Input-
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
Synchronous asserted LOW, addresses presented to the device are captured in the address registers.
A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted,
only ADSP is recognized. ASDP is ignored when
CE1 is deasserted HIGH
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When
Synchronous asserted LOW, addresses presented to the device are captured in the address registers.
[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted,
ADSC
ZZ
Input-
A
only ADSP is recognized.
Input-
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical
Asynchronous “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or
left floating. ZZ pin has an internal pull-down.
DQs
DQPA, DQPB
I/O-
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered
Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the Read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQP[A:B] are placed in a tri-state condition.
VDD
Power
Supply
Power supply inputs to the core of the device.
VSS
Ground
Ground for the device.
VDDQ
I/O Power
Supply
Power supply for the I/O circuitry.
MODE
NC
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or
left floating selects interleaved burst sequence. This is a strap pin and should remain static
during device operation. Mode Pin has an internal pull-up.
No Connects. Not Internally connected to the die. 4M, 9M, 18M, 72M, 144M, 288M, 576M, and
1G are address expansion pins and are not internally connected to the die.
Document #: 001-00208 Rev. *B
Page 3 of 15
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CY7C1324H
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BW[A:B])
indicate a write access. ADSC is ignored if ADSP is active
LOW.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (tCDV) is 6.5 ns (133-MHz device).
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQ[A:D] will be
written into the specified address location. Byte Writes are
allowed. During Byte Writes, BWA controls DQA and BWB
controls DQB. All I/Os are tri-stated when a Write is detected,
even a Byte Write. Since this is a common I/O device, the
asynchronous OE input signal must be deasserted and the
I/Os must be tri-stated prior to the presentation of data to DQs.
As a safety precaution, the data lines are tri-stated once a
Write cycle is detected, regardless of the state of OE.
The CY7C1324H supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Burst Sequences
The CY7C1324H provides an on-chip two-bit wraparound
burst counter inside the SRAM. The burst counter is fed by
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:B]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
A[1:0], and can follow either a linear or interleaved burst order.
The burst order is determined by the state of the MODE input.
A LOW on MODE will select a linear burst sequence. A HIGH
on MODE will select an interleaved burst order. Leaving
MODE unconnected will cause the device to default to an
interleaved burst sequence.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Sleep Mode
Single Read Accesses
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
available at the data outputs a maximum to tCDV after clock
rise. ADSP is ignored if CE1 is HIGH.
Interleaved Burst Address Table
(MODE = Floating or VDD
)
Single Write Accesses Initiated by ADSP
First
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted
active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BWE, and BW[A:B]) are ignored during this first
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
Write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte Writes are allowed.
During Byte Writes, BWA controls DQA and BWB controls
DQB. All I/Os are tri-stated during a Byte Write. Since this is a
common I/O device, the asynchronous OE input signal must
be deasserted and the I/Os must be tri-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tri-stated once a write cycle is detected, regardless
of the state of OE.
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1,A0
Second
Address
A1,A0
Third
Address
A1,A0
Fourth
Address
A1,A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
Document #: 001-00208 Rev. *B
Page 4 of 15
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CY7C1324H
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
Test Conditions
ZZ > VDD – 0.2V
Min.
Max.
40
Unit
mA
ns
tZZS
ZZ > VDD – 0.2V
2tCYC
tZZREC
tZZI
ZZ recovery time
ZZ < 0.2V
2tCYC
0
ns
ZZ Active to sleep current
ZZ Inactive to exit sleep current
This parameter is sampled
This parameter is sampled
2tCYC
ns
tRZZI
ns
Truth Table[2, 3, 4, 5]
ADDRESS
Used
Cycle Description
CE1 CE2 CE3 ZZ ADSP ADSC ADV WE OE CLK
DQ
Deselected Cycle,
Power-down
None
None
None
None
None
H
L
L
L
X
X
X
X
H
X
X
L
L
L
L
L
X
L
X
X
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L-H
L-H
L-H
L-H
L-H
Tri-State
Deselected Cycle,
Power-down
L
L
Tri-State
Tri-State
Tri-State
Tri-State
Deselected Cycle,
Power-down
X
L
L
Deselected Cycle,
Power-down
H
H
Deselected Cycle,
Power-down
X
Sleep Mode, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
None
External
External
External
External
External
Next
X
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
X
X
X
L
X
X
X
X
X
X
L
X
X
X
L
X
L
X
Tri-State
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
Q
L
L
L
H
X
L
Tri-State
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
D
L
L
L
H
H
H
H
H
H
L
Q
L
L
L
H
L
Tri-State
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Tri-State
Next
L
Q
Next
L
H
X
X
L
Tri-State
Next
L
D
Next
L
L
D
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
Q
H
L
Tri-State
Q
H
X
X
Tri-State
D
D
Write Cycle, Suspend Burst
L
Notes:
2. X = “Don't Care.” H = Logic HIGH, L =Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BW , BW ) and BWE = L or GW= L. WRITE = H when all Byte Write Enable signals (BW , BW ),
A
B
A
B
BWE, GW = H.The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks
[A: B]
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the Write cycle
5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a read cycle all data bits are Tri-State when OE
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW)
Document #: 001-00208 Rev. *B
Page 5 of 15
[+] Feedback
CY7C1324H
Truth Table for Read/Write[2, 3]
Function
GW
H
BWE
BWB
X
BWA
X
Read
H
L
L
L
L
X
Read
H
H
H
Write Byte (A, DQPA)
Write Byte (B, DQPB)
Write All Bytes
H
H
L
H
L
H
H
L
L
Write All Bytes
L
X
X
Document #: 001-00208 Rev. *B
Page 6 of 15
[+] Feedback
CY7C1324H
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Supply Voltage on VDDQ Relative to GND ......–0.5V to +VDD
Ambient
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VDD
VDDQ
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
3.3V
−5%/+10%
2.5V –5%
to VDD
Electrical Characteristics Over the Operating Range [6, 7]
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
Max.
3.6
Unit
V
3.135
3.135
2.375
2.4
VDDQ
for 3.3V I/O
for 2.5V I/O
VDD
V
2.625
V
V
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[6]
for 3.3V I/O, IOH = –4.0 mA
for 2.5V I/O, IOH = –1.0 mA
for 3.3V I/O, IOL = 8.0 mA
for 2.5V I/O, IOL = 1.0 mA
for 3.3V I/O
2.0
0.4
V
V
0.4
VDD + 0.3V
VDD + 0.3V
0.8
2.0
1.7
for 2.5V I/O
for 3.3V I/O
–0.3
–0.3
−5
V
for 2.5V I/O
0.7
Input Leakage Current GND ≤ VI ≤ VDDQ
except ZZ and MODE
5
µA
Input Current of MODE Input = VSS
Input = VDD
–30
–5
µA
µA
µA
µA
µA
mA
5
Input Current of ZZ
Input = VSS
Input = VDD
30
5
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
VDD Operating Supply VDD = Max., IOUT = 0 mA, 7.5-ns cycle, 133 MHz
–5
225
Current
f = fMAX= 1/tCYC
ISB1
ISB2
ISB3
Automatic CE
Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected, 7.5-ns cycle, 133 MHz
VIN ≥ VIH or VIN ≤ VIL, f = fMAX,
90
40
75
mA
mA
mA
inputs switching
Automatic CE
Power-Down
Current—CMOS Inputs f = 0, inputs static
Max. VDD, Device Deselected, 7.5-ns cycle, 133 MHz
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
Automatic CE
Power-Down
Max. VDD, Device Deselected, 7.5-ns cycle, 133 MHz
VIN ≥ VDDQ – 0.3V or VIN
≤
Current—CMOS Inputs 0.3V,
f = fMAX, inputs switching
ISB4
Automatic CE
Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected, 7.5-ns cycle, 133 MHz
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
45
mA
Notes:
6. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > –2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
7. T
: Assumes a linear ramp from 0v to V (min.) within 200 ms. During this time V < V and V
< V
.
Power-up
DD
IH
DD
DDQ
DD
Document #: 001-00208 Rev. *B
Page 7 of 15
[+] Feedback
CY7C1324H
Capacitance[8]
100 TQFP
Parameter
Description
Test Conditions
Max.
Unit
pF
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
5
5
5
VDD = 3.3V.
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
pF
VDDQ = 2.5V
pF
Thermal Resistance[8]
100 TQFP
Package
Parameter
ΘJA
Description
Test Conditions
Unit
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and proce-
dures for measuring thermal impedance, per
EIA/JESD51
30.32
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
6.85
°C/W
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
VDD
OUTPUT
90%
10%
Z = 50Ω
0
10%
R = 50Ω
L
GND
5 pF
R = 351Ω
≤ 1 ns
≤ 1 ns
INCLUDING
JIG AND
SCOPE
V = 1.5V
L
(a)
(b)
(c)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50Ω
0
10%
L
GND
5 pF
R =1538Ω
≤ 1 ns
≤ 1 ns
INCLUDING
V = 1.25V
T
JIG AND
SCOPE
(a)
(b)
(c)
Notes:
8. Tested initially and after any design or process change that may affect these parameters.
Document #: 001-00208 Rev. *B
Page 8 of 15
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CY7C1324H
Switching Characteristics Over the Operating Range[9, 10]
-133
Parameter
tPOWER
Clock
tCYC
Description
VDD(Typical) to the First Access[11]
Min.
Max.
Unit
1
ms
Clock Cycle Time
Clock HIGH
7.5
2.5
2.5
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCDV
Data Output Valid after CLK Rise
Data Output Hold after CLK Rise
Clock to Low-Z[12, 13, 14]
6.5
ns
ns
ns
ns
ns
ns
ns
tDOH
2.0
0
tCLZ
tCHZ
Clock to High-Z[12, 13, 14]
3.5
3.5
OE LOW to Output Valid
tOEV
OE LOW to Output Low-Z[12, 13, 14]
OE HIGH to Output High-Z[12, 13, 14]
tOELZ
0
tOEHZ
3.5
Set-up Times
tAS
Address Set-up before CLK Rise
ADSP, ADSC Set-up before CLK Rise
ADV Set-up before CLK Rise
1.5
ns
tADS
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
tADVS
tWES
tDS
GW, BWE, BW[A:B] Set-up before CLK Rise
Data Input Set-up before CLK Rise
Chip Enable Set-up
tCES
Hold Times
tAH
Address Hold after CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tADH
ADSP, ADSC Hold after CLK Rise
GW, BWE, BW[A:B] Hold after CLK Rise
ADV Hold after CLK Rise
tWEH
tADVH
tDH
Data Input Hold after CLK Rise
Chip Enable Hold after CLK Rise
tCEH
Notes:
9. Timing reference level is 1.5V when V
= 3.3V and 1.25V when V
= 2.5V
DDQ
DDQ
10. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
11. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V (minimum) initially before a Read or Write operation
POWER
DD
can be initiated.
12. t
, t
, t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
13. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
14. This parameter is sampled and not 100% tested.
Document #: 001-00208 Rev. *B
Page 9 of 15
[+] Feedback
CY7C1324H
Timing Diagrams
Read Cycle Timing[15]
t
CYC
t
CLK
t
CL
CH
t
t
ADH
ADS
ADSP
t
t
ADH
ADS
ADSC
ADDRESS
t
t
AH
AS
A1
A2
t
t
WES
WEH
GW, BWE,BW[A:B]
Deselect Cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst.
t
t
t
CDV
OEV
OELZ
t
t
OEHZ
CHZ
t
DOH
t
CLZ
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Data Out (Q)
High-Z
t
CDV
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note:
15. On this diagram, when CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document #: 001-00208 Rev. *B
Page 10 of 15
[+] Feedback
CY7C1324H
Timing Diagrams (continued)
Write Cycle Timing[15, 16]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst.
t
t
t
ADH
ADS
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP initiates burst.
t
t
WEH
WES
BWE,
BW[A:B]
t
t
WEH
WES
GW
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
ADV suspends burst.
OE
t
t
DH
DS
Data in (D)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
t
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON’T CARE
UNDEFINED
Note:
16.
Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
LOW.
[A:B]
Document #: 001-00208 Rev. *B
Page 11 of 15
[+] Feedback
CY7C1324H
Timing Diagrams (continued)
Read/Write Timing[15, 17, 18]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
BWE, BW[A:B]
CE
t
t
WEH
WES
t
t
CEH
CES
ADV
OE
t
t
DH
DS
t
OELZ
t
High-Z
D(A3)
D(A5)
D(A6)
Data In (D)
t
OEHZ
CDV
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
Back-to-Back READs
Single WRITE
BURST READ
WRITEs
DON’T CARE
UNDEFINED
Notes:
17. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.
18. GW is HIGH.
Document #: 001-00208 Rev. *B
Page 12 of 15
[+] Feedback
CY7C1324H
Timing Diagrams (continued)
ZZ Mode Timing[19, 20]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
19. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
20. DQs are in High-Z when exiting ZZ sleep mode.
Document #: 001-00208 Rev. *B
Page 13 of 15
[+] Feedback
CY7C1324H
Ordering Information
“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered”.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
133 CY7C1324H-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1324H-133AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Commercial
Industrial
Package Diagram
100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00 0.20
14.00 0.10
1.40 0.05
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
1. JEDEC STD REF MS-026
0.25
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
1.00 REF.
0.20 MIN.
51-85050-*B
DETAIL
A
Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corporation. All product and company names
mentioned in this document may be the trademarks of their respective holders.
Document #: 001-00208 Rev. *B
Page 14 of 15
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback
CY7C1324H
Document History Page
Document Title: CY7C1324H 2-Mbit (128K x 18) Flow-Through Sync SRAM
Document Number: 001-00208
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
347377
428408
See ECN
See ECN
PCI
New Data Sheet
Converted from Preliminary to Final.
*A
NXR
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Removed 100 MHz Speed-bin
Changed Three-State to Tri-State.
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table.
Modified test condition from VIH < VDD to VIH < VDD
Replaced Package Name column with Package Diagram in the Ordering
Information table.
Updated the Ordering Information Table.
Replaced Package Diagram of 51-85050 from *A to *B
*B
459347
See ECN
NXR
Included 2.5V I/O option
Updated the Ordering Information table.
Document #: 001-00208 Rev. *B
Page 15 of 15
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相关型号：
CY7C1325-100ACT
Cache SRAM, 256KX18, 8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
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