CY7C1327G-225AXI [CYPRESS]
4-Mbit (256K x 18) Pipelined Sync SRAM; 4兆位（ 256K ×18 ）流水线同步SRAM
| 型号： | CY7C1327G-225AXI |
| 厂家： | 
CYPRESS |
| 描述： | 4-Mbit (256K x 18) Pipelined Sync SRAM |
| 文件： | 总18页 (文件大小：340K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1327G
PRELIMINARY
4-Mbit (256K x 18) Pipelined Sync SRAM
Features
Functional Description[1]
• Registered inputs and outputs for pipelined operation
• 256K ×18 common I/O architecture
• 3.3V core power supply
The CY7C1327G SRAM integrates 262,144 x 18 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
• 3.3V / 2.5V I/O operation
• Fast clock-to-output times
(
), depth-expansion Chip Enables (CE and
), Burst
CE3
CE1
2
— 2.6 ns (for 250-MHz device)
Control inputs (
(
inputs include the Output Enable ( ) and the ZZ pin.
,
,
and
ADSC ADSP
), Write Enables
). Asynchronous
GW
ADV
), and Global Write (
BWE
, and
BW[A:B]
— 2.6 ns (for 225-MHz device)
OE
— 2.8 ns (for 200-MHz device)
Addresses and chip enables are registered at rising edge of
— 3.5 ns (for 166-MHz device)
clock when either Address Strobe Processor (
) or
ADSP
Address Strobe Controller (
burst addresses can be internally generated as controlled by
the Advance pin ( ).
) are active. Subsequent
ADSC
— 4.0 ns (for 133-MHz device)
— 4.5 ns (for 100-MHz device)
ADV
• Provide high-performance 3-1-1-1 access rate
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two bytes wide as
• User-selectable burst counter supporting Intel®
Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
controlled by the byte write control inputs.
when active
GW
causes all bytes to be written.
LOW
• Asynchronous output enable
The CY7C1327G operates from a +3.3V core power supply
while all outputs also operate with a +3.3V or a +2.5V supply.
All inputs and outputs are JEDEC-standard JESD8-5-
compatible.
• Lead-Free 100-pin TQFP and 119 Ball BGA packages.
• “ZZ” Sleep Mode Option
Logic Block Diagram
ADDRESS
A0, A1, A
REGISTER
A[1:0]
2
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQB,DQP
B
DQB,DQP
WRITE REGISTER
B
WRITE DRIVER
OUTPUT
BUFFERS
BW
B
A
DQs
DQP
DQP
OUTPUT
REGISTERS
SENSE
AMPS
MEMORY
ARRAY
A
B
DQA,DQP
A
E
DQA,DQP
WRITE REGISTER
A
WRITE DRIVER
BW
BWE
GW
INPUT
REGISTERS
ENABLE
REGISTER
CE1
CE2
PIPELINED
ENABLE
CE3
OE
ZZ
SLEEP
CONTROL
1
Note:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com
Cypress Semiconductor Corporation
Document #: 38-05519 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised October 21, 2004
PRELIMINARY
CY7C1327G
Selection Guide
250 MHz
2.6
225 MHz
2.6
200 MHz
2.8
166 MHz
3.5
133 MHz
4.0
100 MHz
Unit
ns
Maximum Access Time
4.5
205
40
Maximum Operating Current
325
290
265
240
225
mA
mA
Maximum CMOS Standby
Current
40
40
40
40
40
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Pin Configurations
NC
NC
NC
VDDQ
VSS
NC
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NC
BYTE B
BYTE A
VDD
100-pin TQFP
CY7C1327G
NC
VSS
VDD
ZZ
DQB
DQB
VDDQ
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
VSS
VDDQ
NC
NC
NC
NC
NC
NC
Document #: 38-05519 Rev. *A
Page 2 of 18
PRELIMINARY
CY7C1327G
Pin Configurations
119-ball BGA
2
1
3
A
4
5
6
A
7
VDDQ
NC
A
ADSP
ADSC
VDD
A
VDDQ
NC
A
B
C
D
E
F
CE2
A
A
A
CE3
A
NC
A
A
NC
DQB
NC
NC
VSS
VSS
VSS
BWB
VSS
NC
VSS
NC
VSS
VSS
VSS
Vss
VSS
NC
VSS
DQPA
NC
NC
DQB
NC
DQA
VDDQ
DQA
NC
CE1
OE
VDDQ
NC
DQA
NC
G
H
J
DQB
NC
ADV
DQB
VDDQ
NC
DQA
VDD
NC
GW
VDD
CLK
VDD
DQB
VDDQ
DQA
K
L
M
N
DQB
VDDQ
DQB
NC
DQB
NC
Vss
VSS
VSS
NC
BWA
VSS
VSS
DQA
NC
NC
VDDQ
NC
BWE
A1
DQA
P
R
T
NC
NC
DQPB
A
VSS
MODE
A
A0
VDD
NC
NC
VSS
NC
A
NC
A
DQA
NC
NC
A
A
ZZ
VDDQ
NC
NC
NC
NC
VDDQ
U
Document #: 38-05519 Rev. *A
Page 3 of 18
PRELIMINARY
CY7C1327G
Pin Definitions
Name
I/O
Input-
Description
Address Inputs used to select one of the 256K address locations. Sampled at the rising edge
A0, A1, A
Synchronous of the CLK if ADSP or
ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1, A0
feed the 2-bit counter.
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
BWA,BWB
GW
Synchronous Sampled on the rising edge of CLK.
Input-
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
Synchronous write is conducted (ALL bytes are written, regardless of the values on BW[A:B] and BWE).
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
BWE
CLK
Synchronous asserted LOW to conduct a byte write.
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1
CE2
CE2
and
to select/deselect the device.
CE3
when a new external address is loaded.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
and to select/deselect the device. CE
ADSP is ignored if CE1 is HIGH. CE1 is sampled only
Input-
Synchronous
2 is sampled only when a new external address is
CE1
loaded.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE3
Input-
CE3
OE
Synchronous CE and CE to select/deselect the device.
Not connected for BGA. Where referenced, CE3 is
1
2
assumed active throughout this document for BGA. CE3 is sampled only when a new external
address is loaded.
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
Input-
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
ADV
Synchronous automatically increments the address in a burst cycle.
Input- Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
Synchronous asserted LOW, A is captured in the address registers. A1, A0 are also loaded into the burst counter.
When and are both asserted, only is recognized. is ignored when
ADSP
ADSP
is deasserted HIGH.
ADSP
ASDP
CE1
ADSC
ZZ
Input-
ZZ “sleep” Input, active HIGH. This input, when High places the device in a non-time-critical
Asynchronous “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or
left floating. ZZ pin has an internal pull-down.
Input-
Synchronous asserted LOW, A is captured in the address registers. A1, A0 are also loaded into the burst counter.
When and are both asserted, only is recognized.
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When
ADSC
ADSP
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
ADSP
ADSC
DQA,
DQB
I/O-
Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
DQPA,
DQPB
specified by “A” during the previous clock rise of the read cycle. The direction of the pins is
controlled by
. When
OE
is asserted LOW, the pins behave as outputs. When HIGH, DQs and
OE
DQP[A:B] are placed in a tri-state condition.
VDD
Power Supply Power supply inputs to the core of the device.
VSS
Ground
Ground for the device.
VDDQ
MODE
I/O Ground Ground for the I/O circuitry.
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. Mode Pin has an internal pull-up.
NC
No Connects. Not internally connected to the die.
Document #: 38-05519 Rev. *A
Page 4 of 18
PRELIMINARY
CY7C1327G
then the Write operation is controlled by BWE and BW[A:B]
signals. The CY7C1327G provides Byte Write capability that
is described in the Write Cycle Descriptions table. Asserting
the Byte Write Enable input (BWE) with the selected Byte
Write (BW[A:B]) input, will selectively write to only the desired
bytes. Bytes not selected during a Byte Write operation will
remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1327G supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Because the CY7C1327G is a common I/O device, the Output
Enable (OE) must be deserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and
(4) the appropriate combination of the Write inputs (GW, BWE,
and BW[A:B]) are asserted active to conduct a Write to the
desired byte(s). ADSC-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the memory array.
The ADV input is ignored during this cycle. If a global Write is
conducted, the data presented to DQ is written into the corre-
sponding address location in the memory core. If a Byte Write
is conducted, only the selected bytes are written. Bytes not
selected during a Byte Write operation will remain unaltered.
A synchronous self-timed Write mechanism has been
provided to simplify the Write operations.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:B]) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the Write
Because the CY7C1327G is a common I/O device, the Output
Enable (OE) must be deserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE.
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE1 is HIGH. The address presented to the address inputs (A)
is stored into the address advancement logic and the Address
Register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within tco if OE is active LOW. The only exception
occurs when the SRAM is emerging from a deselected state
to a selected state, its outputs are always tri-stated during the
first cycle of the access. After the first cycle of the access, the
outputs are controlled by the OE signal. Consecutive single
Read cycles are supported. Once the SRAM is deselected at
clock rise by the chip select and either ADSP or ADSC signals,
its output will tri-state immediately.
Burst Sequences
The CY7C1327G provides a two-bit wraparound counter, fed
by A1, A0, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Single Write Accesses Initiated by ADSP
Sleep Mode
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE1, CE2, CE3 are all asserted active. The address
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The Write signals (GW, BWE, and BW[A:B]) and
ADV inputs are ignored during this first cycle.
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ inputs is written into the corre-
sponding address location in the memory array. If GW is HIGH,
t
he “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
Document #: 38-05519 Rev. *A
Page 5 of 18
PRELIMINARY
CY7C1327G
Interleaved Burst Address Table (MODE =
Floating or VDD
)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
ZZ > VDD – 0.2V
Min.
Max.
40
Unit
mA
ns
tZZS
ZZ > VDD – 0.2V
2tCYC
tZZREC
tZZI
ZZ < 0.2V
2tCYC
0
ns
ZZ active to snooze current
This parameter is sampled
This parameter is sampled
2tCYC
ns
tRZZI
ZZ Inactive to exit snooze current
ns
Document #: 38-05519 Rev. *A
Page 6 of 18
PRELIMINARY
CY7C1327G
Truth Table[ 2, 3, 4, 5, 6]
Next Cycle
Unselected
Unselected
Unselected
Unselected
Unselected
Begin Read
Begin Read
Add. Used
CE2
X
X
L
ZZ
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
DQ
CE3
CE1
ADSP
ADSC
ADV
OE
WRITE
None
H
X
X
L
X
X
tri-state
tri-state
tri-state
tri-state
tri-state
tri-state
tri-state
tri-state
DQ
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
L
None
L
L
H
X
H
X
L
L
L
X
X
L
X
X
X
X
X
X
L
X
X
X
X
X
X
H
L
None
None
L
X
L
H
H
L
None
L
L
External
External
L
H
H
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
L
L
L
H
H
H
X
X
H
H
X
X
H
X
H
H
X
H
X
X
Continue Read Next
Continue Read Next
Continue Read Next
Continue Read Next
Suspend Read Current
Suspend Read Current
Suspend Read Current
Suspend Read Current
X
X
H
H
X
X
H
H
X
H
L
X
X
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
L
L
H
L
tri-state
DQ
L
H
H
H
H
H
H
X
H
H
H
H
X
H
L
tri-state
DQ
H
L
tri-state
DQ
Begin Write
Begin Write
Begin Write
Current
Current
External
X
X
X
X
X
X
X
X
tri-state
tri-state
tri-state
tri-state
tri-state
tri-state
tri-state
tri-state
L
L
Continue Write Next
Continue Write Next
Suspend Write Current
Suspend Write Current
X
H
X
H
X
X
X
X
X
X
L
L
L
L
ZZ “Sleep”
None
X
Truth Table for Read/Write[2]
Function
BWB
BWA
GW
BWE
Read
H
H
H
H
H
H
L
H
L
L
L
L
L
X
X
X
Read
H
H
L
H
L
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Bytes B, A
H
L
L
Write All Bytes
L
L
Write All Bytes
X
X
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BW , BW ) and BWE = L or GW = L. WRITE = H when all Byte write enable signals (BW , BW ),
A
B
A
B
BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the
signal.
is asynchronous and is not sampled with the clock.
OE
OE
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks
[A: B]
after the
or with the assertion of
. As a result,
ADSC
must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state.
is a
OE
OE
ADSP
don't care for the remainder of the write cycle.
6.
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when
is
OE
OE
.
is active (LOW)
inactive or when the device is deselected, and all data bits behave as output when
OE
Document #: 38-05519 Rev. *A
Page 7 of 18
PRELIMINARY
CY7C1327G
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.................................................... > 200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Range
Temperature
VDD
VDDQ
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V –5%
to VDD
DC Voltage Applied to Outputs
in tri-state ............................................ –0.5V to VDDQ + 0.5V
Industrial
–40°C to +85°C
DC Input Voltage....................................–0.5V to VDD + 0.5V
Electrical Characteristics Over the Operating Range [7, 8]
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Test Conditions
Min.
3.135
2.375
2.4
Max.
3.6
Unit
V
VDDQ
VDD
V
VOH
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
V
2.0
V
VOL
VIH
VIL
IX
Output LOW Voltage
Input HIGH Voltage[7]
Input LOW Voltage[7]
0.4
0.4
V
V
DDQ = 2.5V, VDD = Min., IOL = 1.0 mA
VDDQ = 3.3V
DDQ = 2.5V
V
2.0
1.7
VDD + 0.3V
VDD + 0.3V
0.8
V
V
V
VDDQ = 3.3V
–0.3
–0.3
–5
V
VDDQ = 2.5V
0.7
V
Input Load Current
except ZZ and MODE
GND ≤ VI ≤ VDDQ
5
µA
Input Current of MODE Input = VSS
Input = VDD
–30
–5
µA
µA
5
Input Current of ZZ
Input = VSS
Input = VDD
µA
30
5
µA
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
VDD Operating Supply VDD = Max., 4-ns cycle,250MHz
–5
µA
325
290
265
240
225
205
120
115
110
100
90
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Current
IOUT = 0 mA,
4.4-ns cycle,225MHz
5-ns cycle,200MHz
6-ns cycle,166MHz
7.5-ns cycle,133MHz
10-ns cycle,100MHz
4-ns cycle,250MHz
4.4-ns cycle,225MHz
5-ns cycle,200MHz
6-ns cycle,166MHz
7.5-ns cycle,133MHz
10-ns cycle,100MHz
All speeds
f = fMAX
1/tCYC
=
ISB1
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device
Deselected, VIN ≥ VIH or
VIN ≤ VIL
f = fMAX = 1/tCYC
80
ISB2
Automatic CE
Power-down
Current—CMOS Inputs VIN > VDDQ – 0.3V, f = 0
VDD = Max, Device
Deselected, VIN ≤ 0.3V or
40
Shaded areas contain advance information.
Notes:
7. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > -2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
8. T
: Assumes a linear ramp from 0v to V (min.) within 200ms. During this time V < V and V
< V
.
Power-up
DD
IH
DD
DDQ
DD
Document #: 38-05519 Rev. *A
Page 8 of 18
PRELIMINARY
CY7C1327G
Electrical Characteristics Over the Operating Range (continued)[7, 8]
Parameter
Description
Automatic CE
Power-down
Test Conditions
Min.
Max.
105
100
95
Unit
mA
mA
mA
mA
mA
mA
mA
ISB3
VDD = Max, Device
Deselected, or VIN ≤ 0.3V
4-ns cycle,250MHz
4.4-ns cycle,225MHz
5-ns cycle,200MHz
6-ns cycle,166MHz
7.5-ns cycle,133MHz
10-ns cycle,100MHz
All speeds
Current—CMOS Inputs or VIN > VDDQ – 0.3V
f = fMAX = 1/tCYC
85
75
65
ISB4
Automatic CE
VDD = Max, Device
45
Power-down
Current—TTL Inputs
Deselected, VIN ≥ VIH or
VIN ≤ VIL, f = 0
Thermal Resistance[9]
Parameter
Description
Test Conditions
TQFP Package
BGA Package Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA / JESD51.
TBD
TBD
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
TBD
TBD
°C/W
Capacitance[9]
Parameter
CIN
Description
Input Capacitance
Test Conditions
TQFP Package BGA Package Unit
TA = 25°C, f = 1 MHz,
DD = 3.3V.
DDQ = 3.3V
5
5
5
5
5
7
pF
pF
pF
V
V
CCLK
Clock Input Capacitance
Input/Output Capacitance
CI/O
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
OUTPUT
90%
10%
Z = 50Ω
0
10%
R = 50Ω
L
GND
5 pF
R = 351Ω
≤ 1ns
≤ 1ns
V = 1.5V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
5 pF
R =1538Ω
≤ 1ns
≤ 1ns
V = 1.25V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Notes:
9. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05519 Rev. *A
Page 9 of 18
PRELIMINARY
CY7C1327G
Switching Characteristics Over the Operating Range[14, 15]
250 MHz
225 MHz
200 MHz
166 MHz
133 MHz
100 MHz
Parameter
Description
Min. Max Min. Max Min. Max Min. Max Min. Max Min. Max Unit
tPOWER
VDD(Typical) to the first[10]
1
1
1
1
1
1
ms
Clock
tCYC
tCH
Clock Cycle Time
Clock HIGH
4.0
1.7
1.7
4.4
2.0
2.0
5.0
2.0
2.0
6.0
2.5
2.5
7.5
3.0
3.0
10
3.5
3.5
ns
ns
ns
tCL
Clock LOW
Output Times
tCO
Data Output Valid After CLK
Rise
2.6
2.6
2.8
3.5
4.0
4.5 ns
ns
tDOH
Data Output Hold After CLK
Rise
Clock to Low-Z[11, 12, 13]
Clock to High-Z[11, 12, 13]
1.0
0
1.0
0
1.0
0
1.5
0
1.5
0
1.5
0
tCLZ
ns
4.5 ns
4.5 ns
ns
tCHZ
tOEV
tOELZ
2.6
2.6
2.6
2.6
2.8
2.8
3.5
3.5
4.0
4.5
OE LOW to Output Valid
LOW to Output Low-Z[11,
0
0
0
0
0
0
OE
12, 13]
OE HIGH to Output High-Z[11,
tOEHZ
2.6
2.6
2.8
3.5
4.0
4.5 ns
12, 13]
Set-up Times
tAS
Address Set-up Before CLK
Rise
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
tADS
,
ADSC ADSP Set-up Before
CLK Rise
tADVS
tWES
1.2
1.2
1.2
1.2
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ADV Set-up Before CLK Rise
Set-upBefore 1.2
GW, BWE, BWX
CLK Rise
tDS
Data Input Set-up Before CLK 1.2
Rise
1.2
1.2
1.2
1.2
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
tCES
Chip Enable Set-Up Before
CLK Rise
1.2
Hold Times
tAH
Address Hold After CLK Rise 0.3
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
tADH
0.3
,
Hold After CLK
ADSP ADSC
Rise
tADVH
tWEH
0.3
0.3
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ADV Hold After CLK Rise
,
,
GW BWE BWX Hold After
CLK Rise
tDH
Data Input Hold After CLK
Rise
0.3
0.3
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
tCEH
Chip Enable Hold After CLK
Rise
Shaded areas contain advance information.
Notes:
10. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V (minimum) initially before a read or write operation
DD
POWER
can be initiated.
11. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
12. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
13. This parameter is sampled and not 100% tested.
14. Timing references level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V on all data sheets.
DDQ
DDQ
15. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05519 Rev. *A
Page 10 of 18
PRELIMINARY
CY7C1327G
Switching Waveforms
Read Cycle Timing[16]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,
BW[A:B]
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV
suspends
burst.
t
t
OEV
CO
t
t
OEHZ
t
OELZ
t
CHZ
DOH
t
CLZ
t
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A1)
Data Out (Q)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Notes:
16. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
17.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
LOW.
[A:B]
Document #: 38-05519 Rev. *A
Page 11 of 18
PRELIMINARY
CY7C1327G
Switching Waveforms (continued)
Write Cycle Timing[16, 17]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BW[A :B]
t
t
WEH
WES
GW
CE
t
t
CEH
CES
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
DH
DS
Data In (D)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
t
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON’T CARE
UNDEFINED
Document #: 38-05519 Rev. *A
Page 12 of 18
PRELIMINARY
CY7C1327G
Switching Waveforms (continued)
Read/Write Cycle Timing[16, 18, 19]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE,
BW[A:B]
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back READs
Single WRITE
BURST READ
Back-to-Back
WRITEs
DON’T CARE
UNDEFINED
Notes:
18.
19.
.
The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by
GW is HIGH.
ADSP or ADSC
Document #: 38-05519 Rev. *A
Page 13 of 18
PRELIMINARY
CY7C1327G
Switching Waveforms (continued)
ZZ Mode Timing [20, 21]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Ordering Information
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
250
CY7C1327G-250AXC
CY7C1327G-250BGC
CY7C1327G-250BGXC
CY7C1327G-250AXI
CY7C1327G-250BGI
CY7C1327G-250BGXI
CY7C1327G-225AXC
CY7C1327G-225BGC
CY7C1327G-225BGXC
CY7C1327G-225AXI
CY7C1327G-225BGI
CY7C1327G-225BGXI
CY7C1327G-200AXC
CY7C1327G-200BGC
CY7C1327G-200BGXC
CY7C1327G-200AXI
CY7C1327G-200BGI
CY7C1327G-200BGXI
A101
Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial
BG119 119-Ball BGA (14 x 22 x 2.4mm)
BG119 Lead-Free 119-Ball BGA (14 x 22 x 2.4mm)
A101
Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
Industrial
BG119 119-Ball BGA (14 x 22 x 2.4mm)
BG119 Lead-Free 119-Ball BGA (14 x 22 x 2.4mm)
225
200
A101
Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial
BG119 119-Ball BGA (14 x 22 x 2.4mm)
BG119 Lead-Free 119-Ball BGA (14 x 22 x 2.4mm)
A101
Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
Industrial
BG119 119-Ball BGA (14 x 22 x 2.4mm)
BG119 Lead-Free 119-Ball BGA (14 x 22 x 2.4mm)
A101
Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial
BG119 119-Ball BGA (14 x 22 x 2.4mm)
BG119 Lead-Free 119-Ball BGA (14 x 22 x 2.4mm)
A101
Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
Industrial
BG119 119-Ball BGA (14 x 22 x 2.4mm)
BG119 Lead-Free 119-Ball BGA (14 x 22 x 2.4mm)
Notes:
20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
21. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05519 Rev. *A
Page 14 of 18
PRELIMINARY
CY7C1327G
Ordering Information (continued)
Speed
Package
Name
Operating
Range
(MHz)
Ordering Code
CY7C1327G-166AXC
CY7C1327G-166BGC
CY7C1327G-166BGXC
CY7C1327G-166AXI
CY7C1327G-166BGI
CY7C1327G-166BGXI
CY7C1327G-133AXC
CY7C1327G-133BGC
CY7C1327G-133BGXC
CY7C1327G-133AXI
CY7C1327G-133BGI
CY7C1327G-133BGXI
CY7C1327G-100AXC
CY7C1327G-100BGC
CY7C1327G-100BGXC
CY7C1327G-100AXI
CY7C1327G-100BGI
CY7C1327G-100BGXI
Package Type
166
A101
Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial
BG119 119-Ball BGA (14 x 22 x 2.4mm)
BG119 Lead-Free 119-Ball BGA (14 x 22 x 2.4mm)
A101
Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
Industrial
BG119 119-Ball BGA (14 x 22 x 2.4mm)
BG119 Lead-Free 119-Ball BGA (14 x 22 x 2.4mm)
133
100
A101
Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial
BG119 119-Ball BGA (14 x 22 x 2.4mm)
BG119 Lead-Free 119-Ball BGA (14 x 22 x 2.4mm)
A101
Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
Industrial
BG119 119-Ball BGA (14 x 22 x 2.4mm)
BG119 Lead-Free 119-Ball BGA (14 x 22 x 2.4mm)
A101
Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial
BG119 119-Ball BGA (14 x 22 x 2.4mm)
BG119 Lead-Free 119-Ball BGA (14 x 22 x 2.4mm)
A101
Lead-Free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
Industrial
BG119 119-Ball BGA (14 x 22 x 2.4mm)
BG119 Lead-Free 119-Ball BGA (14 x 22 x 2.4mm)
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Lead-Free BG package will be
available in 2005
Document #: 38-05519 Rev. *A
Page 15 of 18
PRELIMINARY
CY7C1327G
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Document #: 38-05519 Rev. *A
Page 16 of 18
PRELIMINARY
CY7C1327G
Package Diagrams (continued)
119-Lead BGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark
of IBM Corporation. All product and company names mentioned in this document may be trademarks of their respective holders.
Document #: 38-05519 Rev. *A
Page 17 of 18
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
CY7C1327G
Document History Page
Document Title: CY7C1327G 4-Mbit (256K x 18) Pipelined Sync SRAM
Document Number: 38-05519
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
224367
278513
See ECN
See ECN
RKF
VBL
New Data Sheet
*A
In Ordering Info section, Changed TQFP to PB-Free TQFP
Added PB-Free BG package.
Document #: 38-05519 Rev. *A
Page 18 of 18
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